Multiplexer

Multiplexing is the generic term used to designate the operation of sending one or more analogue or digital signals over a common transmission line at dissimilar times or speeds and as such, the scheme we use to do just that is called a Multiplexer. In digital electronics, multiplexers are similarly known as data selectors as they can "select" each input line, are made from individual Analogue Switches encased in a single IC package as conflicting to the "mechanical" type selectors such as standard conservative switches and relays. In today era, reversibility has become essential part of digital world to make digital circuits more efficient. In this paper, we have proposed a new method to reduce quantum cost and power for various multiplexers. The results are simulated in Xilinx by using VHDL language.

Digital signal processing applications often use major mathematical operations such as multiplication, which consume more power and time. Operations like Fast Fourier Transform, Convolution and correlation depends heavily on a large number of multiplications. There are many techniques available to perform multiplications. One such technique is logarithmic multiplication. logarithmic multiplication is achieved by adding the binary logarithms of two numbers and deriving the antilog of the result. In this paper, an efficient algorithm for logarithmic multiplication is presented with the use of adders, decoders, multiplexers and a few combinational circuits that effectively reduce the power and area of the multiplier

This paper presents a modified design of Area-Efficient Low power Carry Select Adder (CSLA) Circuit. In digital adders, the speed of addition is limited by the time required to propagate a carry through the adder. The sum for each bit position in an elementary adder is generated sequentially only after the previous bit position, the speed of addition is limited by the time required to transmit a carry through the adder. Carry
select adder processors and systems. Has been summed and a carry propagated into the next position. The  major speed limitation in any adder is in the production of carries.

The 1-bit full adder circuit is a very important component in the design of application specific integrated circuits. This paper presents a novel low-power multiplexer-based 1-bit full adder that uses 12 transistors (MBA-12T). In addition to reduced transition activity and charge recycling capability, this circuit has no direct connections to the power-supply nodes, leading to a noticeable reduction in short-current power consumption. Intensive HSPICE simulation shows that the new adder has more than 26% in power savings over conventional 28-transistor CMOS adder and it consumes 23% less power than 10-transistor adders (SERF [1] and 10T [4]) and is 64% faster.

Multi-degree implementations of the reconfigurable optical add-drop multiplexer (ROADM) are analyzed in terms of in-band crosstalk performance with an emphasis on the reduction in the number of wavelength selective switches used in the module. It is shown experimentally that an 8-degree ROADM using the wavelength selective switches for channel adding and optical splitters for channel dropping performs closely to one that uses switches for both operations. A new modular architecture based on the wavelength selective switches is proposed for implementations applicable to large degree nodes. Performance analysis of this architecture indicates node scalability to 256 degree with crosstalk-induced power penalties below 0.5 dB.

Penulisan makalah ini bertujuan untuk memaparkan penjelasan mengenai contoh  implementasi atau peranan multiplexer dan demultiplexer terhadap industri teknologi. Adapun latar belakang dibuatnya makalah ini adalah karena sulitnya untuk mencari dan mengakses materi mengenai multiplexer dan demultiplexer dalam bentuk Bahasa Indonesia. Adapun metode yang kami gunakan dalam menyusun makalah ini adalah dengan mengumpulkan data-data yang bersumber dari e-book berbahasa Indonesia maupun berbahasa Asing. Pada makalah ini lebih membahas  tentang multiplexer dan demultiplexer itu sendiri, apa yang membedakan antara multiplexer dan demultiplexer. Selain itu, pokok dari bahasan makalah ini yaitu, implementasi atau peranan multiplexer dan demultiplexer dalam industri teknologi berupa sistem, aplikasi dan CMOS analog.
Kata kunci: multiplexer, demultiplexer, peranan, implementasi, teknologi


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We consider non cooperative games in all-optical networks where users share the cost of the used ADM switches for realizing given communication patterns. We show that the two fundamental cost sharing methods, Shapley and Egalitarian, induce polynomial converging games with price of anarchy at most 5/3, regardless of the network topology. Such a bound is tight even for rings. Then, we show that if collusion of at most k players is allowed, the Egalitarian method yields polynomially converging games with price of collusion between ${{3}\over{2}}$ and ${{3}\over{2}}+{{1}\over{k}}$ . This result is very interesting and quite surprising, as the best known approximation ratio, that is ${{3}\over{2}}+\epsilon$ , can be achieved in polynomial time by uncoordinated evolutions of collusion games with coalitions of increasing size. Finally, the Shapley method does not induce well defined collusion games, but can be exploited in the definition of local search algorithms with local optima arbitrarily close to optimal solutions. This would potentially generate PTAS, but unfortunately the arising algorithm might not converge. The determination of new cost sharing methods or local search algorithms reaching a compromise between Shapley and Egalitarian is thus outlined as being a promising and worth pursuing investigating direction.

Bu proje amaç takılan bir entegrenin sağlamlığını test etmektir.Devrede test kıyaslama olarak değilde durumlara göre çıkışlar kontrol edilerek yapılmıştır.

3 girişli veya kapısının logic kapılar aracılığıyla test devresi - 3 input or gate stability control circuit via logic gates

A variety of optical transducers is presented in the literature based on just a few given optical principles. Based on principles like microrefractometry and -reflectivity, a classification is approached, especially for sensors used in bioanalytics. Two methods are discussed in detail, which are favoured in the group known as integrated optical Mach-Zehnder interferometers and reflectometric interference spectroscopy (RIfS) . Recent applications as chemical sensors and biochemical probes in the fields of hydrocarbon monitoring and immunoreactions are demonstrated. Perspectives in routine interaction analysis, microstructuring of devices, direct detection of low-molecular-weight ligands, and parallel high-throughput screening are discussed. . ' Plenary lecture. 0925-4005/97/$17.00 0 1997 Elsevier Science S.A. All rights reserved Prrs0925-4005(97)00042-7 2 A. Brecht, G. Gauglitz/Sensors

Since multiplexer (MUX) is one of the important
components of communication system, to increase the efficiency
of data transmission, to utilize the vast memory space of a
computer in an effective way and to convert parallel form of data
into serial form in telecommunication networks an efficient
design of low power -delay MUX is required. Hence in this work,
a basic 2:1 MUX is designed using various CMOS logic families
such as Static CMOS logic, Pseudo NMOS logic, Domino logic
and Dual-Rail Domino logic to identify the best logic family
suitable for the design of higher levels of MUX. The
implementation is done in VLSI technology as it has features like
small size, low cost, high operating speed and low power. The
performance analysis of the MUX using various CMOS logic
families are conducted using VLSI back- hand tool: CADENCE
VIRTUOSO SCHEMATIC EDITOR 6.1 at 180nm.The results
obtained show that, the Domino logic based 2:1 MUX is the most
efficient design because the average power consumption is
20.06% and PDP(Power Delay Product) is 20.1% lesser than that
of other logic familes. But trade-offs are inferred between
Domino logic and Static CMOS logic which can be neglected on
considering the overall performance. Since the Domino logic
outperforms the other logic families, this work suggests that any
higher level MUX with low power-delay and PDP can be
achieved using Domino logic.

Adders form an almost obligatory component of every contemporary integrated circuit. The prerequisite of the adder is that it is primarily fast and secondarily efficient in terms of power consumption and chip area. Therefore, careful optimization of the adder is of the greatest importance. This optimization can be attained
in two levels; it can be circuit or logic optimization. In circuit optimization the size of transistors are manipulated, where as in logic optimization the Boolean equations are rearranged (or manipulated) to optimize speed, area and power consumption. This paper focuses the optimization of adder through technology independent mapping. The work presents 20 different logical construction of 1-bit adder cell in CMOS logic and its performance is analyzed in terms of transistor count, delay and power dissipation. These performance issues are analyzed through Tanner EDA with TSMC MOSIS 250nm technology. From this analysis the optimized equation is chosen to construct a full adder circuit in terms of multiplexer. This logic optimized multiplexer based adders are incorporated in selected existing adders like ripple carry
adder, carry look-ahead adder, carry skip adder, carry select adder, carry increment adder and carry save adder and its performance is analyzed in terms of area (slices used) and maximum combinational path delay as a function of size. The target FPGA device chosen for the implementation of these adders was Xilinx ISE 12.1 Spartan3E XC3S500-5FG320. Each adder type was implemented with bit sizes of: 8, 16, 32, 64 bits. This variety of sizes will provide with more insight about the performance of each adder in terms of area and delay as a function of size.

Problem statement: Combinational circuits are used in computers for generating binary control decisions and for providing digital components for data processing. Approach: The use of combinational circuits and logic gates to control other circuits was discussed. Different systems that use logic gates, multiplexers, decoders and encoders to control different circuits were presented. This study presented a design and implementation of some combinational circuits such as a decoder, an encoder, a multiplexer, a bus system and read/write memory operations. Results: When we connected some types of combinational circuits to the inputs/outputs of digital circuit, these combinational circuits can help us to manage and flow a different types of control signals through a large digital circuit. Conclusion: Many combinational circuits had a good function which can be used for controlling different parts of any digital system and they produce a suitable way to transfer a control signals between different digital components of any large digital system.

In this paper we present two CMOS LNA blocks during test would be the design objective. On the other hand, designed for integration with other RF frontend blocks for on-being familiar with RF IC design one can realize the existing chip test. Both of them are variants of the source degenerated tradeoffs between the test functionality and the chip LNA with embedded switches and/or a multiplexer, optimized performance required in a normal operation mode. Another with respect to their function and location. We discuss their key factor is usually the chip area overhead. functionality and performances in terms of test mode and the normal operation mode. The circuits are designed for 0.35pm

In this study a four-channel multiplexer of Dense Wavelength Division Multiplexer (DWDM) has been designed and stimulated by one-dimensional photonic crystal structure to be used in optical telecommunication purposes of C band. It has been formed of both Germanium and Silicone crystals based on grading method of refraction factor profile (Apodization). In this process by means of Transfer Matrix Method (TMM), light refraction theorem and defect exertion, the effect of radiated optical signal angle to studied structure and optical multiplexer has been made by too narrow channels.

This paper shows an effective design of circuits such as 2:1, 4:1 multiplexers, 2:4 decoder and a full subtractor using reversible gates. This paper also evaluates number of reversible gates used and garbage output implementing each combinational circuit.

This correspondence describes a new type of carry-skip adder, which can be faster than the conventional two-level carry-skip adders. A way to design optimum adders of this new type is described. In optimum adders of our type, the sizes of the sections of bit positions are bimodal, but the sizes of the blocks in each section are unimodal, unlike the bimodal block sizes in Guyot et al.'s traditional two-level carry-skip adders. A 60-b 2-pm CMOS adder of our type is designed. This adder's simulated delay is approximately 12.6 ns.

Power consumption has emerged as a primary design constraint for integrated circuits (ICs). In the Nanometer technology regime, leakage power has become a major component of total power . Full adder is the basic functional unit of an ALU. The power consumption of a processor is lowered by lowering the power consumption of an ALU, and the power consumption of an ALU can be lowered by lowering the power consumption of Full adder. So the full adder designs with low power characteristics are becoming more popular these days. In this paper we are going to design four different types of Full adder these are applied to 32-bit RCA .The four designs will be developed using Verilog HDL evaluating the performance using Cadence.

When variable bit rate sources are multiplexed in an ATM network, there arise queues with a particular form of correlated arrival process. We analyze such queues by exploiting a result expressing the distribution of work in system of the G / G / l queue originally derived by BeneS. We provide a simple alternative demonstration of this result and extend it to the case of fluid input systems. The result is applied first to a queue where the arrival process is a superposition of periodic sources (the E D , / D / 1 queue), and then to a variable input rate constant output rate fluid system. The latter is shown to model the so-called burst component of the considered superposition queueing process. The difference between this and the real queue, the cell component, can he evaluated by means of the results obtained for the C D , / D / l queue. The relative importance of these two components is explored with reference to the particular case of a superposition of onloff sources. 0733-87 16/9 I /0400-0378$0 I .OO 0 199 1 IEEE .~

In this paper, we demonstrate the development of advanced 3-D low-temperature cofired ceramic (LTCC) system-on-package (SOP) passive components for compact, low cost millimeter-wave wireless front-end modules. Numerous miniaturized easy-to-design passive circuits that can be used as critical building blocks for millimetre-wave SOP modules have been hereby realized with high performance and high integration potential. One miniaturized slotted patch resonator has been designed by the optimal use of vertical coupling mechanism and transverse cuts and has been utilized to realize compact duplexers (39.8 GHz/59 GHz) and 3 and 5 poles band pass filters by the novel 3D (vertical and parallel) deployment of single-mode patch resonators. Measured results agree very well with the simulated data. Also, one multiplexing filter, called directional channelseparation filter, that can be used in mixer applications shows insertion loss of <3dB over the bandpass frequency band and a rejection ~ 25dB at around 38.5GHz over the band rejection section. LTCC fabrication limitations have been overcome by using vertical coupling mechanisms to satisfy millimetre-wave design requirements. Last, a double fed cross-shaped microstrip antenna has been designed for the purpose of doubling the data throughput by means of a dual-polarized wireless channel, covering the band between 59-64 GHz. This antenna can be easily integrated into a wireless millimeterwave link system. Index Terms -patch resonator, duplexer, low-temperature co-fired ceramic (LTCC), system-on-package (SOP), directional filter, multiplexing, 3D/vertical integration, microstrip antenna, dual polarization, millimeter-wave (mmW)

This paper reports the design, fabrication, and testing of a Micro-opto-mechanical grating switch driven by electrostatic actuator for fiber-optic communication applications. It consists of two bounded silicon wafers. One input fiber with a hemispherical lens at its end and three photodetectors are mounted on the upper wafer. A movable platform with two gratings and one mirror are fabricated on the lower wafer. When the movable platform is at a certain position, the input beam can be split into three beams by the gratings. The reflectivity of the mirror is about 85% while the efficiency in the three different order is 29%, 26%, and 26%. The switching speed is about 500 ms. Details of the grating switching design, theoretical analysis, fabrication and experimental results are presented in this paper. q

Our work is motivated by the desire to design packet switches with large aggregate capacity and fast line rates. In this paper, we consider building a packet switch from multiple lower speed packet switches operating independently and in parallel. In particular, we consider a (perhaps obvious) parallel packet switch (PPS) architecture in which arriving traffic is demultiplexed over identical lower speed packet switches, switched to the correct output port, then recombined (multiplexed) before departing from the system. Essentially, the packet switch performs packet-by-packet load balancing, or inverse multiplexing, over multiple independent packet switches. Each lower speed packet switch operates at a fraction of the line rate . For example, each packet switch can operate at rate . It is a goal of our work that all memory buffers in the PPS run slower than the line rate. Ideally, a PPS would share the benefits of an output-queued switch, i.e., the delay of individual packets could be precisely controlled, allowing the provision of guaranteed qualities of service.

The 1-bit full adder circuit is a very important component in the design of application specific integrated circuits. This paper presents a novel low-power multiplexer-based 1-bit full adder that uses 12 transistors (MBA-12T). In addition to reduced transition activity and charge recycling capability, this circuit has no direct connections to the power-supply nodes, leading to a noticeable reduction in short-current power consumption. Intensive HSPICE simulation shows that the new adder has more than 26% in power savings over conventional 28-transistor CMOS adder and it consumes 23% less power than 10-transistor adders (SERF [1] and 10T [4]) and is 64% faster.

Infectious meningitis (IM) and/or infectious encephalitis (IE) can cause significant and irreversible damage to the central nervous system. Objective The main objective of the study was to identify a pathogen which causes IM or Meningoencephalitis (M/E) and evaluate the contribution of FilmArray (FA) M/E in patient management. Material and Method Twenty-one (21) cerebrospinal fluid (CSF) samples tested simultaneously using the FilmArray M/E and bacteria culture. Each sample was tested per the manufacturer's instructions.

The limitations related to CMOS such as power consumption and parasitic capacitance lead scientists to search for new technologies. Quantum-dot cellular automata (QCA) is a CMOS alternative technology that uses charges instead of voltage level for binary representation. In QCA, many metrics are used for circuit differentiation such as delay, complexity and area. In this work, a new simple block of 2:1 QCA-Multiplexer is proposed. The proposed block is more efficient than previous designs by 43%, 53%, 50% and 72% in terms of area, complexity, delay and cost. QCADesigner software is used to design and verify the proposed circuit.

Conventional scan design imposes considerable area and delay overheads. To establish a scan chain in the test mode, multiplexers at the inputs of flip-flops and scan wires are added to the actual design. We propose a low-overhead scan design methodology that employs a new test-point insertion technique. Unlike the conventional test-point insertion, where test points are used directly to increase the controllability and observability of the selected signals, the test points are used here to establish scan paths through the functional logic. The proposed technique reuses the functional logic for scan operations; as a result, the design-fortestability overhead on area or timing can be minimized. We show an algorithm that uses the new test-point insertion technique to reduce the area overhead for the full-scan design. We also discuss its application to the timing-driven partial-scan design.

Digital signal processing applications often use major mathematical operations such as multiplication, which consume more power and time. Operations like Fast Fourier Transform, Convolution and correlation depends heavily on a large number of multiplications. There are many techniques available to perform multiplications. One such technique is logarithmic multiplication. logarithmic multiplication is achieved by adding the binary logarithms of two numbers and deriving the antilog of the result. In this paper, an efficient algorithm for logarithmic multiplication is presented with the use of adders, decoders, multiplexers and a few combinational circuits that effectively reduce the power and area of the multiplier

Rangkaian kombinasional terdiri dari gerbang logika yang memiliki output yang selalu tergantung pada kombinasi input yang ada. Rangkaian kombinasional melakukan operasi yang dapat ditentukan secara logika dengan memakai sebuah fungsi boolean.Salah satu dari rangkaian kombinasional yaitu rangkaian Multiplexer, Multiplexer digunakan untuk membagi kapasitas saluran komunikasi tingkat-rendah menjadi beberapa saluran logik tingkat-tinggi, masing-masing satu untuk setiap sinyal pesan atau aliran data yang ingin disalurkan. Sebuah proses ini di sebut Multiplexing.

Polymer Optical Fibres (POFs) show clear advantages compared to copper and glass fibres. In essence, POFs are inexpensive, space-saving and not susceptible to electromagnetic interference. Thus, the usage of POFs have become a reasonable alternative in short distance data communication. Today, POFs are applied in a wide number of applications due to these specific advantages. These applications include automotive communication systems and in-house-networks. State-of-the-art is to transmit data with only one channel over POF, this limits the bandwidth. To solve this problem, an integrated MUX/DEMUX-element for WDM over POF is designed and developed to use multiple channels. This integration leads to low costs, therefore this component is suitable for mass market applications. The fundamental idea is to separate the chromatic parts of the light in its monochromatic components by means of a grating based on an aspheric mirror. Due to the high NA of the POF the setup has to be designed in a 3D-approach. Therefore this setup cannot be compared with the planar solutions available on market, they would result high losses in the 3 rd dimension. To achieve a fast and optimized design an optical simulation program is used. Particular attention has to be paid to the design of the POF as a light source in the simulation program and the optimisation of the grating. The following realization of the demultiplexer is planed to be done with injection molding. This technology offers easy and very economical processing. These advantages make this technology first choice for optical components in the low-cost array.

Adders are the basic building blocks in digital integrated circuit based designs. Ripple Carry Adders (RCA) are usually preferred for addition of two multi-bit numbers as these RCAs offer fast design time among all types of adders. However, RCAs are slowest adders as every full adder must wait till the carry is generated from previous full adder. On the other hand, Carry Look Ahead (CLA) adders are faster adders, but they required more area. The Carry Select Adder(CSLA) is a compromise on between the RCA and CLA in term of area and delay. This paper presents High Speed Carry Select Adder by replacing Ripple Carry Adder with Kogge-Stone(KSA) Parallel Prefix Adder. Based on this modification 8, 16, 32 and 64-bit High-Speed Proposed Carry Select Adder (PCSLA) architectures have been developed and compared with the Regular and Modified CSLA architectures in Uniform and Variable Block Size. This work estimates the performance of the proposed designs in terms of Maximum combinational delay, Logic delay and Routing delay which are designed and implemented in Xilinx ISE tool.

This paper describes our approach toward advanced customer access network through the development of an optical cross add and drop multiplexer (OXADM) switch. The OXADM focuses on providing survivability through restoration against failure by means of dedicated and shared protection that is applied in FTTH-PON. No degradation in the BER was observed, as confirmed by a comparison of the simulation results with those obtained from system without restoration function in ideal condition to prove the system feasibility.Another feature is the high speed restoration achieved by automatic re-routing using fiber status monitoring. Each OXADM has a node controller which receives reports on the status periodically from Access Control System (ACS). When a failure is detected, ACS will send a command to an OXADM which is the activated. The proposed restoration system is the first of its kind which covers the survivability in the drop section of FTTH access network.

Digital signal processing applications often use major mathematical operations such as multiplication, which consume more power and time. Operations like Fast Fourier Transform, Convolution and correlation depends heavily on a large number of multiplications. There are many techniques available to perform multiplications. One such technique is logarithmic multiplication. logarithmic multiplication is achieved by adding the binary logarithms of two numbers and deriving the antilog of the result. In this paper, an efficient algorithm for logarithmic multiplication is presented with the use of adders, decoders, multiplexers and a few combinational circuits that effectively reduce the power and area of the multiplier.

Multiplexer adalah sebuah perangkat yang dapat menyalurkan beberapa jalur data ke satu jalur luaran. Multiplexer mempunyai satu atau banyak sinyal masukan yang telah terhubung pada masukannya. Pemilihan saluran masukan dilakukan oleh sinyal kontrol. Suatu multiplexer dengan jumlah 2n saluran masukan memerlukan n sinyal kontrol. Multiplexer (MUX) atau selector data adalah suatu rangkaian logika yang dapat menerima satu hingga banyak input data, dan untuk suatu saat tertentu hanya mengizinkan satu data input masuk dan melewati output, yang diatur oleh input selektor. Oleh karena itu, MUX memiliki fungsi sebagai sebuah pengontrol digital.

This paper presents two proposed circuits that employ a footer transistor that is initially OFF in the evaluation phase to reduce leakage and then turned ON to complete the evaluation. Also a new circuit is added using a NAND gate that improves the performance more than 10% -15% compared with latter proposed circuit. According to simulations in a predictive 70 nm process, the proposed circuit increases noise immunity by more than 26X for wide OR gates and shows performance improvement of up to 20% compared to conventional domino logic circuits. The proposed circuit reduces the contention between keeper transistor and NMOS evaluation transistors at the beginning of evaluation phase. High fan-in comparators and multiplexers demonstrate high noise immunity compared with previous proposed works.

The paper attempts to clarify some issues concerning the use, and usefulness, of the packet-speech multiplexer. An accurate mathematical analysis is used to find the trade-off between delay and packet loss. The subjective effect of delay and packet loss is determined using data from our own, and published, conversation tests. It is found that the multiplexer will operate most efficiently if queueing delay is limited, with a large delay limit for heavy traffic conditions and a small delay limit for light traffic conditions. The improvement in TASI (time assignment speech interpolation) advantage gained through allowing delay is small, and it is concluded that the packetspeech multiplexer is unlikely to be used purely for its buffering facility. However, its ability to multiplex speech channels where the information rate is continually varying may be of significance for the next generation of speech coders.

We propose a compact matrix-switch-based hierarchical optical cross-connect (HOXC) architecture that effectively handles the colorless waveband add/drop ratio restriction so as to realize switch scale reduction. In order to implement the colorless waveband add/drop function, we develop a wavelength MUX/DMUX that can be commonly used by different wavebands. We prove that the switch scale of the proposed HOXC is much smaller than that of conventional single-layer optical cross-connects (OXCs) and a typical HOXC. Furthermore, we introduce a prototype system based on the proposed architecture that utilizes integrated novel wavelength MUXs/DMUXs. Transmission experiments prove its technical feasibility.

Ž. Multiplexers have been fabricated using high-temperature superconductors HTS. Superconducting YBa Cu O films 2 3 7 yx Ž. were deposited on MgO, a substrate by using pulsed laser deposition PLD. A conventional photolithographic method was used to produce the superconducting multiplexer pattern. Epitaxial YBCO films with c-axis orientation were grown on MgO Ž. 100 substrates. Superconducting transition temperatures were measured at 89 K. Simulated results of the superconducting multiplexer consisting of hairpin type filters show an insertion loss of 1.2 dB. The measured frequency response of superconducting multiplexer was compared with the simulation results.

We present a Built-In Self-Test (BIST) approach able to detect and accurately diagnose all single and practically all multiple faulty programmable logic blocks (PLBs) in Field Programmable Gate Arrays (FPGAs) with maximum diagnostic resolution. Unlike conventional BIST, FPGA BIST does not involve any area overhead or performance degradation. We also identify and solve the problem of testing configuration multiplexers, that was either ignored or incorrectly solved in most previous work. We introduce the first diagnosis method for multiple faulty PLBs; for any faulty PLB, we also identify its internal faulty modules or modes of operation. Our accurate diagnosis provides the basis for both failure analysis used for yield improvement and for any repair strategy used for fault-tolerance in reconfigurable systems. We present experimental results showing detection and identification of faulty PLBs in actual defective FPGAs. Our BIST architecture is easily scalable.