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2009, Journal of Computer Science
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4 pages
1 file
Problem statement: Combinational circuits are used in computers for generating binary control decisions and for providing digital components for data processing. Approach: The use of combinational circuits and logic gates to control other circuits was discussed. Different systems that use logic gates, multiplexers, decoders and encoders to control different circuits were presented. This study presented a design and implementation of some combinational circuits such as a decoder, an encoder, a multiplexer, a bus system and read/write memory operations. Results: When we connected some types of combinational circuits to the inputs/outputs of digital circuit, these combinational circuits can help us to manage and flow a different types of control signals through a large digital circuit. Conclusion: Many combinational circuits had a good function which can be used for controlling different parts of any digital system and they produce a suitable way to transfer a control signals between different digital components of any large digital system.
2012
This is the paper presenting a novel method for defining, analyzing and implementing the basic combinational circuitry with less number of ternary multiplexers. Multilplexer is used as basic building block to realize all the combinational and sequential circuitry providing complete, concise, implementation-free description of the ternary function involved. This shows the potential of VHDL modeling and simulation which can be applied to Ternary switching circuits for verifying its functionality and timing specifications. This is the method which is used in analyzing the complex ternary functions and reduction of gate count
The foundations for the design of digital logic circuits were established in the preceding chapters. The elements of Boolean algebra (two-element " switching algebra ") and how the operations in Boolean algebra can be represented schematically by means of gates (primitive devices) were presented in Chapter 2. How switching expressions can be manipulated and represented in different ways was the subject of Chapter 3, which also presented various ways of implementing such representations in a variety of circuits using primitive gates. With all of the tools for the purpose now in hand, we will be concerned in this chapter with the design of more complex logic circuits. Circuits in which all outputs at any given time depend only on the inputs at that time are called com-binational logic circuits. The design procedures will be illustrated with important classes of circuits that are now universal in digital systems. The approach taken is to examine the tasks that a combinational logic circuit is intented to perform and then identify one or more circuits that can perform the task. One circuit may have some specific advantages over others, but it may also have certain deficiencies. Often one factor can be improved, but only at the expense of others. Some important factors are speed of operation, complexity or cost of hardware, power dissipation, and availability in prefabricated units. We will take up a number of different operations that are useful in different contexts and show how appropriate circuits can be designed to carry out these operations.
Proceedings of 13th International Conference on Computer and Information Technology (ICCIT 2010), 2010
A neural representation of combinational logic circuit is proposed, called ‘Logical Neural Network’ (LNN). LNN is a feed-forward neural network (NN) where the weights of the network indicate the connections of digital circuit. The logic operations of the circuit such as AND, OR, NOR etc are performed with the neurons of LNN. A modification of Simple Genetic Algorithm (mSGA) is applied to design and optimize the LNN for a given truth table. The proposed technique is experimentally studied on four bit parity checker, two bit multiplexer, two bit full adder, full subtractor, and two bit multiplier circuits. LNN is compared with conventional ‘Cell Array’ method. LNN outperforms the Cell Array method in terms of number of required gates.
Power dissipation is the major aspect which is effecting the digital circuits. By implementing the self resetting logic to the digital circuit, the power dissipation is drastically reduced. In the VLSI Design this low power technique is very advanced for DSP applications. The dynamic circuits are becoming increasingly popular because of the speed advantage over static CMOS logic circuits; hence they are widely used today in high performance and low power circuits. Self-resetting logic is a commonly used piece of circuitry that can be found in use with memory arrays as word line drivers. Self resetting logic implemented in dynamic logic families have been proposed as viable clock less alternatives. The combinational logic is a type of digital logic which is implemented by Boolean circuits, where the output is a pure function of the present input only. This is in contrast to sequential logic, in which the output depends not only on the present input but also on the history of the input. In this paper mainly the self resetting logic is applied for the different combinational circuits and the analysis is done very clearly. By implementing this low power technique for different logic circuits and adders, by comparison with DYNAMIC and SRCMOS logic's power dissipation is drastically reduced up to 35% compared with CMOS logic circuits and observations are tabulated.
—This paper presents a new approach to the design of combinational digital circuits with multiplexers using Evolutionary techniques. Genetic Algorithm (GA) is used as the optimization tool. Several circuits are synthesized with this method and compared with two design techniques such as standard implementation of logic functions using multiplexers and implementation using Shannon's decomposition technique using GA. With the proposed method complexity of the circuit and the associated delay can be reduced significantly.
Objective of this paper is to present historiography of logic switching circuits. The research mainly focuses on chronological development and application of logic in the field of electronic and computer applications. This paper briefly discussed on the basic needs of logic synthesis and also discuss few interesting facts and design consideration regarding logic synthesis. It also enhances student’s deep understanding of different logic function minimization technique during a lecture and practical implementation.
Aim: At the end of the course the student will be able to analyze, design, and evaluate digital circuits, of medium complexity, that are based on SSIs, MSIs, and programmable logic devices.
This paper presents a novel method for defining, analyzing, testing and implementing the basic combinational circuitry with VHDL Simulator. This paper shows the potential of VHDL modeling and simulation that can be applied to Ternary switching circuits to verify its functionality and timing specifications. A novel method is brought out for implementing the basic combinational circuitry with minimum number of multiplexers. It also includes 1-bit and 2-bit position shifter and Barrel shifter. Method of coding is illustrated with respect to block diagram. An intention is to show how proposed simulator can be used to simulate MVL circuits and to evaluate system performance.
Radio and Electronic Engineer, 1980
Many algorithms have been suggested 1 " 5 in the past to design combinational logic circuits using multiplexers. An alternative method, based on the Boolean matrix approach, is suggested here. The method is simpler and faster compared to existing methods and can be easily programmed on a computer. Finally, the proper selection of multiplexers is suggested by applying simple empirical rules.
Digital circuits are called combinational if they are without memory: i.e. they have outputs that depend only on the present values of the inputs. Combinational circuits are generally consideration of as acyclic (i.e., feedforward) structures. However, cyclic circuits can be combinational [1]. Conventional recognized techniques in logic analysis and timing analysis of combinational circuits have limited themselves to acyclic combinational circuits since cyclic circuits cannot be analyzed in conventional method. The temporal behavior of a circuit depends on the delay values of the circuit elements, but its functional or logical behavior should not be dependent on the delay values. Cyclic combinational circuits have structural feedback; however there is no logical feedback. In cyclic combinational circuit the primary outputs is combinational even when some intermediate signals in the circuit are sequential [2]. A general attitude for the synthesis of multilevel combinational circuits with cyclic topologies gives major improvements
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