Decoder

These days complex numbers are represented in computer arithmetic using a divideand-conquer technique wherein the real part of the number is represented by a separate base-2 binary string and the imaginary part of the number is represented by a separate base-2 binary string. Then each binary string is treated separately to evaluate the result of any operation on the given complex number. Complex Binary Number System (CBNS) is (-1+j)-based binary number system which allows both real and imaginary components of the complex number to be collectively represented as single binary string. In this paper, we have presented two designs of nibble-size complex binary multiplier circuits (decoder-based, minimum-delay) and implemented them on various Xilinx FPGAs.

This paper considers the use of punctured quasiarithmetic (QA) codes for the Slepian-Wolf problem. These entropy codes are defined by finite state machines for memoryless and first-order memory sources. Puncturing an entropy coded bit-stream leads to an ambiguity at the decoder side. The decoder makes use of a correlated version of the original message in order to remove this ambiguity. A complete distributed source coding (DSC) scheme based on QA encoding with side information at the decoder is presented, together with iterative structures based on QA codes. The proposed schemes are adapted to memoryless and first-order memory sources. Simulation results reveal that the proposed schemes are efficient in terms of decoding performance for short sequences compared to well-known DSC solutions using channel codes.

This paper presents a novel implementation of the memorization system of the Non-Binary LDPC Decoder. The proposed approach relies on new implementations of STT-MRAM with power gating capabilities. A new data mapping has been defined to fit in with the physical dimensions of these implementations. The decoder adopting the devised memorization system has been compared to SRAM-based one which is used in almost all traditional decoders in order to demonstrate the feasibility of using power-gated MRAM. The obtained results show a significant reduction in the consumed energy by the memory reaching up to 78.45%.

NLP researchers face a dilemma: on one side, it is unarguably accepted that languages have internal structure rather than strings of words. On the other side, they nd it very di cult and expensive to write grammars that have g o o d c o verage of language structures. Statistical machine translation tries to cope with this problem by ignoring language structures and using a statistical models to depict the translation process. Most of the translation models are word-based. While the approach h a s a c hieved surprisingly good performance comparable to the best commercial systems, many questions remain in the machine translation community. Can the statistical word-based translation still perform well on language pairs with radically di erent linguistic structures? How w ould it function with less training data or with spoken languages? The thesis work investigated these questions. In summary, w ord-based alignment model is a major cause of errors in German-English statistical spoken language translation. To account for this problem, a structure-based alignment model is introduced. This new model takes advantages of a bilingual grammar inference algorithm, which can automatically acquire shallow phrase structures used by the model. The structure-based model can directly depict the structure di erence between English and German spoken languages. It also results in focused learning of word alignment, therefore it can alleviate the sparse data problem. The structurebased model achieved 11 percent error reduction over the state-of-the-art statistical machine translation models.

In VLSI, there is integration of hundreds and thousands of transistors to form a chip (or) microchip. SRAM is utilized for computer cache memory and a chunk of random access memory digital to analog converter on a video card. SRAM keeps data constant, without the need of memory module to be refreshed periodically. SRAM takes main role in very large scale integrated circuit (VLSI) due to its storage capacity and small access time. In this work the simulation study of different SRAM cells 4+2T SRAM, 4TSRAM, 5T SRAM and 6T SRAM are done. Also a 4byte SRAM architecture with row decoder, column decoder, SRAM cell, pre-charge circuit, sense amplifier and write driver circuit are simulated using EDA tool in 45nm technology. The average power delay and area various SRAMs are calculated and compared. SRAM-5T is showing better results for Average power consumption and delay while SRAM-4T is better in terms area.

NLP researchers face a dilemma: on one side, it is unarguably accepted that languages have internal structure rather than strings of words. On the other side, they find it very difficult and expensive to write grammars that have good coverage of language structures. Statistical machine translation tries to cope with this problem by ignoring language structures and using a statistical models to depict the translation process. Most of the translation models are word-based. While the approach has achieved surprisingly good performance comparable to the best commercial systems, many questions remain in the machine translation community. Can the statistical word-based translation still perform well on language pairs with radically different linguistic structures? How would it function with less training data or with spoken languages? The thesis work investigated these questions. In summary, word-based alignment model is a major cause of errors in German-English statistical spoken languag...

"It's a Microcontroller Based DIY Electronics Project. Named Wireless RF Module Using PIC Microcontroller. The RF module is a small electronic circuit used to transmit, receive, or transceive radio waves on one of a number of carrier frequencies. RF modules are widely used in consumer applications such as garage door openers, wireless alarm systems, industrial remote controls, smart sensor applications, weather monitoring system, RFID, wireless mouse technology and wireless home automation systems. They are often used instead of infrared remote controls as they have the advantage of not requiring line-of-sight operation. Thanxx.
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It is now clear that Unmanned Aerial Vehicles (UAV) have many functionalities. This increase in the usage areas of UAVs causes some dangers as well. UAVs can come into contact with or even damage electrical cables during flight, and two major situations can happen:

1. Damage to UAV as a result of contact with power lines
2. Occurence of power outages etc. caused by damage to electrical lines

To prevent the above situations, lidar sensors can be used; however, the heavy sensors and the thin- ness of the cables make the situation very difficult. Therefore, alternative ways of detecting power lines are sought,and in this project, the plan is to investigate the validity of image segmentation within the scope of this field. Based on this, I used U-Net and LinkNet neural networks used for segmentation and VGG-16, VGG- 19, ResNet34, and Inception V3 encoders used in these models. In modeling, the power line dataset of the urban scene (PLDU) and power line dataset of a mountain scene (PLDM) were used, a comparative analysis was made with the help of the "Jaccard" index, and an optimal variant was determined for both databases. As a result, the LinkNet archetype gave better results for PLDM data, while U-Net gave much better results for PLDU.

Synthesis is an automatic method of converting a higher level of abstraction to a lower level of abstraction. In other words the synthesis process converts Register Transfer Level (RTL) descriptions to gate-level netlists. A Register Transfer-Level description is a style that specifies a particular design in terms or registers and combinational logic in between. A good coding style would help the synthesis tool generate a design with minimal area and maximum performance. These gate-level netlists can be optimized for area, speed, testability, etc. The most commonly used synthesis tool in the ASIC industry is Synopsys Design Compiler. Design constraints and other synthesis options are given as commands or default settings to the tool.

Future generations of cellular communications requires higher data rates and a more reliable
transmission link with the growth of multimedia services, while keeping satisfactory quality of service, .
MIMO antenna systems have been considered as an efficient approach to address these demands by
offering significant multiplexing and diversity gains over single antenna systems without increasing
bandwidth and power. Although MIMO systems can unfold their huge benefit in cellular base stations,
but they may face limitations when it comes to their deployment in mobile handsets.
To overcome this drawback, relays (fixed or mobile terminals) can cooperate to improve the overall
system performance in cellular networks. Cooperative communications can efficiently combat the severity
of fading and shadowing through the assistance of relays. It has been found that using relays the capacity
and coverage of cellular networks can be extended without increasing mobile transmit power or
demanding extra bandwidth.

Nowadays memory forms an important and necessary part of every system. In order to make the system more compact and faster, optimization of memory in terms of area, power and speed is to be made. In this paper column decoder has been implemented to minimize the power and area. The memory architecture is simulated using Laker-ADP schematic tool. The number of sense amplifiers required for MxN memory is reduced in ratio 4:1.

TillS BOOK IS ABOUT linear controller design based on optimization of convex or quasi-convex performance criteria. It addresses the problem: "given a linear, finite dimensional time invariant, continuous time model, find if possible a controller (of the same class, linear, time invariant, finite dimensional, continuous time) to meet given design specifications.

Problem statement: Combinational circuits are used in computers for generating binary control decisions and for providing digital components for data processing. Approach: The use of combinational circuits and logic gates to control other circuits was discussed. Different systems that use logic gates, multiplexers, decoders and encoders to control different circuits were presented. This study presented a design and implementation of some combinational circuits such as a decoder, an encoder, a multiplexer, a bus system and read/write memory operations. Results: When we connected some types of combinational circuits to the inputs/outputs of digital circuit, these combinational circuits can help us to manage and flow a different types of control signals through a large digital circuit. Conclusion: Many combinational circuits had a good function which can be used for controlling different parts of any digital system and they produce a suitable way to transfer a control signals between different digital components of any large digital system.

This paper deals with a new class of convolutional codes called Turbo-codes, whose performances in terms of Bit Error Rate (BER) are close to the SHANNON limit. The Turbo-Code encoder is built using a parallel concatenation of two Recursive Systematic Convolutional codes and the associated decoder, using a feedback decoding rule, is implemented as P pipelined identical elementary decoders.

Low Power is an extremely important issue for future mobile communication systems; The focus of this paper is to implementat turbo codes for low power solutions. The effect on performance due to variation in parameters like frame length, number of iterations, type of encoding scheme and type of the interleave in the presence of additive white Gaussian noise is studied with the floating point model. In order to obtain the effect of quantization and word length variation, a fixed point model of the application is also developed.. The application performance measure, namely bit-error rate (BER) is used as a design constraint while optimizing for power and area coverage. Low power Optimization is Performed on Implementation levels by the use of Voltage scaling. With those Techniques we can reduced the power 98.5%and Area(LUT) is 57% and speed grade is Increased .This type of Power maneger is proposed and implemented based on the timing details of the turbo decoder in the VHDL model.

This paper shows an effective design of circuits such as 2:1, 4:1 multiplexers, 2:4 decoder and a full subtractor using reversible gates. This paper also evaluates number of reversible gates used and garbage output implementing each combinational circuit.

Advantage of error detection and correction techniques along with information theory is that it enables reliable delivery of digitized data over communication channels that might be unreliable. Multiple communication channels while operating have to handle the channel noise resulting in errors occurring during transmission from transmitter to a receiver located at some distance. In this paper, a sophisticated error control coding i.e. Reed Solomon Coding technique has been implemented using VHDL and implementation is done on Virtex XC6VLX50 FPGA. The simulation result shows successful design of transmitter and receiver section. We also make use of the clock gating technique for reducing the power consumption of the design

The use of nanowire crossbars to build devices with large storage capabilities is a very promising architectural paradigm for forthcoming nanoscale memory devices. However, this new type of memory devices raises questions regarding how to test their correct operation. In particular, the variability affecting the decoder is expected to make very complex the test of these new devices. In this paper we present a method to simplify the test of these new devices by using a current thresholder to detect badly addressed nanowires. In the proposed method, the thresholder design is based on a stochastic and perturbative model of the current through the nanowires. Thus, the calculated thresholder parameters are robust against technology variation. As our experimental results indicate, the thresholder error probability is initially only ∼ 10 −4 , which can be also reduced further (up to ∼ 60×) by trading-off only ∼ 35% area overhead in the memory.

To reduce the power dissipation in circuits, the reversible logic design is implemented. Reversible logic design is one of the main low power techniques. In the proposed design the address decoder is designed using basic reversible logic gates Fredkin gate and Peres gate. The encoder is designed using Fredkin and Feynman gate. In the use of Peres gate in proposed design reduce the quantum cost and power dissipation of the decoder. The Content Addressable memory architecture will be realized using FPGA

Here it is proposed a conceptual model for geographic location of points in two dimensions, by the use of triangulation. The triangulation method here described operates on an Ultra-wideband (UWB) Timed-array module with center frequency of 4GHz. The technique consists in two arrays of planar antennas located at predetermined points, which serve as receptor for new portable UWB transmitter equipped with an omnidirectional planar antenna. The relative coordinates are then computed using proposed mathematical models. The transmitter circuit was designed using 180nm Complementary Metal Oxide Semiconductor (CMOS) – IBM (7WL_5LM_MA) process and the planar antennas were designed on FR-4 substrate. Post-Layout Spice circuit simulations show the generation of pulses with 94.5mVpp amplitudes and 514ps width. The consumption is around 677µW per pulse using a 1.8V power supply at 100MHz pulse repetition rate (PRR). 3D electromagnetic simulations were performed using CST Microwave Studio 2011, with an accuracy of less than 0.1m.

IEEE 802.11dg devices promise to accommodate the increasing consumer demands for high data rate wireless communications. A novel optimal decoding method for receiver antenna diversity combining for COFDM system is discussed in this paper. The proposed method provides robust wireless connections for applications such as wireless multimedia communications. The proposed optimal diversity combining integrates the channel equalization, demodulation (bit metrics calculation) and diversity combining in the decoder, which is the maximum likelihood decoding method for the diversity combining for COFDM system. The proposed method can have about 4-6 dB gain over a single antenna receiver and 2-4 dB gain over a conventional symbol level diversity-combining receiver without increasing the implementation complexity.

With the advancement in technology, the number of electronic devices in our day-to-day lives has increased to make life simpler. So a necessity to construct a Universal Remote System that will easily control all these devices from a distance will not only reduce the complexity of handling the number of devices simultaneously, but also save power. This paper presents a successfully developed hardware of a Universal Remote Control System using DTMF (Dual- Tone Multi-Frequency) tones as the control signals. The uniqueness of DTMF is that it is simple to generate and noise- immune. This system was also implemented using GSM links besides the wired channel, the main advantage of it being that it helps in controlling devices located at any part of the world or at any place like hazardous plants, where the presence of a human could prove dangerous. So there are a number of practical applications associated with this system. It is simple, economical, easy to use and could be further upgrade...

This paper deals with a new class of convolutional codes called Turbo-codes, whose performances in terms of Bit Error Rate (BER) are close to the SHANNON limit. The Turbo-Code encoder is built using a parallel concatenation of two Recursive Systematic Convolutional codes and the associated decoder, using a feedback decoding rule, is implemented as P pipelined identical elementary decoders.

Early Chinese elite were defined by their aristocratic control of land. That control came directly from the emperor and was documented on bronze ritual vessels, which were handed down from generation to generation. The land grant boundaries were defined using symbols inscribed on bronze as decorations, and Western Zhou vessels containing these symbols were used to resolve land disputes. Methodical analysis comparing the inscriptions in relation to the symbols, combined with an understanding of early Chinese cartography and etymology, allows the bronze vessel land grants to be decoded.

A flash digital phase-locked loop (DPLL) is designed using 0.18 mm CMOS process and a 3.3 V power supply. It operates in the frequency range 200 MHz -2 GHz. The DPLL operation includes two stages: (i) a novel coarse-tuning stage based on a flash algorithm similar to the algorithm employed in flash A/D converters, and (ii) a fine-tuning stage similar to conventional DPLLs. The flash portion of the DPLL is made up of frequency comparators, an encoder and a decoder which drives a multiple charge pump (CP)/lowpass filter (LPF) combination. Design considerations of the flash DPLL circuit components as well as implementation using Cadence design tools are presented. Spectre simulations were also performed and demonstrated a significant improvement in the lock time of the flash DPLL as compared to the conventional DPLL. By increasing the number of frequency comparators, the lock time is expected to be always less than 100 ns in the above-mentioned frequency range.

We address the problem of distributed source coding, i.e. compression of correlated sources that are not co-located and/or cannot communicate with each other to minimize their joint description cost. In this work we tackle the related problem of compressing a source that is correlated with another source which is available only at the decoder. In contrast to prior information-theoretic approaches, we introduce a new construction and practical framework for tackling the problem based on the judicious incorporation of channel coding principles into this source coding problem. We dub our approach as distributed source coding using syndromes (DISCUS). We focus in this paper on trellis-structured constructions of the framework to illustrate its utility. Simulation results confirm the power of DISCUS, opening up a new and exciting constructive playing-ground for the distributed source coding problem. For the distributed coding of correlated i.i.d. Gaussian sources that are noisy versions of each other with “correlation-SNR” in the range of 12 to 20 dB, the DISCUS method attains gains of 7-15 dB in SNR over the Shannon-bound using “naive” independent coding of the sources

It is now clear that Unmanned Aerial Vehicles (UAV) have many functionalities. This increase in the usage areas of UAVs causes some dangers as well. UAVs can come into contact with or even damage electrical cables during flight, and two major situations can happen: 1. Damage to UAV as a result of contact with power lines 2. Occurence of power outages etc. caused by damage to electrical lines To prevent the above situations, lidar sensors can be used; however, the heavy sensors and the thin- ness of the cables make the situation very difficult. Therefore, alternative ways of detecting power lines are sought,and in this project, the plan is to investigate the validity of image segmentation within the scope of this field. Based on this, I used U-Net and LinkNet neural networks used for segmentation and VGG-16, VGG- 19, ResNet34, and Inception V3 encoders used in these models. In modeling, the power line dataset of the urban scene (PLDU) and power line dataset of a mountain scene (PLDM) were used, a comparative analysis was made with the help of the "Jaccard" index, and an optimal variant was determined for both databases. As a result, the LinkNet archetype gave better results for PLDM data, while U-Net gave much better results for PLDU.

We discover the optimum decoder structure for fast low-power SRAMS. The results are ideal when the decoder is designed as a binary tree without the precoder. We find that skewed circuits with self-resetting gates work well, and we explore some basic scaling algorithms for minimal delay and power in the SRAM data path. Signal oscillations on high capacitance nodes like bit lines and data lines are decreased, resulting in low power operation. Clocked voltage sense amplifiers are required for low sensing power, and accurate construction of their sense clock is required for high-speed operation. By restricting bit line and NO line swings, we examine tracking circuits to aid in the development of the sense clock and allow timed sense amplifiers. The tracking circuits successfully use a replica memory cell and a replica bit line to track the memory cell's delay throughout a wide variety of manufacturing and operating conditions. The results of two different prototypes' experiments are reported. Finally, we investigate the speed and power development trends of SRAMs as a function of size and technology, discovering that if the connection delay is negligible, the SRAM delay grows as the logarithm of its size. Wire delay becomes increasingly important for SRAMs after the fifth generation. The wire delay worsens as the process shrinks, requiring wire redesign to keep the wire delay proportionate to the gate delay. Hierarchical SRAM topologies provide enough of array space for fat Wires and may be used to control time. Throughout the procedure, the wire delay for 4Mb and smaller designs diminishes.

IEEE 802.11dg devices promise to accommodate the increasing consumer demands for high data rate wireless communications. A novel optimal decoding method for receiver antenna diversity combining for COFDM system is discussed in this paper. The proposed method provides robust wireless connections for applications such as wireless multimedia communications. The proposed optimal diversity combining integrates the channel equalization, demodulation (bit metrics calculation) and diversity combining in the decoder, which is the maximum likelihood decoding method for the diversity combining for COFDM system. The proposed method can have about 4-6 dB gain over a single antenna receiver and 2-4 dB gain over a conventional symbol level diversity-combining receiver without increasing the implementation complexity.

This paper presents an automated system for human face recognition in a real time background for ATM transaction. Now a days taking money from the ATM has became a major threat. When we are inserting our debit card the system is asking for the pin number. After typing the pin number the money that we need is been transacted. With the orginal debit card any one can take the money from the ATM. Now a days unknown strange people are creating a duplicate debit card and they use it in the ATM and loot our money. To eradicate this problem we are going for secured ATM transaction using face recognition. Now a days face recognition technique is playing a vital role in the field of secured process. By following this technique we can avoid the strangers looting our money and thus our money will be safer and secured. This process is carried out by matching the present captured face image to already stored database image. When both the images gets matched up ATM transaction is been allowed. If the images doesn't match up the transaction is been denied. But this task is very difficult as the real time background subtraction in an image is still a challenge. To detect real time human face, Principal Component Analysis (PCA) is used to recognize the faces detected with a high accuracy rate. Once recognition is done with the matched face, then the input image will be marked and updated in the database. This project gives much more solutions with accurate results in user interactive manner rather than existing normal transaction management systems. The ease of deployment is due to wireless mode of communication. A prototype of the controller is implemented, and shows how the controller can easily and flexibly control the appliances.

Consider the two-way rate-distortion problem in which a helper sends a common limited-rate message to both users based on side information at its disposal. We characterize the region of achievable rates and distortions where a Markov form (Helper)-(User 1)-(User 2) holds. The main insight of the result is that in order to achieve the optimal rate, the helper may use a binning scheme, as in Wyner-Ziv, where the side information at the decoder is the "further" user, namely, User 2. We derive these regions explicitly for the Gaussian sources with square error distortion, analyze a trade-off between the rate from the helper and the rate from the source, and examine a special case where the helper has the freedom to send different messages, at different rates, to the encoder and the decoder.

Low Power is an extremely important issue for future mobile communication systems; The focus of this paper is to implementat turbo codes for low power solutions. The effect on performance due to variation in parameters like frame length, number of iterations, type of encoding scheme and type of the interleave in the presence of additive white Gaussian noise is studied with the floating point model. In order to obtain the effect of quantization and word length variation, a fixed point model of the application is also developed.. The application performance measure, namely bit-error rate (BER) is used as a design constraint while optimizing for power and area coverage. Low power Optimization is Performed on Implementation levels by the use of Voltage scaling. With those Techniques we can reduced the power 98.5%and Area(LUT) is 57% and speed grade is Increased .This type of Power maneger is proposed and implemented based on the timing details of the turbo decoder in the VHDL model.

The turbo detection of turbo coded symbols over correlated Rayleigh flat fading channels generated according to Jakes' model is considered in this paper. We propose a method to estimate the channel signal-to-noise ratio (SNR) and the maximum Doppler frequency. These statistics are required by the linear minimum mean squared error (LMMSE) channel estimator. To improve the system convergence , we redefine the channel reliability factor by taking into account the channel estimation error statistics. Simulation results for rate 1/3 turbo code and two different normalized fading rates show that the use of the new reliability factor greatly improves the performance. The improvement is more substantial when channel statistics are unknown. K EYWORDS MAP-BCJR decoder, SNR, maximum Doppler frequency, turbo processing, channel reliability.

We address the problem of compressing correlated distributed sources, i.e., correlated sources which are not co-located or which cannot cooperate to directly exploit their correlation. We consider the related problem of compressing a source which is correlated with another source that is available only at the decoder. This problem has been studied in the information theory literature under the name of the Slepian-Wolf (1973) source coding problem for the lossless coding case, and as "rate-distortion with side information" for the lossy coding case. We provide a constructive practical framework based on algebraic trellis codes dubbed as DIstributed Source Coding Using Syndromes (DISCUS), that can be applicable in a variety of settings. Simulation results are presented for source coding of independent and identically distributed (i.i.d.) Gaussian sources with side information available at the decoder in the form of a noisy version of the source to be coded. Our results reveal the promise of this approach: using trellis-based quantization and coset construction, the performance of the proposed approach is 2-5 dB from the Wyner-Ziv (1976) bound.

In CDMA systems with variable number of users, the decoder consists of two stages. The first stage is the active user identification and the second one is the multi-user detection. Most of the proposed active user identification methods fail to work in overloaded CDMA systems (when the number of users is more than the spreading factor). In this paper we propose a joint active user identification and multi-user detection for binary input CDMA systems using the Viterbi algorithm. We will show that the proposed identification/detection method is Maximum A posteriori Probability (MAP) and outperforms the pervious results. In addition, some suboptimum decoders will be proposed that have lower computational complexities but lower performances.

This paper presents circuit design for a low power fault secure encoder and decoder system. Memory cells in logic circuits have been protected from soft errors for more than a decade due to increase in soft error rates. In this paper the circuitry around the memory block have been susceptible to soft errors and must be protected from faults. The proposed design uses error correcting codes and ring counter addressing scheme. In the ring counter several new clock gating techniques are proposed to reduce power consumption. A fault secure Encoder and Decoder error free low power logic circuits can be achieved by the proposed design. Simulation results show great improvement in power consumption. Fault secure Encoder and Decoder with clock gated by CG-element consumes approximately half the power of that consumed by the fault free circuit which doesn’t employ clock gating technique.

This paper presents a BCH based hardware implementation of 32-bit Fault-tolerant ALU in which is compared with the current techniques such as Residue code, Triple Modular Redundancy (TMR) with single voting and TMR with triplicated voter that are widely used in space application to mitigate the upsets, in terms of area penalty. We consider BCH (Bose, Chaudhuri, and Hocquenghem) codec (encoder, decoder) that is implemented FPGA hardware. The new implementation of ALU employing BCH code on Spartan-3 FPGA has been provided. The results show reduced area requirements compared to the other technique and it can correct any 5-bit error in any positions of 32-bits input registers of ALU