Power Consumption

In 2020, mobile access networks will experience significant challenges as compared to the situation of today. Traffic volumes are expected to increase 1000 times, and the number of connected devices will be 10-100 times higher than today in a networked society with unconstrained access to information and sharing of data available anywhere and anytime to anyone and anything. One of the big challenges is to provide this 1000-fold capacity increase to billions of devices in an affordable and sustainable way. Low energy consumption is the key to achieve this. This paper takes as starting point the situation of today, and tries to pinpoint important focus areas and potential solutions when designing an energy efficient 5G mobile network architecture. These include system architecture, where a logical separation of data and control planes is seen as a promising solution; network deployment, where (heterogeneous) ultra dense layouts will have a positive effect; radio transmission, where the introduction of massive antenna configurations is identified as an important enabler; and, finally, backhauling solutions that need to be more energy efficient than today.

In this work an optimized version of the field-mill sensor structure for atmospheric electric field measurements was presented. Both the mechanical structure and the electronic front-end, acquisition and control system are optimized in order to reduce the power consumption and to enhance the instrument metrological performance in term of sensitivity and frequency band. A solar power operated system was realized and tested. The developed system is also equipped with a GPS receiver, allowing data synchronization. This feature enables the implementation of a distributed measurement system for the monitoring of the atmospheric electric field.

Due to CMOS technology scaling, devices are getting smaller, faster, and operating at lower supply voltages. The reduced capacitances and power supply voltages and the increased chip density to perform more functionality result in increasing the soft errors and making them one of the essential design constraints at the same level as delay and power. Even though the impact of process variations on the performance and the power consumption has been investigated by many researchers, its impact on soft errors has not been paid enough attention. This impact is investigated in this paper for 65-nm CMOS technology. The soft error yield is defined in this paper similar to the timing yield and the power yield. This paper shows that the soft error yield of the sense-amplifier based flip flop (SA-FF) is very poor. Therefore, soft error mitigation techniques are required when using this flip-flop topology. The semi-dynamic flip-flop (SD-FF) exhibits the best soft error yield behavior with a very high performance at the expense of large power requirement. Finally, some design insights are proposed to guide flip-flops designers to select the best flip-flop topology that satisfies their specific circuit soft error rate constraints.

Performance and power are the first order design metrics for Network-on-Chips (NoCs) that have become the de-facto standard in providing scalable communication backbones for multicores/CMPs. However, NoCs can be plagued by higher power consumption and degraded throughput if the network and router are not designed properly. Towards this end, this paper proposes a novel router architecture, where we tune the frequency of a router in response to network load to manage both performance and power. We propose three dynamic frequency tuning techniques, FreqBoost, FreqThrtl and FreqTune, targeted at congestion and power management in NoCs. As enablers for these techniques, we exploit Dynamic Voltage and Frequency Scaling (DVFS) and the imbalance in a generic router pipeline through time stealing. Experiments using synthetic workloads on a 8x8 wormhole-switched mesh interconnect show that FreqBoost is a better choice for reducing average latency (maximum 40%) while, FreqThrtl provides the maximum benefits in terms of power saving and energy delay product (EDP). The FreqTune scheme is a better candidate for optimizing both performance and power, achieving on an average 36% reduction in latency, 13% savings in power (up to 24% at high load), and 40% savings (up to 70% at high load) in EDP. With application benchmarks, we observe IPC improvement up to 23% using our design. The performance and power benefits also scale for larger NoCs.

Camless internal combustion engines offer improvements over traditional engines in terms of torque performance, reduction of emissions, reduction of pumping losses and fuel economy. Theoretically, electromagnetic valve actuators offer the highest potentials for improving efficiency due to their control flexibility. For real applications, however, the valve actuators developed so far suffer from high power consumption and other control problems. One key point is the design of the reference trajectory to be tracked by the closed loop controller. In this brief, a design technique aimed at minimizing power consumption is proposed. A constrained optimization problem is formulated and its solution is approximated by exploiting local flatness and physical properties of the system. The performance of the designed trajectory is validated via an industrial simulator of the valve actuator.

Microprocessor power has become a first-order constraint at run-time. Designers must employ aggressive power-management techniques at run-time to keep a processor's ballooning power requirements under control. Effective power management benefits from knowledge of run-time microprocessor power consumption in both the core and individual microarchitectural structures, such as caches, queues, and execution units. Increasingly feasible perstructure power-control techniques, such as fine-grain clock gating, power gating, and dynamic voltage/frequency scaling (DVFS), become more effective from run-time estimates of per-structure power. However, run-time computation of per-structure power estimates based on utilization requires daunting numbers of input statistics, which makes per-structure monitoring of run-time power a challenging problem.

The concept of energy-efficient networking has begun to spread in the past few years, gaining increasing popularity. Besides the widespread sensitivity to ecological issues, such interest also stems from economic needs, since both energy costs and electrical requirements of telcos' and Internet Service Providers' infrastructures around the world show a continuously growing trend. In this respect, a common opinion among networking researchers is that the sole introduction of low consumption silicon technologies may not be enough to effectively curb energy requirements. Thus, for disruptively boosting the network energy efficiency, these hardware enhancements must be integrated with ad-hoc mechanisms that explicitly manage energy saving, by exploiting network-specific features. This paper aims at providing a twofold contribution to green networking. At first, we explore current perspectives in power consumption for next generation networks. Secondly, we provide a detailed survey on emerging technologies, projects, and work-in-progress standards, which can be adopted in networks and related infrastructures in order to reduce their carbon footprint. The considered approaches range from energy saving techniques for networked hosts, to technologies and mechanisms for designing nextgeneration and energy-aware networks and networking equipment.

Advancements in modern CAD tools enable students to design hardware, simulate their designs, synthesize them, and study common low-level issues such as timing, glitches, power consumption, and space requirements. Rather than emphasizing logic and gates to ...

We investigate the idea of using nodes with controllable mobility as intermediate relays for reducing the power consumption in a network of mobile wireless sensors. We present the relay deployment problem, which is to optimally position the relay nodes in the network so as to minimize the power consumed in communication. We discuss and evaluate a localized solution methodology that computes the optimal position and movement of the relay nodes based on the information pertaining to the active data flows and the mobility patterns of the sensors in the network. Results from a preliminary simulation study indicate that deployment of relay nodes can result in considerable energy savings. We also outline some of the issues that need to be addressed in deploying such mobilitycontrollable relay nodes in a real network.

We propose a design flow for low-power and low-cost, data-dominated, embedded systems which tightly integrate different technologies and architectures. We use Math- works’ Simulink c environment,for functional specification and analysis of performance,criteria such as timing (latency and throughput) and power,dissipation. The flow can exploit trade-offs between,software and hardware,as well as between digital and analog implemen- tations, and it can

The growing computing demand from industry and academia has lead to excessive power consumption which not only impacting long term sustainability of Grids like infrastructures in terms of energy cost but also from environmental perspective. The problem can be addressed by replacing with more energy efficient infrastructures, but the process of switching to new infrastructure is not only costly but also time consuming. Grid being consist of several HPC centers under different administrative domain, make problem more difficult. Thus, for reduction in energy consumption, we address the challenge by effectively distributing compute-intensive parallel applications on grid. We presented a metascheduling algorithm which exploits the heterogeneous nature of Grid to achieve reduction in energy consumption. Simulation results show that out algorithm HAMA can significantly improve the energy efficiency of global grids by a factor of typically 23% and as much as a factor of 50% in some cases while meeting user's QoS requirements

With adiabatic techniques for capacitor charging, theory suggests that it should be possible to build gates with arbitrarily small energy dissipation. In practice, the complexity of adiabatic approaches has made them impractical. We describe a new CMOS logic family-adiabatic dynamic logic (ADL)-that is the result of combining adiabatic theory with conventional CMOS dynamic logic. ADL gates are simple, general, readily cascadable, and may be fabricated in a standard CMOS process. A chain of 1000 ADL inverters has been constructed in 0.9 pm CMOS and successfully tested at 250 MHz. This result, together with comprehensive circuit simulation, suggest that ADL offers an order of magnitude reduction in power consumption over conventional CMOS circuitry.

Market and customer demands have continued to push the limits of CMOS performance. At-speed test has become a common method to ensure these high performance chips are being shipped to the customers fault-free. However, at-speed tests have been known to create higher-than-average switching activity, which normally is not accounted for in the design of the power supply network. This potentially creates conditions for additional delay in the chip; causing it to fail during test. In this paper, we propose a pattern compaction technique that considers the layout and gate distribution when generating transition delay fault patterns. The technique focuses on evenly distributing switching activity generated by the patterns across the layout rather than allowing high switching activity to occur in a small area in the chip that could occur with conventional delay fault pattern generation. Due to the relationship between switching activity and IR-drop, the reduction of switching will prevent large IR-drop in high demand regions while still allowing a suitable amount of switching to occur elsewhere on the chip to prevent fault coverage loss. This even distribution of switching on the chip will also result in avoiding hot-spots.

This paper describes a 500-Gbps parallel wavelengthdivision multiplexed (PWDM) optical interconnect where 48 channels of 10.42-Gbps data are transmitted over a parallel 12-fiber ribbon with 4 wavelengths per fiber. The transmitter and receiver are each chip-scale packages with a footprint of 5 mm x 8 mm and a combined power consumption of 3 W. This work is motivated by the continually increasing bandwidth needs of short-distance computer processor interconnects, which are demanding optical solutions that maximize bandwidth per unit area, power consumption, and cost.

In this research work, a survey on Wireless Sensor Networks (WSN) and their technologies, standards and applications was carried out. Wireless sensor networks consist of small nodes with sensing, computation, and wireless communications capabilities. Many routing, power management, and data dissemination protocols have been specifically designed for WSNs where energy awareness is an essential design issue. Routing protocols in WSNs might differ depending on the application and network architecture. A multidisciplinary research area such as wireless sensor networks, where close collaboration between users, application domain experts, hardware designers, and software developers is needed to implement efficient systems. The flexibility, fault tolerance, high sensing fidelity, low cost, and rapid deployment characteristics of sensor networks create many new and exciting application areas for remote sensing. In the future, this wide range of application areas will make sensor networks an integral part of our lives. However, realization of sensor networks needs to satisfy the constraints introduced by factors such as fault tolerance, scalability, cost, hardware, topology change, environment, and power consumption.

A single-chip video codec with embedded display controller for videotelephony applications is described. It encodes and decodes simultaneously up to 30 CIF pictures per second according to video-conferencing recommendations H261, H263 (all five options), and H263+ (six additional options). The die area is 132 mm 2 in a 0.35-m technology, and the power consumption is 1.4 W. The chip uses a distributed dedicated multiprocessor architecture, where computation-intensive functions are done by dedicated hardware, and where picture quality or standard dependent parts are done in software on dedicated programmable processors. Main architectural choices are discussed, and emphasis is put on hardware/software partitioning and codesign.

We present a model of energy consumption in IP networks. Using this model, we identify energy ldquohotspotsrdquo and estimate how energy consumption will grow with increasing network capacity. Todaypsilas Internet uses less than 1% of the available electricity supply. However, network energy consumption could grow substantially as access rates increase.

Protection of data against long fading time is one of the greatest challenges posed by a satellite delivery system offering multimedia services to mobile devices like DVB-SH. To deal with this challenge several enhancements and modifications of the existing terrestrial mobile TV (DVB-H) physical and link layers are being considered. These solutions provide the required protection depth but they don't take into account the specificity of mobile handheld devices such as power consumption, memory constraints and chipsets implementation costs. In this report, we propose an innovative algorithm (called Multi Burst Sliding Encoding or MBSE) that extends the DVB-H intra-burst (MPE-FEC) protection to an inter-burst protection so that complete burst losses could be recovered while taking into account the specificity of mobile handheld devices. Based on a clever organisation of the data, our algorithm allows to provide protection against long term fading while still using RS code implemented in DVB-H chipsets. We evaluate the performance of MBSE by both theoretical analysis as well as intensive simulations and experiments. The results also show good performance in terms of protection, battery and memory saving. The MBSE is now under standardisation and it is considered by the DVB Forum as the main solution for the DVB-SH class terminals.

Selection of dynamic dividers in CMOS PLLs for GHzs applications allows remarkable reduction in power loss without affecting phase noise and power supply sensitivity. Frequency dividers are combination of classic TSPC logic (true-single-phase-clock) and E_TSPC logic (extended TSPC). The designed PLL with % 8/9 prescaler is used for wireless LAN applications and synthetic of frequencies between 5.14 to 5.70 GHz. In this paper a % 8/9 prescaler has designed at 0.25 micrometers process for 2.5_3 GHz band width. This prescaler has been designed with 2.5v power supply with using E_TSPC logic. In this circuit in addition to decrement of power consumption, divider can work in a nearly high speed. Subsequently the dimensions of transistors have been improved and power consumption has been reduced from 3.8mw to 2.9mw. Then, the layout of circuit has been designed with L-Edit software. The simulation results of are identical to that we expect according to earlier Spice simulations.

Energy-efficiency is key to meet lifetime requirements of Wireless Sensor Networks (WSN) applications. Today's run-time platforms and development environments leave it to the application developer to manage power consumption. For best results, the characteristics of the individual hardware platforms must be well understood and minutely directed. An Operating System (OS) with suitable programming abstractions can micromanage power consumption of resources. We demonstrate with the Mote Runner platform how the inherent overhead of managed application code is compensated for by a platform-independent communication API together with sleep optimizations. The proposed abstractions and optimizations can be applied to other modern sensor network platforms. To quantify the effectiveness of our approach, we measured the energy efficiency of a realworld WSN application using a custom TDMA communication protocol fully implemented on both Mote Runner and TinyOS. Mote Runner's power management and sleep phase optimizations outperforms TinyOS in our test application for duty cycles below 10% on the Iris hardware.

The power consumption of wireless access networks will become an important issue in the coming years. In this paper, the power consumption of base stations for mobile WiMAX, fixed WiMAX, UMTS, HSPA, and LTE is modelled and related to the coverage. A new metric, the power consumption per covered area P C area , is introduced, to compare the energy efficiency of the considered technologies for a range of bit rates. Assuming the model parameters are correct, the conclusions are then as follows. For a 5 MHz channel, UMTS is the most energy-efficient technology until a bit rate of 2.8 Mbps, LTE between 2.8 Mbps and 8.2 Mbps, fixed WiMAX between 8.2 Mbps and 13.8 Mbps and finally mobile WiMAX for bit rates higher than 13.8 Mbps. Furthermore, the influence of MIMO is investigated. For a 2x2 MIMO system, P C area decreases by 36 % for mobile WiMAX and by 23 % for HSPA and LTE compared to the SISO system, resulting in a higher energy efficiency. The power consumption model for base stations is used in the deployment tool GRAND (Green Radio Access Network Design) for green wireless access networks. GRAND uses a genetic based algorithm and is applied on an actual case for the Brussels Capital Region, showing the possibilities of energy-efficient planning.

Register files are becoming one of the critical components of current out-of-order processors in terms of delay and power consumption, since their potential to exploit instruction-level parallelism is quite related to the size and number of ports of the register file. In conventional register renaming schemes, register releasing is conservatively done only after the instruction that redefines the same register is committed. Instead, we propose a scheme that releases registers as soon as the processor knows that there will be no further use of them. We present two earlyreleasing hardware implementations with different performance/complexity trade-offs. Detailed cycle-level simulations show either a significant speedup for a given register file size, or a reduction in register file size for a given performance level.

Three-dimensional integrated circuits (3D-ICs) are a promising approach to address the integration challenges faced by current systems on chips (SoCs). Designing an efficient network on chip (NoC) interconnect for a 3-D SoC that meets not only the application performance constraints but also the constraints imposed by the 3-D technology is a significant challenge. In this paper, we present a design tool, SunFloor 3D, to synthesize application-specific 3-D NoCs. The proposed tool determines the best NoC topology for the application, finds paths for the communication flows, assigns the network components to the 3-D layers, and places them in each layer.

Motivated by the design of the well-known Enigma machine, we present a novel ultra-lightweight encryption scheme, referred to as Hummingbird, and its applications to a privacy-preserving identification and mutual authentication protocol for RFID applications. Hummingbird can provide the designed security with a small block size and is therefore expected to meet the stringent response time and power consumption requirements described in the ISO protocol without any modification of the current standard. We show that Hummingbird is resistant to the most common attacks such as linear and differential cryptanalysis. Furthermore, we investigate some properties for integrating the Hummingbird into a privacypreserving identification and mutual authentication protocol.

An occupancy map provides an abstract top view of a scene and can be used for many applications such as domotics, surveillance, elderly-care and video teleconferencing. Such maps can be accurately estimated from multiple camera views. However, using a network of regular high resolution cameras makes the system expensive, and quickly raises privacy concerns (e.g. in elderly homes). Furthermore, their power consumption makes battery operation difficult. A solution could be the use of a network of low resolution visual sensors, but their limited resolution could degrade the accuracy of the maps. In this paper we used simulations to determine the minimum required resolution needed for deriving accurate occupancy maps which were then used to track people. Multi-view occupancy maps were computed from foreground silhouettes derived via an analysis of moving edges. Ground occupancies computed from each view were fused in a Dempster-Shafer framework. Tracking was done via a Bayes filter usin...

Since battery technology has not progressed as rapidly as semiconductor technology, power efficiency has become increasingly important in wireless networking, in addition to the traditional quality and performance measures, such as bandwidth, throughput, and fairness. Energy-efficient design requires a cross layer approach as power consumption is affected by all aspects of system design, ranging from silicon to applications. This article presents a comprehensive overview of recent advances in cross-layer design for energy-efficient wireless communications. We particularly focus on a system-based approaches towards energy optimal transmission and resource management across time, frequency, and spatial domains. Details related to energy-efficient hardware implementations are also covered.

A significant source for enhancing application performance and for reducing power consumption in embedded processor applications is to improve the usage of the memory hierarchy. Such objective classically translates into optimizing spatial and temporal data locality especially for nested loops. In this paper, we focus on temporal data locality. Unlike many existing methods, our approach pays special attention to TLB (Translation Lookaside Buffer) effectiveness since a TLB miss can take up to three times more cycles than a cache miss. We propose a generalization of the traditional approach for temporal locality improvement, called data sequence localization, which reduces the number of iterations that separates accesses to a given array element.

Climate change has caused an increasing number of landslides, especially in the mountainous provinces of Vietnam, resulting in the destruction of vital transport and other infrastructure. Current monitoring and forecasting systems of the meteorology department cannot deliver accurate and reliable forecasts for weather events and issue timely warnings. This paper describes the development of a simple, low cost, and efficient system for monitoring and warning landslide in real-time. The authors focus on the use of wireless and related technologies in the implementation of a technical solution and some of the problems of the wireless sensor network (WSN) related to power consumption. Promising compressed sensing (CS) based solution for landslide monitoring is discussed and evaluated in the paper.

This paper investigates implementation and design issues for a heterogeneous network for structural monitoring. The proposed application uses wireless sensors and the controller area network (CAN) to provide energy efficient monitoring. The contributions include: implementation of the PIC18f4680 platform in TinyOS, creating a message protocol over CAN, and developing a sensor board.

A 256 144-bit TCAM is designed in 0.18-m CMOS. The proposed TCAM cell uses 4T static storage for increased density. The proposed match-line (ML) sense scheme reduces power consumption by minimizing switching activity of search-lines and limiting voltage swing of MLs. The scheme achieves a match-time of 3 ns and operates at a minimum supply voltage of 1.2 V.

This paper described about design, fabrication and characterization of conductivity sensor using printed circuit board (PCB). The main objective is to sense the conductivity of aqua agriculture. A sensor was design by using interdigital capacitor concept where the term interdigital refers to pattern of fingers that is resembled by the shape and relative position of the electrodes. This sensor was fabricated by using PCB in order to minimize the cost than the existing conductivity sensor. Sensor performance was characterized by various test setups to check ability and accuracy of the sensor. From the result, it shown that the sensor has very good sensitivity with correlation coefficient R 2 of 0.969.

Design of power-efficient and highspeed data path logic systems are one of the most substantial areas of research in VLSI system design. In digital adders, the speed of addition is limited by the time required to propagate a carry through the adder. The sum for each bit position in an elementary adder is generated sequentially only after the previous bit position has been summed and a carry propagated into the next position. The CSLA is used in many computational systems to alleviate the problem of carry propagation delay by independently generating multiple carries and then select a carry to generate the sum. However, the CSLA is not area efficient because it uses multiple pairs of Ripple Carry Adders (RCA) to generate partial sum and carry by considering carry input, then the final sum and carry are selected by the multiplexers (mux). The basic idea of this work is to use Binary to Excess-1 Converter (BEC) instead of RCA in the regular CSLA to achieve high speed and low power consumption.

We present a routability-driven top-down clustering technique for area and power reduction in clustered FPGAs. This technique is based on a multilevel partitioning approach. It leads to better device utilization, savings in area, and reduction in power consumption. Routing area reduction of 15% is achieved over previously published results. Power dissipation is reduced by an average of 8.5%

The problem of optimal space allocation among interconnect wires in a VLSI layout, in order to minimize the switching power consumption and the average signal delay, is addressed in this article. We define a Weighted Power-Delay Sum (WPDS) objective function and derive necessary and sufficient conditions for the existence of optimal interwire space allocation, based on the notion of capacitance density. At the optimum, every wire must be in equilibrium of its line-to-line weighted capacitance density on its two opposite sides, and the WPDS of the whole circuit is minimal if and only if capacitance density is uniformly distributed across the entire layout. This condition is shown to be equivalent to all paths of the layout cross-capacitance graph having the same length and all cuts having the same flow. An implementation which has been used in the design of a recent commercial high-end microprocessor and yielded 17% power reduction and 9% delay reduction in top-level interconnects is presented.

This article presents the design of a novel quadband LNA operating in the GSM 0.9GHz/GSM l.8GHz and ZigBee 0.9GHz/WLAN 2.4GHz communication standards. This pseudo-concurrent architecture uses a two bit mode switch for selecting between the frequency bands. An RF switch is implemented before the Low Noise Amplifier (LNA) module to improve the insertion loss and isolation between the frequency bands. The pseudo-concurrent LNA is designed and simulated in CADENCE using 130nm UMC technology. The current design is especially suitable for use in multi-standard wireless receiver frontends as it saves die area and reduces power consumption by replacing parallel LNAs for each channel frequency. Simulation results indicate a Noise Figure below 4dB and S 21 above 14 dB in all frequency bands while drawing 10mA current from a 1.2V power supply.

We describe an optimization strategy for minimizing total power consumption using dual threshold voltage (Vth) technology. Significant power savings are possible by simultaneous assignment of Vth with gate sizing. We propose an efficient algorithm based on linear programming that jointly performs Vth assignment and gate sizing to minimize total power under delay constraints. First, linear programming assigns the optimal amounts of slack to gates based on power-delay sensitivity. Then, an optimal gate configuration, in terms of Vth and transistor sizes, is selected by an exhaustive local search. Benchmark results for the algorithm show 32% reduction in power consumption on average, compared to sizing only power minimization. There is up to a 57% reduction for some circuits. The flow can be extended to dual supply voltage libraries to yield further power savings.

Solar cooling applied to buildings is without a doubt an interesting alternative for reducing energy consumption in traditional mechanical steam compression air conditioning systems. The study of these systems should have a closely purely fundamental approach including the development of numerical models in order to predict the overall installation performance. The final objective is to estimate cooling capacity, power consumption, and overall installation performance with relation to outside factors (solar irradiation, outside temperature.). The first stage in this work consists of estimating the primary energy produced by the solar collector field. The estimation of this primary energy is crucial to ensure the evaluation of the cooling capacity and therefore the cooling distribution and thermal comfort in the building. Indeed, the absorption chiller performance is directly related to its heat source. This study presents dynamic models for double glazing solar collectors and compares the results of the simulation with experimental results taken from our test bench (two collectors). In the second part, we present an extensive collector field model (36 collectors) from our solar cooling installation at The University Institute of Technology in St Pierre, Reunion Island as well as our stratified tank storage model. A comparison of the simulation results with real scale solar experimental data taken from our installation enables validation of the double glazing solar collector and stratified tank dynamic models.

In the battlefield of the future, more and more information will be available for making decisions on a tactical level, provided that this information can be dispersed rapidly and accurately. As a consequence, advanced tactical decision support that now is limited to advanced platforms (e.g. combat aircrafts) will become available at a much lower level, ranging from different kind of

In this study, irradiation of natural rubber latex using pulsed plasma cathode electron beam system has been attempted. Fundamentally different from the conventional hot filament electron sources, the present pulsed plasma cathode electron beam can be used for vulcanization process with large area of irradiation (150 × 650 mm), low electrical power consumption (< 9 kW), and high efficiency. The evaluation results show that after electron beam irradiation at 150 kV 18 A on old natural rubber latex with stirring method, an increase of the tensile strength up to 12.3 MPa can be achieved without any chemical additive or sensitizer. Higher tensile strength until 18.0 MPa can be provided on fresh natural rubber latex. It suggests that the present system can be applied as a new type of electron accelerator for cross-linking of natural rubber latex.

This paper presents a standalone closed loop wireless power transmission system that is built around a commercial off-the-shelf (COTS) radio frequency identification (RFID) transceiver (MLX90121) operating at 13.56 MHz. It can be used for inductively powering implantable biomedical devices in a closed loop fashion. Any changes in the distance and misalignment between transmitter and receiver coils in near-field wireless power transmission can cause a significant change in the received power, which can cause either malfunction or excessive heat dissipation. RFID transceivers are often used open loop. However, their back telemetry capability can be utilized to stabilize the received voltage on the implant. Our measurements showed that the delivered power to the transponder was maintained at 1.48 mW over a range of 6 to 12 cm, while the transmitter power consumption changed from 0.3 W to 1.21 W. The closed loop system can also oppose voltage variations as a result of sudden changes in load current.

We have developed a novel analog front-end part of a wireless brain oxymeter receiver instrument based on near-infrared spectroreflectometry (NIRS). The NIRS receiver makes use of dynamic threshold transistors (DTMOS) for low voltage (1–V), low power and low noise enhancement. The design is composed of a transimpedance amplifier (TIA) and an operational transconductance amplifier (OTA). The OTA differential input pairs are in a class AB configuration, and uses DTMOS devices for input common-mode range enhancement. Post-layout simulations under a 5 pF load, using 0.18 µm CMOS technology results are, for the OTA, an input referred noise of 134 nV/√Hz at 1 kHz, and a power consumption of 16.7 µW without any extra noise reduction technique. Also, the TIA gives 208 pA/√Hz at 1 kHz, while having a power consumption of only 10.9 µW. The proposed analog front-end circuits have been used to implement a NIRS receiver instrument with improved ultra low-light level measurements, high resolution...

Multiplexing is the generic term used to designate the operation of sending one or more analogue or digital signals over a common transmission line at dissimilar times or speeds and as such, the scheme we use to do just that is called a Multiplexer. In digital electronics, multiplexers are similarly known as data selectors as they can "select" each input line, are made from individual Analogue Switches encased in a single IC package as conflicting to the "mechanical" type selectors such as standard conservative switches and relays. In today era, reversibility has become essential part of digital world to make digital circuits more efficient. In this paper, we have proposed a new method to reduce quantum cost and power for various multiplexers. The results are simulated in Xilinx by using VHDL language.