Logarithmic number system

Digital signal processing applications often use major mathematical operations such as multiplication, which consume more power and time. Operations like Fast Fourier Transform, Convolution and correlation depends heavily on a large number of multiplications. There are many techniques available to perform multiplications. One such technique is logarithmic multiplication. logarithmic multiplication is achieved by adding the binary logarithms of two numbers and deriving the antilog of the result. In this paper, an efficient algorithm for logarithmic multiplication is presented with the use of adders, decoders, multiplexers and a few combinational circuits that effectively reduce the power and area of the multiplier

Digital signal processing applications often use major mathematical operations such as multiplication, which consume more power and time. Operations like Fast Fourier Transform, Convolution and correlation depends heavily on a large number of multiplications. There are many techniques available to perform multiplications. One such technique is logarithmic multiplication. logarithmic multiplication is achieved by adding the binary logarithms of two numbers and deriving the antilog of the result. In this paper, an efficient algorithm for logarithmic multiplication is presented with the use of adders, decoders, multiplexers and a few combinational circuits that effectively reduce the power and area of the multiplier

Digital signal processing applications often use major mathematical operations such as multiplication, which consume more power and time. Operations like Fast Fourier Transform, Convolution and correlation depends heavily on a large number of multiplications. There are many techniques available to perform multiplications. One such technique is logarithmic multiplication. logarithmic multiplication is achieved by adding the binary logarithms of two numbers and deriving the antilog of the result. In this paper, an efficient algorithm for logarithmic multiplication is presented with the use of adders, decoders, multiplexers and a few combinational circuits that effectively reduce the power and area of the multiplier.

ÐA new European research project aims to develop a microprocessor based on the logarithmic number system, in which a real number is represented as a fixed-point logarithm. Multiplication and division therefore proceed in minimal time with no rounding error. However, the system can only offer an overall advantage over floating-point if addition and subtraction can be performed with speed and accuracy at least equal to that of floating-point, but these operations require the interpolation of a nonlinear function which has hitherto been either time-consuming or inaccurate. We present a procedure by which additions and subtractions can be performed rapidly and accurately and show that these operations are thereby competitive with their floating-point equivalents. We then present some large-scale case studies which show that the average performance of the LNS exceeds floating-point, in terms of both speed and accuracy.

In this paper, a simple CPU with MDLNS extensions is presented. The logarithmic characteristic of MDLNS makes it perfectly suitable in multiplication intensive algorithms. The CPU takes advantage of a straight forward architecture which greatly simplifies the implementation for examining the MDLNS in many DSP applications. To maintain design simplicity, only 2-digit 2DLNS (2 bases) representations and operations have been considered. As an practical application of CPU, an assembly program is written to implement a simple filterbank based on a 2DLNS processing architecture. This implementation demonstrates the efficiency and efficacy of 2DLNS CPU in real applications.

A BSTRA GT In this paper, a novel algorithm for multi-operand Logarithmic Number System (LNS) addition and subtraction is presented. In particular. the computation of the nonlinear functions required for logarithmic addition and subtraction is deconiposed into computing Y", ...