DESIGN OF AN AREA EFFICIENT 16-BIT LOGARITHMIC MULTIPLIER

2019 Design, Automation & Test in Europe Conference & Exhibition (DATE), 2019

Logarithmic multipliers take the base-2 logarithm of the operands and perform multiplication by only using shift and addition operations. Since computing the logarithm is often an approximate process, some accuracy loss is inevitable in such designs. However, the area, latency, and power consumption can be significantly improved at the cost of accuracy loss. This paper presents a novel method to approximate log2N that, unlike the existing approaches, rounds N to its nearest power of two instead of the highest power of two smaller than or equal to N. This approximation technique is then used to design two improved 16×16 logarithmic multipliers that use exact and approximate adders (ILM-EA and ILM-AA, respectively). These multipliers achieve up to 24.42% and 9.82% savings in area and power-delay product, respectively, compared to the state-of-the-art design in the literature with similar accuracy. The proposed designs are evaluated in the Joint Photographic Experts Group (JPEG) image compression algorithm and their advantages over other approximate logarithmic multipliers are shown.

2010

Digital signal processing algorithms often rely heavily on a large number of multiplications, which is both time and power consuming. However, there are many practical solutions to simplify multiplication, like truncated and logarithmic multipliers. These methods consume less time and power but introduce errors. Nevertheless, they can be used in situations where a shorter time delay is more important than accuracy. In digital signal processing, these conditions are often met, especially in video compression and tracking, where integer arithmetic gives satisfactory results. This paper presents and compare different multipliers in a logarithmic number system. For the hardware implementation assessment, the multipliers are implemented on the Spartan 3 FPGA chip and are compared against speed, resources required for implementation, power consumption and error rate. We also propose a simple and efficient logarithmic multiplier with the possibility to achieve an arbitrary accuracy through an iterative procedure. In such a way, the error correction can be done almost in parallel (actually this is achieved through pipelining) with the basic multiplication. The hardware solution involves adders and shifters, so it is not gate and power consuming. The error of proposed multiplier for operands ranging from 8 bits to 16 bits indicates a very low relative error percentage.

IOSR Journal of Electrical and Electronics Engineering, 2014

A multiplier is one of the key hardware blocks in most digital and high performance systems such as FIR filters, digital signal processors and microprocessors etc. many researchers have tried and are trying to design multipliers which offer either of the following-high speed, low power consumption, less area, more accuracy or even combination of them in multiplier. This paper presents a simple and efficient logarithmic multiplier with the possibility to achieve a maximum accuracy with less area and low power Consumption through an iterative procedure with recursive logic. The proposed modified iterative logarithmic multiplier is based on the same form of number representation as Mitchell's algorithm [1962], but for error correction it uses different algorithm proposed by Z. Babic, A. Avramovic , P. Bulic [2011]. And to make it more efficient instead of array of basic block proposed by Z. Babic, A. Avramovic , P. Bulic [2011] it contain only single basic block with recursive logic which finds approximate product and also error correction terms. Due to that it is less area and power consuming in expense of slightly increase in delay. Because there is always trade off between Area and delay. In order to evaluate the performance of the proposed multiplier and compare it with previous works, we implemented four 16-bit multipliers proposed by Z. Babic, A. Avramovic , P. Bulic [2011]: a pipelined multiplier with no correction terms and three pipelined multipliers with one, two and three correction terms and one 16-bit proposed Modified iterative logarithmic multiplier on the Xilinx xc3s1500-5fg676 FPGA.

International Journal of Engineering & Technology

Multiplication is one of important arithmetic component for digital signal processing, neural network and image processing. But, it is well known fact that multiplier has most hardware consuming component out of all arithmetic components. Here, it is given a possible solution by using an efficient VLSI architecture of Mitchell’s algorithm based Iterative Logarithmic Multiplier (ILM) with modified architecture of Leading One Detector (LOD) and seamless pipelined technique. The proposed work is based on the hardware minimization at the same error cost than of previously reported architectures. We use VHDL to design the existing and proposed Mitchell’s algorithm based iterative logarithmic multiplier. Both multipliers design are evaluated with the Synopsys design compiler by using 90 nm CMOS technology and compared the results in terms of Data Arrival Time (DAT), area, power, Area Delay Product (ADP) and energy. The proposed Mitchell's based ILM gives 33.18 %, 39.03 % and 31.62 % l...

In many real-time DSP applications, performance is a prime target. However, achieving high performance may be done at the expense of area and power dissipation. Attempts have been made to use alternative number systems to optimize the realization of arithmetic blocks, so as to maintain high performance without increasing area and power. For this we used Logarithmic Number System in base two. By using this number system, we can achieve highly optimized realizations of functions such as multiplication, division and square root. Complex multiplication is one of the critical operations in various wireless and DSP applications. Complex multiplication requires a large area for implementation and consumes high power as the input width increases from 16 to 32 bits. Using the Logarithmic Number System can transform this operation into few additions and subtractions. The corresponding savings can even compensate for the additional costs of number system conversions at the input and output. In this paper we have design an optimized logarithmic multiplier based on Mitchell’s Algorithm [1]. The design uses an iterative method to implement the logarithmic multiplier so as to increase the speed of multiplication, and reduce the number of logic blocks used to design it. For the design entry, we used the Xilinx ISE 13.2 - Web-PACK and designed with Verilog HDL. The design was synthesized with the Xilinx XST Release 13.2 for Windows. When using Xilinx xc3s1500-5fg676 device, the pipelined implementation of the basic block uses 4.63% fewer number of slices and 6.93% fewer number of 4 input LUTs than the reference design [8]. The total power consumed by the pipelined basic block is 2.92% less than the reference design [8].

Integration, the VLSI Journal

Over the last few years, the Logarithmic Number System (LNS) has played a pivotal and decisive role in the field of Digital Signal Processing (DSP) and Image processing. Multiplication is a ubiquitous thirsty area to perform arithmetic operations in DSP applications and researchers have found that LNS is the possible solution for multiplication to be performed for a DSP application. In this paper, we propose a novel approach based on the Improved Operand Decomposition (IOD) to make an efficient logarithmic multiplier and subsequent the achievement through scale realization. The Pipeline technique and the efficient correction circuit are used for error minimization at the cost of minimal hardware and delay. Reported and proposed multiplier is evaluated and compared in terms of Data Arrival Time (DAT), area, power, Area Delay Product (ADP), and EPS (Energy per Sample) at 90 nm CMOS technology by using Synopsys design compiler. Simulation results show that the proposed IOD method for logarithmic multiplication without the pipelining gives maximum of 35.39 % less ADP and 11.15% less EPS for 32-bit architecture than of the reported logarithmic multiplier architecture. The proposed IOD based logarithmic multiplier with the pipelining gives a maximum of 20.17 % less ADP for 8-bit architecture and 21.72 % for 32-bit architecture than of the reported iterative pipelined architecture of logarithmic multiplication. Simulation results show that the optimized logarithmic converter gives 7.32 %, and optimized antilogarithmic converter gives 41.59 % less ADP respectively than of the reported logarithmic and antilogarithmic converter structures. The optimized antilogarithmic converter architecture gives a maximum of 43.94 % less EPS than of the reported antilogarithmic converter structure.

In last four decades, the Logarithmic Number System (LNS) is the most vocative words in the field of arithmetic operations (like addition, subtraction, multiplication, and division). In all arithmetic operations multiplication is most area consuming component, but researchers have analyzed that, LNS has potential to solve this problem. Hence, this paper gives a detailed and meaningful discussion of the evolution of LNS, systematic developments of the LNS multiplier architecture design, highlights the research areas, a further possibility of improvements, their limitations and finally application in the various fields.

International Journal of Circuit Theory and Applications, 2020

Real-time digital signal and image processing applications, such as filtering, demand high performance. Often, multiplication is one of the most timeconsuming steps of the filtering operation. Log-based multipliers have been used for improving multiplication efficiency at the expense of accuracy. The objective of the proposed work is to improve the accuracy of log-based hardware multipliers by appropriately altering the filter weights and without increasing the required resources. 1 | INTRODUCTION Filtering is a computationally expensive but widely used operation in image and signal processing applications including image enhancement, 1 smoothing, 2,3 and edge detection. 4 Hardware filtering implementations often have high circuitry and power consumption requirements, mainly due to the use of multipliers. Log-based multipliers convert multiplications and divisions to more efficient operators, namely, additions and subtractions, at the expense of accuracy. Mitchell 5 first proposed a method for implementing log-based multipliers using a piecewise linear approximation technique. Although the log and anti-log functions in Mitchell method are hardware efficient, they produce large average errors. Attempts have been made to improve Mitchell approximation by proposing several error correction circuits. These methods include Mitchell-based methods, 6-9 lookup table (LUT)-based methods, 10-14,19,20 and region-based approaches. 15-21 This work concentrates on filtering (convolution) applications, where the filter weights are known and fixed. The proposed method employs Mitchell multiplier but optimizes the filter weights so that the convolution error is reduced. Before presenting the proposed method, some background information about existing log-based multipliers is provided. 2 | REVIEW OF LOGARITHMIC MULTIPLIERS 2.1 | Mitchell logarithmic multiplier Mitchell multiplier 5 uses a piecewise linear approximation of the log 2 (N) curve, as shown in Figure 1 for an integer N. The method is exact when N is a power of 2. The binary representation of N

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