state machine

This article describes a self-healing mechanism for statemachine based distributed components. Each component is composed of two layers: a healing (HL) and a service or functional layer (FL). At least, the functional layer must be implemented according to a statemachine specification. The healing layer has the capacity of monitoring the service layer of the component of witch it is a part and responsible of. In the event of a failure of the functional layer, the healing layer acts on it in terms of states. It will be shown that this mechanism, being consistent with classical faulttolerance strategies, allows the HL to act on the FL in a more precise way than employing an entire software module as a replacement unit. It will be shown also that this mechanism is suitable for hot-swapping software modules.

Model-based selective regression testing promises reduction in cost and labour by selecting a subset of the test suite corresponding to the modifications after system evolution. However, identification of modifications in the systems and selection of corresponding test cases is challenging due to interdependencies among models. State-based testing is an important approach to test the system behaviour. Unfortunately the existing state-based regression testing approaches do not care for dependencies of the state machine with other system models. This paper presents the tool support and evaluation of our statebased selective regression testing methodology for evolving state-based systems. START is an Eclipsebased tool for state-based regression testing compliant with UML 2.1 semantics. START deals with dependencies of state machines with class diagrams to cater for the change propagation. We applied the START on a case study and our results show significant reduction in the test cases ...

This paper, describes the design and development of a Supervisory Control System (SCS) for an Electric Vehicle (EV) developed by The Applied Electronics Group. The SCS was implemented on a Panel PC, and the Controller Area Network protocol was used as the communication interface with the Traction Controller. This scheme allows implementing the complete control of the EV as two-level architecture, where the SCS works as a high-level controller coordinating the low-level subsystems (traction, batteries, etc.). I.

This paper describes a process to reverse engineer structural and behavioural formal models of a GUI application by a dynamic technique, mixing manual with automatic exploration. The goal is to diminish the effort required to construct the model and mapping information needed in a model-based GUI testing process. A skeleton of a state machine model of the GUI, represented in a formal pre/post specification language, is generated automatically by the exploration process. Mapping information between the model and the ...

This paper introduces an analysis and design of a digital controlled double loop voltage-current for a buck converter. Taking into account the implementation requirements, the chosen platform was an Field-Programmable Gate Array (FPGA). This paper also shows in detail the analog-digital interface. The study is completed by a detailed analysis of the FPGA programming including states machines and logic diagrams. Finally, theoretical results are validated with extensive simulations.

This paper focuses on verification and validation of a model dedicated to mode handling of flexible manufacturing systems (FMSs). This model is specified using the synchronous formalism safe state machines (SSMs). The rigorous semantics that characterize such formalism enable to provide formal verification mechanisms ensuring determinism and dependability. A structured framework for verification and validation of the model dedicated to mode handling is proposed. The main properties being verified within this framework and the corresponding verification methods are presented. The approach is illustrated using an example of a manufacturing production cell. The formal analysis tools integrated into the development environment Esterel Studio are used within the design process. ß

Una Máquina de Estado Finito (Finite State Machine), llamada también Autómata Finito es una abstracción computacional que describe el comportamiento de un sistema reactivo mediante un número determinado de Estados y un número determinado de Transiciones entre dicho Estados.

Currently, Model-Driven Engineering (MDE) is considered one of the most promising approaches for software development. In this paper, a simple but complete example based on state-machines will be used to demonstrate the benefits of this approach. After defining a modelling language (meta-model) for statemachines, a graphical tool will be presented which is aimed at easing the description and validation of state-machine models. These models will then be used as inputs for another tool which will automatically generate the corresponding Ada code, including a simulation program to test the correctness and performance of the implemented application. This work has been partially funded by the Spanish CICYT project MEDWSA (TIN2006-15175-C05-02) and the PMPDI-UPCT-2006 program (Universidad Politécnica de Cartagena).

SAL (see http://sal.csl.sri.com) is an open suite of tools for analysis of state machines; it constitutes part of our vision for a Symbolic Analysis Laboratory that will eventually encompass SAL, the PVS verification system, the ICS decision procedures, and other tools developed in our group and elsewhere. SAL provides a language similar to that of PVS, but specialized for the specification of state machines; it was first released with an explicit-state model checker as SAL 1 in July 2002; SAL 2, which was released in December 2003, adds high-performance symbolic and bounded model checkers, and novel infinite bounded and witness model checkers. Both the bounded model checkers can additionally perform verification by k-induction, and the capabilities of all the model checkers and their components are available through an API that is scriptable in Scheme.

Nested words are a structured model of execution paths in procedural programs, reflecting their call and return nesting structure. Finite nested words also capture the structure of parse trees and other tree-structured data, such as XML. We provide new temporal logics for finite and infinite nested words, which are natural extensions of LTL, and prove that these logics are first-order expressively-complete. One of them is based on adding a "within" modality, evaluating a formula on a subword, to a logic CaRet previously studied in the context of verifying properties of recursive state machines (RSMs). The other logic, NWTL, is based on the notion of a summary path that uses both the linear and nesting structures. For NWTL we show that satisfiability is EXPTIME-complete, and that model-checking can be done in time polynomial in the size of the RSM model and exponential in the size of the NWTL formula (and is also EXPTIME-complete). Finally, we prove that first-order logic over nested words has the three-variable property, and we present a temporal logic for nested words which is complete for the two-variable fragment of first-order.

The development of flexible and inexpensive controller for large scale light emitting diode (LED) video display image rendering is presented. The concept and system components of such system are presented. Controller is capable of discrete pixel intensity dimming by using the pulse width modulation (PWM). It can control the LED boards containing pixel arrays or the individual pixels/pixel strings. High dimming resolution usually contradicts with high refresh frequency and number of controllable LEDs. Thanks to novel dimming technique the dimming resolution can be varied without significant loss of refresh frequency or number of controllable LEDs. Data between the structure blocks circulates in a series fashion using the conventional shielded twisted pair (STP) cable. The structure and functional diagram of the serializer and deserializer needed for data transmission are presented. Control is accomplished by personal computer (PC) via a high speed universal serial bus (USB2) interfac...

Aspect-oriented programming modularizes crosscutting concerns into aspects with the advice invoked at the specified points of program execution. Aspects can be used in a harmful way that invalidates desired properties and even destroys the conceptual integrity of programs. To assure the quality of an aspect-oriented system, rigorous analysis and design of aspects are highly desirable. In this paper, we present an approach to aspect-oriented modeling and verification with finite state machines. Our approach provides explicit notations (e.g., pointcut, advice and aspect) for capturing crosscutting concerns and incremental modification requirements with respect to class state models. For verification purposes, we compose the aspect models and class models in an aspect-oriented model through a weaving mechanism. Then we transform the woven models and the class models not affected by the aspects into FSP (Finite State Processes), which are to be checked by the LTSA (Labeled Transition System Analyzer) model checker against the desired system properties. We have applied our approach to the modeling and verification of three aspect-oriented systems. To further evaluate the effectiveness of verification, we created a large number of flawed aspect models and verified them against the system requirements. The results show that the verification has revealed all flawed models. This indicates that our approach is effective in quality assurance of aspect-oriented state models. As such, our approach can be used for model-checking state-based specification of aspect-oriented design and can uncover some system design problems before the system is implemented.

The control structure of many real-time applications are naturally described by state machines. However, the state transitions of these machines are governed not only by the state of the system and the occurrence of events, but also by their time of occurrence. The control structure of a realtime system determines what computation to perform and the set of timing constraints in effect at all times. The computation performed by the system can then be modeled by a directed graph, where the nodes denote transformations on the data and the edges denote data flow. In this paper, we discuss some research issues that arise from the integration of control flow with data flow.

Behaviour analysis should form an integral part of the software development process. This is particularly important in the design of concurrent and distributed systems, where complex interactions can cause unexpected and undesired system behaviour. We advocate the use of a compositional approach to analysis. The software architecture of a distributed program is represented by a hierarchical composition of subsystems, with interacting processes at the leaves of the hierarchy. Compositional reachability analysis (CRA) exploits the compositional hierarchy for incrementally constructing the overall behaviour of the system from that of its subsystems. In the Tracta CRA approach, both processes and properties reflecting system specifications are modelled as state machines. Property state machines are composed into the system and violations are detected on the global reachability graph obtained. The property checking mechanism has been specifically designed to deal with compositional techniques. Tracta is supported by an automated tool compatible with our environment for the development of distributed applications.

Several techniques for database replication using group communication have recently been proposed, namely, the Database State Machine, Postgres-R, and the NODO protocol. Although all rely on a totally ordered multicast for consistency, they differ substantially on how multicast is used. This results in different performance trade-offs which are hard to compare as each protocol is presented using a different load scenario and evaluation method. In this paper we evaluate the suitability of such protocols for replication of On-Line Transaction Processing (OLTP) applications in clusters of servers and over wide area networks. This is achieved by implementing them using a common infrastructure and by using a standard workload. The results allows us to select the best protocol regarding performance and scalability in a demanding but realistic usage scenario.

We present a framework for verifiable concurrent programming in Java based on a design pattern for concurrency controllers. Using this pattern, a programmer can write concurrency controller classes defining a synchronization policy by specifying a set of guarded commands and without using any of the error-prone synchronization primitives of Java. We present a modular verification approach that exploits the modularity of the proposed pattern, i.e., decoupling of the controller behavior from the threads that use the controller. To verify the controller behavior (behavior verification) we use symbolic and infinite state model checking techniques, which enable verification of controllers with parameterized constants, unbounded variables and arbitrary number of user threads. To verify that the threads use a controller in the specified manner (interface verification) we use explicit state model checking techniques, which allow verification of arbitrary thread implementations without any restrictions. We show that the correctness of the user threads can be verified using the concurrency controller interfaces as stubs, which improves the efficiency of the interface verification significantly. We also show that the concurrency controllers can be automatically optimized using the specific notification pattern. We demonstrate the effectiveness of our approach on a Concurrent Editor implementation which consists of 2800 lines of Java code with remote procedure calls and complex synchronization constraints.

Believable agents designed for long-term interaction with human users need to adapt to them in a way which appears emotionally plausible while maintaining a consistent personality. For short-term interactions in restricted environments, scripting and state machine techniques can create agents with emotion and personality, but these methods are labor intensive, hard to extend, and brittle in new environments. Fortunately, research in memory, emotion and personality in humans and animals points to a solution to this problem. Emotions focus an animal's attention on things it needs to care about, and strong emotions trigger enhanced formation of memory, enabling the animal to adapt its emotional response to the objects and situations in its environment. In humans this process becomes reflective: emotional stress or frustration can trigger reevaluating past behavior with respect to personal standards, which in turn can lead to setting new strategies or goals. To aid the authoring of adaptive agents, we present an artificial intelligence model inspired by these psychological results in which an emotion model triggers case-based emotional preference learning and behavioral adaptation guided by personality models. Our tests of this model on robot pets and embodied characters show that emotional adaptation can extend the range and increase the behavioral sophistication of an agent without the need for authoring additional hand-crafted behaviors.

This paper presents a novel approach to synthesize low power FSMs using non-uniform code length Switching activity i s reduced by decreasrng the ezpected number of state bits switched less than [log lSl1. The state set S of the F S M 2s decomposed into two sets based on the ltmit state probabilitres. The state set with very hxgh probability is encoded with less than rlogISi1 bits. The other state set, being less probable. IS encoded usxng more than rloglSi1 bits. To the best of our knowledge, this i s the first time two code lengths are used for one state machine This encoding is realized by using Ptp-flops with gated clock The loyrc generating the enable signal of the clock uses only a srngle mrnterm. The state sets can be encoded using any uniform-length encodrng algorithm with objectives of low power and low area. The eiperrments show an average of 13% and 18% reduction rn power f o r two encoding algorithms respectively.

Decreasing the program size has become an important goal in the design of embedded systems target to mass production. This problem has led to a number of efforts aimed at designing processors with shorter instruction formats (e.g. ARM Thumb and MIPS16), or that can execute compressed code (e.g. IBM CodePack PowerPC). Much of this work has been directed towards RISC architectures though. This paper proposes a solution to the problem of executing compressed code on embedded DSPs. The experimental results reveal an average compression ratio of 75% for typical DSP programs running on the TMS320C25 processor. This number includes the size of the decompression engine. Decompression is performed by a state machine that translates codewords into instruction sequences during program execution. The decompression engine is synthesized using the AMS standard cell library and a 0.6m 5V technology. Gate level simulation of the decompression engine reveals minimum operation frequencies of 150MHz.

Finite State Machines (FSM) provide a powerful way to describe dynamic behavior of systems and components. Implementations of FSM in Object-Oriented (OO) languages have been widely studied since the classical State design pattern has been introduced. Various design patterns were derived from the State pattern, however, the focus was always on object's behavior. This paper proposes the Persistent State Pattern, an extension to the State pattern where persistent data is taken on account. The Persistent State Pattern integrates classical and enterprise design patterns, and it is conceived for enterprise applications. It can be used with OO databases and relational databases, and it can also be incorporated by an object-relation mapping framework. We present the close relationship between the Persistent State Pattern and the concepts of model and event driven design. * Corresponding author. Relationship Model (ERM) [6]), takes part of a business process or a workflow. Processes and workflows may be executed by various actors and must be able to be persistent. A database entity which is part of the process may be persisted in different states. Let us take as example a purchase process, in a company, which could be summarized by the following steps: i) a professional in the company's operation creates a purchase request, which is modeled by an entity called PurchaseRequest; ii) the purchase request is evaluated by the company's financial office before, and it can be approved or rejected; iii) the purchase office contacts suppliers and negociates prices; iv) the financial office pays; v) the product is delivered. During this process, the Pur-chaseRequest entity changes it's state several times. The PurchaseRequest entity could have, for instance, the states elaborating, approved, rejected, and others. Since there are different actors interacting with the entity, the entity's state must be persistent.

A Framework for Executable UML Models Joe Mooney General Dynamics Scottsdale, Arizona Email: [email protected] ... Time is counted via event ticks, which are simulations of real time. The elapsed real (wall clock) time between each tick may be of varying duration. ...

We propose an Hierarchical State Machine (HSM) model for specifying behavioral interfaces of peers participating in a composite web service. We integrate the HSM model to a design pattern which is supported by a modular verification technique that can 1) statically analyze the properties about global interactions of a composite web service and 2) check the conformance of the Java implementations of the participant peers to their interfaces. We extend the synchronizability analysis to HSMs to efficiently identify composite web services whose global interactions can be analyzed with respect to unbounded queues using finite state model checkers. We also discuss automated translation of behavioral interfaces specified as HSMs to BPEL specifications to be published and used by other services.

X3D-UML utilises X3D (eXtensible 3D) to enable standards-based advanced 3D UML visualisations. Using X3D-UML, 3D UML State Machine Diagrams have been evaluated against actual user tasks and data, using the Sequential Evaluation methodology. The results of User Task Analysis, Heuristic Evaluation and Formative Evaluation phases provide clear evidence that the use of UML extended with 3D is a practical solution for visualising complex system behaviour. RoseRT model metrics show between 56%-90% of state machine diagram work would benefit from such 3D UML extensions; hence the 3D improvement can deliver considerable benefit to organisations.

Since class objects are the major components in object-oriented (00) programs during run-time, testing the behavior of these objects become an important task in testing of object-oriented programs to comple ment other types of testing, such as, structuretesting and functional testing. To check the behavior of objects in 00 programs, it is essential to check each state and each transition for every object. This paper proposes a new test model, called object state diagram, to capture and represent the dynamic behavior of objects in an 00 program. The model is an extension of the existing state models, it supports basic 00 features, such as class objects, inheritance, aggregation and overloading. Unlike other models, it is a concurrent, communicating state machine which has the capability of representing the object state hierarchy for a complex class object. Based on this model we address the issues and solutions to object state test strategy, test criteria and test generation.

The underlying model of computation for PROMELA is based on interacting processes with asynchronous communication, and hence SPIN has been mainly used as a verification engine for concurrent software systems. On the other hand, hardware verification has mostly focused on clock synchronous register-transfer level (RTL) models. As a result, verification tools such as SMV which are based on synchronous state machine models have been used more frequently for hardware verification. However, as levels of abstractions are being ...

This dissertation focuses on the area of improving programming language support for constructing fault-tolerant systems. Specifically, the design and implementation of FT-SR, a programming language developed for building a wide variety of fault-tolerant systems, is described. FT-SR is based on the concurrent programming language SR and is designed as a set of extensions to SR. A distinguishing feature of FT-SR is the flexibility it provides the programmer in structuring fault-tolerant software. It is flexible enough to be used for structuring systems according to any of the standard fault-tolerance structuring paradigms that have been developed for such systems, including the object/action model, the restartable action paradigm, and the state machine approach. This is especially important in systems building because different structuring paradigms are often appropriate for different parts of the system. This flexibility sets FT-SR apart from other fault-tolerant programming languages which provide language support for the one paradigm that is best suited for the class of applications they choose to support. FT-SR, on the other hand, is suitable for programming a variety of systems and applications. FT-SR derives its flexibility from a programming model based on fail-stop atomic objects. These objects execute operations as atomic actions except when a failure or series of failures cause underlying implementation assumptions to be violated; in this case, notification is provided. This dissertation argues that fail-stop atomic objects are the fundamental building blocks for all fault-tolerant programs. FT-SR provides the programmer with simple fail-stop atomic objects, and mechanisms that allow these failstop atomic objects to be composed to form higher-level fail-stop atomic objects that can tolerate a greater number of faults. The mechanisms for composing fail-stop atomic objects are based on standard redundancy techniques. This ability to combine the basic building blocks in a variety of ways allows programmers to structure their programs in a manner best suited to the application at hand.

The State Machine model is frequently used to represent the behaviour of a system, allowing one to express and execute this behaviour in a deterministic way. A graphical representation such as a UML State Chart diagram tames the complexity of the system, thus facilitating changes to the model and communication between developers and domain experts. We present a reusable state machine code generator, developed by the Universidad Técnica Federico Santa María and the European Southern Observatory. The generator itself is based on the open source project architecture, and uses UML State Chart models as input. This allows for a modular design and a clean separation between generator and generated code. The generated state machine code has well-defined interfaces that are independent of the implementation artefacts such as the middle-ware. This allows using the generator in the substantially different observatory software of the Atacama Large Millimeter Array and the ESO Very Large Telesc...

Event-driven programming is a popular model for writing programs for tiny embedded systems and sensor network nodes. While event-driven programming can keep the memory overhead down, it enforces a state machine programming style which makes many programs difficult to write, maintain, and debug. We present a novel programming abstraction called protothreads that makes it possible to write eventdriven programs in a thread-like style, with a memory overhead of only two bytes per protothread. We show that protothreads significantly reduce the complexity of a number of widely used programs previously written with event-driven state machines. For the examined programs the majority of the state machines could be entirely removed. In the other cases the number of states and transitions was drastically decreased. With protothreads the number of lines of code was reduced by one third. The execution time overhead of protothreads is on the order of a few processor cycles.

Financial forecasting is an example of a signal processing problem which is challenging due to small sample sizes, high noise, non-stationarity, and non-linearity. Neural networks have been very successful in a number of signal processing applications. We discuss fundamental limitations and inherent difficulties when using neural networks for the processing of high noise, small sample size signals. We introduce a new intelligent signal processing method which addresses the difficulties. The method proposed uses conversion into a symbolic representation with a self-organizing map, and grammatical inference with recurrent neural networks. We apply the method to the prediction of daily foreign exchange rates, addressing difficulties with non-stationarity, overfitting, and unequal a priori class probabilities, and we find significant predictability in comprehensive experiments covering 5 different foreign exchange rates. The method correctly predicts the direction of change for the next day with an error rate of 47.1%. The error rate reduces to around 40% when rejecting examples where the system has low confidence in its prediction. We show that the symbolic representation aids the extraction of symbolic knowledge from the trained recurrent neural networks in the form of deterministic finite state automata. These automata explain the operation of the system and are often relatively simple. Automata rules related to well known behavior such as trend following and mean reversal are extracted.

This paper addresses the problem of automatic generation of implementation software from high-level functional specifications in the context of embedded system on chip designs. Software design complexity for embedded systems has increased so much that a high-level functional programming paradigm need to be adopted for formal verifiability, maintainability and short time-to-market. We propose a framework for efficiently generating implementation software from a synchronous state machine specification for embedded control systems. The framework is generic enough to allow hardware/software partition for a given architecture platform. It is demonstrated that the logic optimization and simulation techniques can be combined to produce fast execution code for such embedded systems. Specifically, we propose a framework for software synthesis from multi-valued logic, including fast evaluation of logic functions, and scheduling techniques for node execution. Experiments are performed to show the initial results of our algorithms in this framework.

The need of communication protocols in todaypsilas environment increases as much as the network explores. Many new kinds of protocols, e.g. for information sharing, security, etc., are being developed day-to-day which often leads to rapid, premature developments. Many protocols have not scaled to satisfy important properties like deadlock and livelock freedom, since MDA focuses on the rapid development rather than on the quality of the developed models. In order to fix the above, we introduce a 2-Phase strategy based on the UML state machine and sequence diagram to satisfy the properties of communication protocols. We convert these models into PROMELA code for execution on the SPIN model checker. The results are compared with the developed UML models.

The importance of providing a mechanism to call C functions from high-level languages has been understood for many years and, these days, almost all statically-typed high-level-language implementations provide such a mechanism. One glaring omission, however, has been support for calling variadic C functions, such as printf. Variadic functions have been ignored because it is not obvious how to give static types to them and because it is not clear how to generate calling sequence when the arguments to the function may not be known until runtime. In this paper, we address this longstanding omission with an extension to the NLFFI foreign-interface framework used by Standard ML of New Jersey (SML/NJ) and the MLton SML compiler. We describe two different ways of typing variadic functions in NLFFI and an implementation technique based on the idea of using state machines to describe calling conventions. Our implementation is easily retargeted to new architectures and ABIs, and can also be easily added to any HOT language implementation that supports calling C functions.

It is common for large designs to have heterogeneous components interacting with each other. These components often follow a particular model of computation such as controllers modeled using state machines, signal processing filters modeled as data flow and event-based components using discrete-event. Hence, there are several academic and industrial attempts at incorporating heterogeneity into the design flow, primarily in system level design languages and frameworks for modeling and simulation. A variety of attempts are proposed such as extending simulation kernels for existing frameworks and simply using language constructs to mimic other models of computation. However, the benefit of one over the other is not apparent to the designer and thus not clear which of the two is a better strategy for EDA tools to integrate. In this paper we argue whether Deep heterogeneity (kernel-level) or Shallow heterogeneity (language-level) is a suitable strategy for introducing heterogeneity in system level design languages and frameworks.

... Add to: Digg Furl. Spurl Blink. Simpy Google. Del.icio.us Y!MyWeb. Search, Similar Articles; Articles by Steven Silverman. ASCII Text. x, Steven Silverman, "Games Theory and Software Defined Radios," MILCOM, pp. 1-7, MILCOM 2006, 2006. BibTex. x, ...

The design of fault-tolerant real-time systems is an area of great research activity, particularly in the context of safety-critical systems like spacecrafts. The present work describes the design, implementation, and proof of a fault-tolerant server in a transputer network. The software was developed in Occam with in-line GUY code at certain places to improve performance. Byzantine faults are tolerated and the basic strategy is failure-masking by replication.

Requirements engineers need to make sure that the requirements models and specifications they are building do accurately capture what stakeholders really want. Requirements animation has been recognized to be a promising approach to support this. The principle is to simulate an executable version of the requirements model and to visualize the simulation in some form appealling to stakeholders. Most animation

Distributed network protocols operate similar to periodic state machines, utilizing internal states and timers, for network coordination. This creates opportunities for carefully engineered radio jamming to target the protocol operating periods and disrupt network communications. Such periodic attacks targeting specific protocol period/frequency of operation is referred to as Null Frequency Jamming (NFJ). In this paper, we investigate NFJ targeted at

We present Odin, an SDN framework to introduce programmability in enterprise wireless local area networks (WLANs). Enterprise WLANs need to support a wide range of services and functionalities. This includes authentication, authorization and accounting, policy, mobility and interference management, and load balancing. WLANs also exhibit unique challenges. In particular, access point (AP) association decisions are not made by the infrastructure, but by clients.

Combining discrete state-machines with continuous behavior, hybrid systems are a well-established mathematical model for discrete systems acting in a continuous environment. As a priori infinite state systems, their computational properties are undecidable in the general model and the main line of research concentrates on model checking of finite abstractions of restricted subclasses of the general model. In our work, we use deductive methods, falling back upon the general-purpose theorem prover PVS. To do so we extend the classical approach for the verification of state-based programs by developing an inductive proof method to deal with the parallel composition of hybrid systems. The methods cover shared variable communication, label-synchronization, and especially the common continuous activities in the parallel composition of hybrid automata. Besides hybrid systems and their parallel composition, we formalized their operational step semantics and a number of proof-rules within PV...

We describe an application of inductive logic programming to transfer learning. Transfer learning is the use of knowledge learned in a source task to improve learning in a related target task. The tasks we work with are in reinforcement-learning domains. Our approach transfers relational macros, which are finite-state machines in which the transition conditions and the node actions are represented by first-order logical clauses. We use inductive logic programming to learn a macro that characterizes successful behavior in the source task, and then use the macro for decision-making in the early learning stages of the target task. Through experiments in the RoboCup simulated soccer domain, we show that Relational Macro Transfer via Demonstration (RMT-D) from a source task can provide a substantial head start in the target task. isClose(Opponent) hold :true pass(Teammate) :-isOpen(Teammate) not isClose(Opponent) Table 1. The features that describe a BreakAway state.

We propose composed strings called "statechart DNA" as essential building blocks for a new statechart (sc) abstraction method. We define the simplified statechart (ssc) and show that our definition covers the UML 2.0 sc model, by matching it to all model elements of the StateMachine package of the UML 2.0 metamodel and to the OCL constraints on these model elements. A Model Driven Architecture (MDA) is defined, inspired by a PIM-to-PIM model transformation procedure between UML sc models and ssc models. We discuss the rationale behind action abstraction in ssc models. This framework is used to isolate sc DNA, first in ssc models, then in UML sc models. We show how sc DNA, a compaction of sc construction primitives, can be used to define behavior model metrics and more generally, to manage and maintain evolving object behavior. State machine versioning is an important application of statechart DNA to manage industrial model repositories.

Methods for specifying Moore type state machines (transducers) abstractly via primitive recursive functions and for defining parallel composition via simultaneous primitive recursion are discussed. The method is mostly of interest as a concise and convenient way of working with the complex state systems found in computer programming and engineering, but a short section indicates connections to algebraic automata theory and the theorem of Krohn and Rhodes.

We present a protocol for general state machine replication - a method that provides strong consistency - that has high performance in a wide-area network. In particular, our protocol Mencius has high throughput under high client load and low latency under low client load even under ...

The software architecture of a distributed system can be described as a hierarchical composition of subsystems, with interacting processes as the leaves of the hierarchy. Process behaviour can be specified using finite-state machines. A global state machine describing the overall system behaviour can be constructed using compositional reachability analysis techniques. These techniques compose the global state machine of a system from its component processes in stages, based on the specified hierarchy. This staged composition may however exacerbate the state explosion problem. A promising way to alleviate this problem is to include, in the analysis of each subsystem, the behaviour constraints imposed by its environment. Behaviour constraints can be derived algorithmically but may be too weak to adequately constrain the compositional analysis. In this paper, we describe a technique which enables software developers to also specify behaviour constraints intuitively. These constraints can be combined with those derived algorithmically. As constraints specified by software developers may be incorrect, the technique incorporates an effective mechanism to detect incorrect constraints and give an indication of how to correct them. Incorporation of the mechanism does not increase the complexity of analysis. The mechanism is supported by augmenting the state machine model with a special state π. The state is used to capture automatically potential errors in the constraints specified by software developers. The mechanism can also be utilised to detect violation of design assumptions. A gas station system is used as a case study in our discussion.