state machine

Nested words are a structured model of execution paths in procedural programs, reflecting their call and return nesting structure. Finite nested words also capture the structure of parse trees and other tree-structured data, such as XML. We provide new temporal logics for finite and infinite nested words, which are natural extensions of LTL, and prove that these logics are first-order expressively-complete. One of them is based on adding a "within" modality, evaluating a formula on a subword, to a logic CaRet previously studied in the context of verifying properties of recursive state machines (RSMs). The other logic, NWTL, is based on the notion of a summary path that uses both the linear and nesting structures. For NWTL we show that satisfiability is EXPTIME-complete, and that model-checking can be done in time polynomial in the size of the RSM model and exponential in the size of the NWTL formula (and is also EXPTIME-complete). Finally, we prove that first-order logic over nested words has the three-variable property, and we present a temporal logic for nested words which is complete for the two-variable fragment of first-order.

DQDB (distributed queue dual bus) is a media access control (MAC) protocol which is being standardized as an IEEE 802.6 MAN [ll]. The DQDB MAC protocol offers two types of services to its users: isochronous and asynchronous. This paper thoroughly analyzes the asynchronous part of the DQDB MAC protocol with only one priority class. According to our methodology, DQDB behavior is first analyzed in normal conditions (i.e., when the offered load is lower [underload] or slightly higher [overload] than the medium capacity), and then in asymptotic conditions (i.e., when each DQDB MAN node is trying to seize all the medium capacity). For each condition, performance and fairness metrics have been devised. The results obtained clearly show that DQDB is unfair when the bandwidth balancing mechanism (BWB) is disabled, and that the unfairness depends, in particular, upon the medium capacity and bus length. While this unfairness does not meaningfully degrade a node's quality of service in underload, it does cause unpredictable behavior in overload. When the BWB is enabled, DQDB behavior changes significantly. In asymptotic conditions, after a transient time, completely fair behavior is reached. In normal conditions, even though DQDB behavior still remains unfair, some major drawbacks are solved in the steady state (e.g., distribution of packet loss among the nodes). Our analysis is then broadened to include higher medium capacities up to 1.2 Gb/s. Finally, the extension of the methodology used in this paper to the analysis of the broad class of resource-sharing algorithms is sketched.

The software architecture of a distributed program can be represented by a hierarchical composition of subsystems, with interacting processes at the leaves of the hierarchy. Compositional reachability analysis (CRA) is a promising state reduction technique which can be automated and used in stages to derive the overall behaviour of a distributed program based on its architecture. CRA is particularly suitable for the analysis of programs which are subject to evolutionary change. When a program evolves, only the behaviours of those subsystems affected by the change need be re- evaluated. The technique however has a limitation. The properties available for analysis are constrained by the set of actions that remain globally observable. Properties involving actions encapsulated by subsystems may therefore not be analyzed. In this paper, we enhance the CRA technique to check safety properties which may contain actions that are not globally observable. To achieve this, the state machine mo...

Behaviour analysis should form an integral part of the software development process. This is particularly important in the design of concurrent and distributed systems, where complex interactions can cause unexpected and undesired system behaviour. We advocate the use of a compositional approach to analysis. The software architecture of a distributed program is represented by a hierarchical composition of subsystems, with interacting processes at the leaves of the hierarchy. Compositional reachability analysis (CRA) exploits the compositional hierarchy for incrementally constructing the overall behaviour of the system from that of its subsystems. In the Tracta CRA approach, both processes and properties reflecting system specifications are modelled as state machines. Property state machines are composed into the system and violations are detected on the global reachability graph obtained. The property checking mechanism has been specifically designed to deal with compositional techniques. Tracta is supported by an automated tool compatible with our environment for the development of distributed applications.

Since class objects are the major components in object-oriented (00) programs during run-time, testing the behavior of these objects become an important task in testing of object-oriented programs to comple ment other types of testing, such as, structuretesting and functional testing. To check the behavior of objects in 00 programs, it is essential to check each state and each transition for every object. This paper proposes a new test model, called object state diagram, to capture and represent the dynamic behavior of objects in an 00 program. The model is an extension of the existing state models, it supports basic 00 features, such as class objects, inheritance, aggregation and overloading. Unlike other models, it is a concurrent, communicating state machine which has the capability of representing the object state hierarchy for a complex class object. Based on this model we address the issues and solutions to object state test strategy, test criteria and test generation.

In this paper, the authors propose a mathematical model for a new topology called "stacked multicell converter" (SMC). Each phase of the SMC n × m multilevel inverter is formed by a stack of m flying-capacitor multilevel inverters, and each stack or stage is realized by connecting in series n controllable commutation cells. An original multicarrier subharmonic pulsewidth modulation (PWM), called disposition band carrier and phase-shifted carrier PWM (DBC-PSC-PWM), method is developed to produce (n × m + 1) output voltage levels and to improve the output voltage harmonic spectrum with a wide output frequency range. A diagram state machine is then used to decode the DBC-PSC-PWM modulator and distribute the commutations evenly to each inverter cell in a cyclical fashion. To carry out, in practice, the SMC n × m modulation technique, the implementation of the modulation control strategy has been done in a field-programmable gate array circuit XC4010E+ of XILINX to control a three-phase SMC 3 × 2 seven-level inverter, and the experimental results are carried out to confirm the high performance of this inverter.

Formal specification languages are often criticized for being difficult to understand, difficult to use, and unacceptable by software practitioners. Notations based on state machines, such as, Statecharts, Requirements State Machine Language (RSML), and SCR, are suitable for modeling of embedded systems and eliminate many of the main drawbacks of formal specification languages. Although a specification language can help eliminate accidental complexity, the inherent complexity of many of today's systems inevitably leads to large and complex specifications. Thus, there is a need for mechanisms to simplify a formal specification and present information to analysts and reviewers in digestible chunks. In this paper, we present a two tiered approach to slicing (or simplification) of hierarchical finite state machines. We allow an analyst to simplify a specification based on a scenario. The remaining behavior, called an interpretation of the specification, can then be sliced to extract the information effecting selected variables and transitions. To evaluate the effectiveness and utility of slicing in hierarchical state machines, we have implemented a prototype tool and applied our slicing approach to parts of a specification of a large avionics system called TCAS II (Traffic alert and Collision Avoidance System II).

Real-time 3D graphics are being extensively used to build interactive virtual environments for a number of different applications. In many situations, virtual objects are required to exhibit complex behaviors, and the use of a versatile behavioral programming methodology is required. This paper presents a feature modeling approach to define behavioral information of virtual objects, giving special attention to their capabilities of interaction with virtual human actors. The proposed method is based on a complete definition and representation of interactive objects, which are called smart objects. This representation is based on the description of interaction features: parts, movements, graspable sites, functionalities, purposes, etc, including a behavioral automata based on scripts and graphical state machines.

State machine based formalisms such as labelled transition systems (LTS) are generally assumed to be complete descriptions of system behaviour at some level of abstraction: if a labelled transition system cannot exhibit a certain sequence of actions, it is assumed that the system or component it models cannot or should not exhibit that sequence. This assumption is a valid one at the end of the modelling effort when reasoning about properties of the completed model. However, it is not a valid assumption when behaviour models are in the process of being developed. In this setting, the distinction between proscribed behaviour and behaviour that has not yet been defined is an important one. Knowing where the gaps are in a behaviour model permits the presentation of meaningful questions to stakeholders, which in turn can lead to model exploration and thus more comprehensive descriptions of the system behaviour. In this paper we propose using partial labelled transition systems (PLTS) to capture what remains to be defined of the system behaviour. In the context of scenario synthesis, we show that PLTSs can be used to support the iterative incremental elaboration of behaviour models.

State machines consume and process actions complementary to programs issuing actions. State machines maintain a state and reply with a boolean response to each action in their interface. As state machines offer a service to programs, their interface is also called a service interface. State machines can be combined with several natural operators, thus giving rise to a state machine calculus. State machines are used for abstract data type modeling.

Aspect-Oriented Programming languages allow pointcut descriptors to directly quantify over the implementation points of a system. Such pointcuts introduce strong mutual coupling between base modules and aspects and are problematic with respect to independent development. This paper introduces a new joinpoint selection mechanism based on state machine specifications. The interfaces of a system include a specification of the effects of method invocations on the state of the module instance. This specification is not defined with respect to potential aspects, but unambiguously describes the observable behavior of the module. We show how a smart joinpoint selection mechanism is able to infer points that might be located deep inside the implementation of a module, given pointcuts that are expressed entirely in terms of its specification elements. We present a tool, the Motorola WEAVR, which implements this technique in a Model-Driven Engineering environment.

The notion of intuitionistic fuzzy finite switchboard state machines and (strong) homomorphisms of intuitionistic fuzzy finite state machines are introduced, and related properties are investigated. After we give a congruence relation on the set of all words of elements of X of finite length, the quotient structure is discussed. We show that the family of equivalence classes is a finite semigroup with identity.

Early power analysis for systems-on-chip (SoC) is crucial for determining the appropriate packaging and cost. This early analysis commonly relies on evaluating power formulas for all cores for multiple configurations of voltage, frequency, technology and application parameters, which is a tedious and error-prone process. This work presents a methodology and algorithms for automating the power analysis of SoCs. Given the power state machines for individual cores, this work defines the product power state machine for the whole SoC and uses formal symbolic simulation algorithms for traversing and computing the minimum and maximum power dissipated by sets of power states in the SoC.

Since the source code of Android was released to the public, people have concerned about the security of the Android system. Whereas the insecurity of a system can be easily exaggerated even with few minor vulnerabilities, the security is not easily demonstrated. Formal methods have been favorably applied for the purpose of ensuring security in different contexts to attest whether the system meets the security goals or not by relying on mathematical proofs. In order to commence the security analysis of Android, we specify the permission mechanism for the system. We represent the system in terms of a state machine, elucidate the security needs, and show that the specified system is secure over the specified states and transitions. We expect that this work will provide the basis for assuring the security of the Android system. The specification and verification were carried out using the Coq proof assistant.

This paper proposes a revised semantic interpretation of UML Statechart Diagrams which ensures, under the specified design rules, that Statecharts may be constructed to have true compositional properties. In particular, hierarchical state machines may be properly encapsulated to allow independent verification and compositional testing, something which is not possible under the current UML semantics. Certain problems regarding the formal tractability of UML Satechart Diagrams are addressed, such as the confusion over states and connectors, the flattening effect of boundary-crossing transitions, and the consequences of inverting the inter-level priority rule for handling concurrent events. A set-theoretic formal treatment of object states, events, guards and run-tocompletion processing is given, describing both serial and concurrent Statecharts.

We present a real-time execution semantics for UML activity graphs that is intended for workflow modelling. The semantics is defined in terms of execution algorithms that define how components of a workflow system execute an activity graph. The semantics stays close to the semantics of UML state machines, but differs from it in some minor points. Our semantics deals with real time. The semantics provides a basis for verification of UML activity graphs, for example using model checking, and also for executing UML activity graphs using simulation tools. We illustrate an execution by means of a small example.

The readability of formal requirements specification languages is hypothesized as a limiting factor in the acceptance of formal methods by the industrial community. An empirical study was conducted to determine how various factors of state-based requirements specification language design affect readability using aerospace applications. Six factors were tested in all, including the representation of the overall state machine structure, the expression of triggering conditions, the use of macros, the use of internal broadcast events, the use of hierarchies, and transition perspective (going-to or coming-from). Subjects included computer scientists as well as aerospace engineers in an effort to determine whether background affects notational preferences. Because so little previous experimentation on this topic exists on which to build hypotheses, the study was designed as a preliminary exploration of what factors are most important with respect to readability. It can serve as a starting point for more thorough and carefully controlled experimentation in specification language readability.

Secure software engineering is a new research area that has been proposed to address security issues during the development of software systems. This new area of research advocates that security characteristics should be considered from the early stages of the software development life cycle and should not be added as another layer in the system on an ad-hoc basis after

The software architecture of a distributed system can be described as a hierarchical composition of subsystems, with interacting processes as the leaves of the hierarchy. Process behaviour can be specified using finite-state machines. A global state machine describing the overall system behaviour can be constructed using compositional reachability analysis techniques. These techniques compose the global state machine of a system from its component processes in stages, based on the specified hierarchy. This staged composition may however exacerbate the state explosion problem. A promising way to alleviate this problem is to include, in the analysis of each subsystem, the behaviour constraints imposed by its environment. Behaviour constraints can be derived algorithmically but may be too weak to adequately constrain the compositional analysis. In this paper, we describe a technique which enables software developers to also specify behaviour constraints intuitively. These constraints can be combined with those derived algorithmically. As constraints specified by software developers may be incorrect, the technique incorporates an effective mechanism to detect incorrect constraints and give an indication of how to correct them. Incorporation of the mechanism does not increase the complexity of analysis. The mechanism is supported by augmenting the state machine model with a special state π. The state is used to capture automatically potential errors in the constraints specified by software developers. The mechanism can also be utilised to detect violation of design assumptions. A gas station system is used as a case study in our discussion.

A. We consider a class of infinite-state stochastic games generated by stateless pushdown automata (or, equivalently, 1-exit recursive state machines), where the winning objective is specified by a regular set of target configurations and a qualitative probability constraint '>0' or '=1'. The goal of one player is to maximize the probability of reaching the target set so that the constraint is satisfied, while the other player aims at the opposite. We show that the winner in such games can be determined in NP ∩ co-NP. Further, we prove that the winning regions for both players are regular, and we design algorithms which compute the associated finite-state automata. Finally, we show that winning strategies can be synthesized effectively.

Verification of a test case for testing the conformance of protocol implementations against the formal description of the protocol involves verifying three aspects of the test case: expected input/output test behavior, test verdicts, and the test purpose. We model the safety and liveness properties of a test case using branching time temporal logic. There are four types of safety properties: transmission safety, reception safety, synchronization safety, and verdict safety. We model a test purpose as a liveness property and give a set of notations to formally specify a test purpose. All these properties expressed as temporal formulas are verified using model checking on an extended state machine graph representing the composed behavior of a test case and protocol specification. This methodology is shown to be effective in finding errors in manually developed conformance test suites.

We apply machine learning techniques to verify safety properties of finite state machines which communicate over unbounded FIFO channels. Instead of attempting to iteratively compute the reachable states, we use Angluin's L* algorithm to learn these states. The learnt set of reachable states is then used either to prove that the system is safe, or to produce a valid execution of the system that leads to an unsafe state (i.e. to produce a counterexample). Specifically, we assume that we are given a model of the system and we provide a novel procedure which answers both membership and equivalence queries for a representation of the reachable states. We define a new encoding scheme for representing reachable states and their witness execution; this enables the learning algorithm to analyze a larger class of FIFO systems automatically than a naive encoding would allow. We show the upper bounds on the running time and space for our method. We have implemented our approach in Java, and demonstrate its application to a few case studies.

This paper introduces an analysis and design of a digital controlled double loop voltage-current for a buck converter. Taking into account the implementation requirements, the chosen platform was an Field-Programmable Gate Array (FPGA). This paper also shows in detail the analog-digital interface. The study is completed by a detailed analysis of the FPGA programming including states machines and logic diagrams. Finally, theoretical results are validated with extensive simulations.

In this paper we present a genetic algorithm-based approach towards designing self-assembling objects comprised of square smart blocks. Each edge of each block can have one of three polarities (+1,-1 or 0) which defines how blocks stick togetheropposite charges attract, like charges repel, and a 0 face neither attracts nor repels. In addition to this property, the block contains an internal state machine which can change the polarity of any number of its sides following the detection of an "event". The aim of this work is to evolve block parameters which allow the self-assembly of desired basic structures that can be used as primitive building blocks for the assembly of more complicated objects. We detail a genetic algorithm-based approach towards evolving the state machine logic, with a fitness measure based on the difference of the final shape from some desired goal or target shape. The experimental results show that the genetic algorithms can find optimal rule sets and a number of stable building blocks can be generated using the evolved rule sets.

This paper focuses on verification and validation of a model dedicated to mode handling of flexible manufacturing systems (FMSs). This model is specified using the synchronous formalism safe state machines (SSMs). The rigorous semantics that characterize such formalism enable to provide formal verification mechanisms ensuring determinism and dependability. A structured framework for verification and validation of the model dedicated to mode handling is proposed. The main properties being verified within this framework and the corresponding verification methods are presented. The approach is illustrated using an example of a manufacturing production cell. The formal analysis tools integrated into the development environment Esterel Studio are used within the design process. ß

This paper presents a novel approach to synthesize low power FSMs using non-uniform code length Switching activity i s reduced by decreasrng the ezpected number of state bits switched less than [log lSl1. The state set S of the F S M 2s decomposed into two sets based on the ltmit state probabilitres. The state set with very hxgh probability is encoded with less than rlogISi1 bits. The other state set, being less probable. IS encoded usxng more than rloglSi1 bits. To the best of our knowledge, this i s the first time two code lengths are used for one state machine This encoding is realized by using Ptp-flops with gated clock The loyrc generating the enable signal of the clock uses only a srngle mrnterm. The state sets can be encoded using any uniform-length encodrng algorithm with objectives of low power and low area. The eiperrments show an average of 13% and 18% reduction rn power f o r two encoding algorithms respectively.

Objective: Many image-guided surgery applications require tracking devices as part of their core functionality. The Image-Guided Surgery Toolkit (IGSTK) was designed and developed to interface tracking devices with software applications incorporating medical images. Methods: IGSTK was designed as an open source C++ library that provides the basic components needed for fast prototyping and development of image-guided surgery applications. This library follows a component-based architecture with several components designed for specific sets of image-guided surgery functions. At the core of the toolkit is the tracker component that handles communication between a control computer and navigation device to gather pose measurements of surgical instruments present in the surgical scene. The representations of the tracked instruments are superimposed on anatomical images to provide visual feedback to the clinician during surgical procedures. Results: The initial version of the IGSTK toolkit has been released in the public domain and several trackers are supported. The toolkit and related information are available at www.igstk.org. Conclusion: With the increased popularity of minimally invasive procedures in health care, several tracking devices have been developed for medical applications. Designing and implementing high-quality and safe software to handle these different types of trackers in a common framework is a challenging task. It requires establishing key software design principles that emphasize abstraction, extensibility, reusability, faulttolerance, and portability. IGSTK is an open source library that satisfies these needs for the image-guided surgery community.

We propose a rule-based approach for transforming B abstract machines into UML diagrams. We believe that important insight into the structure underlying a B model can be gained by representing it in UML, for example in order to explain the model to stakeholders that are not experts in the B formalism. We focus on the generation of class diagram and state machines. Our approach does not prescribe a mechanic algorithm for translation, giving the modeler choices to adapt the resulting UML models as appropriate.

Hierarchical Communicating Real-Time State Machines (H-CRSM) is a formal modelling language for the modular development of distributed real-time systems. The formalism is characterized by the use of state transitions with guarded commands and timing constraints, the adoption of a few distilled statecharts constructs, and the modular specification of timing constraints along a state hierarchy. This paper proposes a translation of H-CRSM into UPPAAL which enables model checking. Translation rests on unfolding a hierarchical model on a flat representation. The resultant approach is demonstrated by means of a case study.

This paper addresses the problem of automatic generation of implementation software from high-level functional specifications in the context of embedded system on chip designs. Software design complexity for embedded systems has increased so much that a high-level functional programming paradigm need to be adopted for formal verifiability, maintainability and short time-to-market. We propose a framework for efficiently generating implementation software from a synchronous state machine specification for embedded control systems. The framework is generic enough to allow hardware/software partition for a given architecture platform. It is demonstrated that the logic optimization and simulation techniques can be combined to produce fast execution code for such embedded systems. Specifically, we propose a framework for software synthesis from multi-valued logic, including fast evaluation of logic functions, and scheduling techniques for node execution. Experiments are performed to show the initial results of our algorithms in this framework.

Esterel and Safe State Machines (SSMs) are synchronous languages dedicated to the modeling of embedded reactive systems. While Esterel is a textual language, SSMs are based on the graphical Statecharts formalism. Statecharts are often more intuitive to understand than their textual counterpart, and their animated simulation can help to visualize subtle behaviors of a program. However, in terms of editing speed, revision management, and meta-modeling, the textual nature of Esterel is advantageous. We present an approach to transform Esterel v5 programs into equivalent SSMs. This permits a design flow where the designer develops a system at the Esterel level, but uses a graphical browser and simulator to inspect and validate the system under development. We synthesize SSMs in two phases. The first phase transforms an Esterel program into an equivalent SSM, using a structural translation that results in correct, but typically not very compact SSMs. The second phase iteratively applies optimization rules that aim to reduce the number of states, transitions and hierarchy levels to enhance readability of the SSM. As it turned out, this optimization is also useful for the traditional, manual design of SSMs. The complete transformation has been implemented in a prototypical modeling environment, which allows to demonstrate the practicality of this approach and the compactness of the generated SSMs.

Web services among of the applications involving closely the customer's private information. In order to take into account the privacy concerns of the individuals, organizations (e.g Web services) provide privacy policies as promises describing how they will handle personal data of the individual. However, privacy policies do not convince potential individuals to disclose their personal data, do not guarantee the protection of personal information, and do not provide how to handle a possible evolution of the policies. In this paper, we introduce a framework based on an agreement as a solution to these problems. It contains a privacy model defined in the policy level of the agreement. The framework supports in the negotiation level of the agreement a lifecycle management which is an important deal of a dynamic environment that characterizes Web services. A negotiation protocol is proposed that enable ongoing privacy negotiation to be translated into a new privacy agreement.

The generation of actual sensory data in real-world deployments of pervasive spaces is very costly and requires significant preparation and access to human subjects. This situation can be mitigated if practical forms of sharing of existing datasets are enabled among the research community. In this paper we address two main problems. First, we propose a standard for the representation of smart space datasets, based on a careful examination of several existing data. The standard specification should allow researchers to effortlessly position their existing or future datasets for sharing. We briefly present the specifications. Second, to enable higher utility of shared datasets, we propose algorithms and tools that can extend a shared dataset into a similar set of a slightly customized pervasive space (e.g., an original space with additional sensors/actuators or behaviors). Specifically, we propose the use of machine learning algorithms to generate the additional patterns of events and to automatically integrate them into the original shared dataset.

This paper addresses the problem of monitoring the compliance of privacy agreement that spells out a consumer's privacy rights and how consumer private information must be handled by the service provider. A state machine based model is proposed to describe the Private Data Use Flow (PDUF) toward monitoring which can be used by privacy analyst to observe the flow and capture privacy vulnerabilities that may lead to non-compliance. The model is built on top of (i) properties and timed-related privacy requirements to be monitored that are specified using LTL (Linear Temporal logic) (ii) a set of identified privacy misuses.

Formal specijications can be hundreds ofpages in length -a reflection of the size and complexity of the systems being specijied. Lengthy documents are dificult to read, understand, and use. Program slicing was developed to address these issues for programs. In this paper, we apply similar techniques to formal specijications expressed as hierarchical state machines. We present a two tiered approach to slicing (or simplijication) of hierarchical state machines. We have applied our techniques to a large case study and present empirical data highlighting the reduction and simplijication capabilities of our approach to large spec$cations.

Requirements of the desired software product can be translated into state transition diagram or other UML diagrams. To verify the complete coverage of software requirements, the proposed Ant based approach generates non-repetitive transitions from the input state diagram. This approach has less redundant transitions and also gives uncovered transition in successive paths instead of giving whole redundant path again and again. The paper also contains a comparison between already existing approaches with respect to some parameters like coverage, redundancy, total number of transitions.

We describe experimental results to demonstrate the wide-ranging computational ability of quasiperiodic oscillators built from rings of differentiating Schmitt triggers. We describe a theoretical model based on necklace functions to compute the number of states supportable by a ring circuit of a given size. Experimental results are presented to demonstrate that probabilistic state machines can be built from these ring circuits. Other experimental results are given to demonstrate that the rings can model spiking neural network circuits.

NASA spends millions designing and building spacecraft for its missions. The dependence on software is growing as spacecraft become more complex. With the increasing dependence on software comes the risk that bugs can lead to the loss of a mission. At NASA's Jet Propulsion Laboratory new tools are being developed to address this problem. Logic model checking [9] and runtime verification [5] can increase the confidence in a design or an implementation. A barrier to the application of such property-based checks is the difficulty in mastering the requirements notations that are currently available. For these techniques to be easily usable, a simple but expressive requirement specification method is essential. This paper describes a requirements capture notation and supporting tool that graphically captures formal requirements and converts them into automata that can be used in model checking and for runtime verification.

Reproducing daily behaviours requires the ability to schedule behaviours depending on resources (body parts for example) and priority (intentions or physiological parameters) constraints. A simple way is to say that behaviours which are using the same resources are mutually exclusive. This approach is not sufficient to achieve realism purpose, as in real life, humans are able to combine them in a much microscopic way. All day long, humans mix different behaviours, as for example reading a newspaper while drinking a coffee and smoking a cigarette. If all behaviours using common resources were mutually exclusive, an agent could not reproduce this example, except if a specific behaviour is created. This solution becomes rapidly too complex and has motivated the work presented in this paper. It consists in an extension of HPTS, our behavioural model, by the introduction of resources and priority levels. In the contrary of some previous approaches, it is not necessary to specify exhausti...