Integrated Circuit Packaging

A novel low-cost packaging approach is presented in this paper, which is appropriate for high-frequency electronic circuits in discrete, as well as integrated, configurations. This approach is based on silicon micromachining and can effectively provide on-wafer and discrete packaging for high-quality highprecision miniature components. The required fabrication techniques are compatible with standard integrated-circuit processing and, for this reason, are low in fabrication costs. As an example, this paper presents the development of a Ka-band package that can shield and electromagnetically isolate monolithic-microwave integrated-circuit components, such as a phase shifter. The performance of this package is compared to that of a ceramic one and demonstrates excellent electrical response in addition to high design versatility.

Miniaturization reduces package size, cost and board space. System on Chip (SoC) integrates a system on a common silicon substrate, however there are some shortcomings with this approach such as high manufacturing cost. Handling of different levels of voltage and current on a common silicon substrate with controller IC operating in the range of several volts and milliamps, while power

Plastic electronic packages are known to absorb moisture when exposed to humid ambient conditions during storage in tape and reel in the factory. Reliability becomes a concern when packages are exposed to a humid environment for a prolonged time and then processed through a reflow oven. Thermo-mechanical and moisture induced interfacial stresses generated between the die attach and die may

A novel low-temperature Cu-Cu bonding approach called the insertion bonding technique has been developed. This technique hinges on the introduction of a tangential pressure at the metal-metal interface, which leads to a high localized plastic deformation that is essential for bond formation. Through finite element modeling studies, it is observed that the insertion bonding technique results in a significantly larger plastic deformation in comparison to the conventional bonding technique under the same bonding conditions. First experimental studies of the insertion bonding technique were performed and it is observed that an electrically yielding Cu-Cu joint is achieved at a low bonding temperature of 100°C. This shows that the insertion bonding technique holds much promise for low-temperature Cu-Cu bonding.

A variety of parameters impact package reliability. One set of parameters that does not get much attention is the variations in package design that are assembly and vendor related. This study shows that solder pad size is important in solder joint reliability. Differences in solder pad size due to different vendors and processes can affect the reliability considerably. The impact of substrate thickness on package reliability has been shown in finite element stress analysis, moiré interferometry experiments, and reliability tests. However, in certain cases, the pad size effect can be so significant that it overrides the impact of substrate thickness. This work indicates that in order to obtain good correlation between predictive engineering results and reliability tests data, this factor should not be ignored. In this study, finite element simulation has been used to quantify the pad size effect on the BGA reliability in the PBGA package. Air-to-air thermal cycling test results were compared with FEM predictions. Optimized pad sizes are discussed and the impact on the solder joint reliability is predicted. Solder pad size effect was found to be a dominant feature in correlating test data with predictions.

Laser drilling has emerged in the last five years as the most widely accepted method of creating microvias in high-density electronic interconnect and chip packaging devices. Most commercially available laser drilling tools are currently based on one of two laser types: far-IR CO2 lasers and UV solid-state lasers at 355 nm. While CO2 lasers are recognized for their high average power and drilling throughput, UV lasers are known for high-precision material removal and their ability to drill the smallest vias, with diameters down to about 25-30 m now achievable in production. This paper presents a historical overview of techniques for drilling microvias with UV solid-state lasers. Blind and through via formation by percussion drilling, trepanning, spiralling, and image projection with a shaped beam are discussed. Advantages and range of applicability of each technique are summarized. Drivers of throughput scaling over the last five years are outlined, and representative current-generation performance is presented.

Microwave model and high-frequency measurement of the anisotropically conductive film (ACF) flip-chip interconnection was investigated using a microwave network analysis. The test integrated circuits (IC's) were fabricated using a 1poly and 3-metal 0.6 m Si process with an inverted embedded microstrip structure. As flip chip bumps, electroless Ni/Au plating was performed on Al input/output (I/O) pads of test IC chips. And as an interconnect material, several ACF's were prepared and flip-chip bonded onto the Rogers® RO4003 high frequency organic substrate. S-parameters of on-chip and substrate were separately measured in the frequency range of 200 MHz to 20 GHz using a microwave network analyzer HP8510 and cascade probe, and the cascade transmission matrix conversion was performed. The same measurements and conversion were conducted on the test chip mounted substrates at the same frequency range. Then impedance values in flip-chip interconnection were extracted from cascade transmission matrix.

The area-I/O flip-chip package provides a high chip-density solution to the demand of more I/O's in VLSI designs; it can achieve smaller package size, shorter wirelength, and better signal and power integrity. In this paper, we introduce the routing problem for chip and package co-design and present the first work in the literature to handle the multiple Re-Distribution Layer (RDL) routing problem for flip-chip designs, considering pin and layer assignment, total wirelength minimization, and chip-package co-design. Our router adopts a two-stage technique of global routing followed by RDL routing. The global routing assigns each block port to a unique bump pad via an I/O pad and decides the RDL routing among I/O pads and bump pads. Based on the minimum-cost maximumflow algorithm, we can guarantee 100% RDL routing completion after the assignment and the optimal solution with the minimum wirelength. The RDL routing efficiently distributes the routing points between two adjacent bump pads and then generates a 100% routable sequence to complete the routing. Experimental results based on 10 industry designs demonstrate that our router can achieve 100% routability and the optimal routing wirelength under reasonable CPU times, while related works cannot.

A driving force to achieve increased speed and performance along with higher I/O count is the Flip Chip (FC) Technology which has therefore an high level of importance for a variety of applications. A breakthrough, however, will be the use of flip chip due to cost reduction. For this aim it is essential to use low cost bumping techniques.

This paper will discuss the IC packaging industry trends and how IC packaging is important and should to be considered in semiconductor companies for successful product design. IC packaging design flow and steps will be discussed on how it is done in the industry.

The development of Taiwan's integrated circuit (IC) industry is discussed in four sections covering the history of industry, the performance of the industry, the trends and development activities, and the future challenges. The latest data describing the industry are provided by Taiwan ERSO/ITRI ITIS project. The data cover the operations, marketing and technology indices, industry development goals, and investment trends that serve as a reference to regional developments in the IC industry. The paper also provides figures depicting the diversified supply system, the inter-relationship between investors, and the strategic alliances emerging in the Taiwan IC industry. has been in charged of ERSO/ITRI's survey research for the nation's semiconductor industry and is responsible for leading ERSO's strategic planning team. He is the Principal Investigator for the government funded project that publishes the Semiconductor Industry Yearbook. The yearbook is a primary source reference for industry that describes the current status of the industry and highlights trends in technology and competition.

The power consumption of microprocessors is increasing at an alarming rate leading to 2X reduction in the power distribution impedance for every product generation. In the last decade, high I/O ball grid array (BGA) packages have replaced quad flat pack (QFP) packages for lowering the inductance. Similarly, multilayered printed circuit boards loaded with decoupling capacitors are being used to meet the target impedance. With the trend toward system-on-package (SOP) architectures, the power distribution needs can only increase, further reducing the target impedance and increasing the isolation characteristics required. This paper provides an overview on the design of power distribution networks for digital and mixed-signal systems with emphasis on design tools, decoupling, measurements, and emerging technologies.

Mechanical properties of solder masks are critical in the reliability performance of flip-chip packages. Many recent studies show that the mechanical properties of solder mask materials have great influence on moisture absorption, delamination at interconnections and solder fatigue life in flipchip packages. There are also assembly process issues related to the properties of solder masks. In this article, an experimental investigation that mechanically characterizes solder one mask material is conducted. Mechanical properties such as Young's modulus, failure strength and creep behaviors are determined based on the measured data from the experiments. The testing temperature is set at two levels: 25OC and 8OOC. The major instrument is a sophisticated micro mechanical tester.

It has been a trend to convert gold wire to copper wire in manufacturing of semiconductor chip due to cost effectiveness. Another motivation for the conversion comes from the physical properties of copper wire. Copper wire offers the advantages of presenting higher mechanical strength, lower electrical resistance and slower intermetallic growth. Aside from the differences in term of chemical stability, copper is a stiffer material as compared to gold. It has been determined that copper wire requires new process optimization in comparison to gold wire. Parameter adjustments for ball bond formation, stitch bond formation, and looping profile are needed during conversion from gold to copper.

A variety of package parameters impact package reliability. One of the parameters that does not get much attention is the variations in package design that are assembly and vendor related. It was shown in this study that the solder pad size plays a big role in solder joint reliability. The difference in solder pad size due to different vendors and processes can affect the reliability considerably. In certain cases, the pad size effect can be so significant that it will override the effect of substrate thickness. Our work indicates that in order to obtain good correlations between predictive engineering results and reliability tests data, this factor should not be ignored. In this paper, finite element analysis was used to study the impact of substrate thickness on solder reliability for flip-chip PBGA (plastic ball grid array) packages. The simulation results were experimentally validated with moire interferometry. Both numerical and experimental results indicated that better solder reliability could be achieved by using thicker substrate. However, the size of BGA solder pad was found to be crucial to BGA life. In order to achieve higher C5 (controlled collapse chip carrier connection) reliability, a larger solder pad is preferred

The demand for die to package interconnects free of Pb in the next generation flip chip packages requires a flux and underfill solution that meets package reliability requirements. Bump cracks and bump deformation were observed during temperature cycling on large body, full Pb-free ceramic flip chip BGA packages during initial package development. The phenomenon is considered unique in terms of its nature and failure mechanism. Traditional bump crack issues are concentrated at or near the silicon and underfill interfaces. In this case, cracks occurred within the bulk solder away from either silicon or substrate interface. Failed bumps also showed severe deformation. In addition, morphology differences in the underfill material surrounding the affected bumps provided important clues as to the nature of the failure mechanism. An extensive investigation to understand the root cause of the unique bump crack issue in the bulk solder, which covered both process and material-related factors, resulted in a clear understanding of the failure mechanism and the implementation of an effective solution to the problem. This manuscript describes the relationship of the flux residueunderfill interaction, the localized change in underfill properties due to the flux residues, and eventually the impact of this change on the bump integrity during package stressing. These findings made it possible to establish a good fluxunderfill selection methodology to achieve a robust Pb-free package solution that is being implemented in next generation flip chip products. Figure 1: Traditional bump crack

This paper presents an overview of the current status of use of conductive adhesives in various electronics packaging applications. Strong emphasis is placed on recent developments in surface mount and flip-chip technology, as these methods in ...

3-D integrated circuits promise high bandwidth, low latency, low device power, and a small form factor. Increased device density and asymmetrical packaging, however, renders the design of 3-D power delivery a challenge. We investigate in this paper various methods to improve 3-D power delivery. We analyze the impact of through-silicon via (TSV) size and spacing, of controlled collapse chip connection (C4) spacing, and of dedicated power delivery TSVs. In addition to considering typical cylindrical or square metal-filled TSVs (core TSVs), we also investigate using coaxial TSVs for power delivery resulting in reduced routing blockages and added coupling capacitance. Our 3-D evaluation system is composed of a quad-core chip multiprocessor, a memory die, and an accelerator engine, and it is evaluated using representative SPEC benchmark traces. This is the first detailed architectural-level analysis for 3-D power delivery. Our findings provide clear guidelines for 3-D power delivery design. More importantly, we show that it is possible to achieve 2-D-like, or even better, power quality by increasing C4 granularity and by selecting suitable TSV size and spacing.

Over the glass transition temperature, molding compounds strongly exhibit viscoelastic behavior which causes their Young's moduli to be not only temperature-dependent but also time-dependent. In the present study, the stress relaxation test is used for the characterization of the viscoelasticity of an epoxy molding compound. The viscoelastic properties of the epoxy molding compound are determined in terms of Prony coefficients, relaxation time and time-temperature shift factors. Furthermore, the effect of viscoelasticity on the delamination in IC packaging is investigated.

With the continued demand for fine features, enhanced assembly yield, and improved reliability in the microelectronic packaging industry, there is a need to reduce substrate warpage. Factors such as coefficient of thermal expansion mismatch among several materials in the packaging substrate, modulus of different materials, thickness of different layers, orientation of features in each layer, thermal and mechanical loading conditions influence the substrate warpage, and any effort to reduce substrate warpage needs to address one or more of these factors. One technique to reduce warpage will be through the viscoelastic relaxation of the dielectric material, when other factors cannot be changed for performance, processing, or cost reasons. Thus, it is important to accurately model the viscoelastic relaxation of the dielectric material, and study how the warpage can be reduced either by changing dwell times at different temperatures and/or by introducing appropriate mechanical loads in combination with thermal loads. In this paper, we present two approaches to reduce substrate warpage: 1) by modifying the temperature-time profile of the sequential processing steps, and 2) by using an external mold to reduce the substrate warpage. Based on the simulation results, it appears that significant warpage reduction is achievable through the proposed techniques.

Increased use of sensors and controls in automotive applications has resulted in significant emphasis on the deployment of electronics directly mounted on the engine and transmission. Increased shock, vibration, and higher temperatures necessitate the fundamental understanding of damage mechanisms which will be active in these environments. Electronics typical of office benign environments use FR-4 printed circuit boards (PCBs). Automotive applications typically use high glass-transition temperature laminates such as FR4-06 glass/epoxy laminate material ( g = 164.9 C). In automotive underhood application environments, metal-backing of PCBs is being targeted for thermal dissipation, mechanical stability, and interconnections reliability.

The flip-chip package is introduced for modern integrated circuit (IC) designs with higher integration density and larger I/O counts. In this paper, we consider the pre-assignment flip-chip routing problem with predefined connections between driver pads and bump pads. This problem has been shown to be much more difficult than the free-assignment one, but is more popular in real-world designs because the connections between driver pads and bump pads are typically predetermined by IC or packaging designers. Based on the concept of routing sequence exchange, we propose a very efficient approach to guide the global routing by computing the longest common subsequence and the maximum planar subset of chords for pre-assignment flip-chips. We observe that the existing work over-constrains the capacity of a routing tile, which might miss some critical solution space with a better routing solution (e.g., smaller wirelength), and provide a remedy for this insufficiency to identify a better solution in a more complete solution space. We also develop a constant-time routability analyzer to check if a given set of wires can pass through a tile. Experimental results show that our router can achieve a 125× speedup with even better solution quality (same routability with slightly smaller wirelength), compared with a state-of-the-art flip-chip router based on integer linear programming.

Relative damage-index based on the leadfree interconnect transient strain history from digital image correlation, explicit finite-elements, cohesive-zone elements, and component's survivability envelope has been developed for life-prediction of two-leadfree electronic alloy systems. Life prediction of pristine and thermally-aged assemblies, have been investigated.

For critical high speed applications, system designers budget electrical performance for each individual component within the integration. During the budgeting process, each component is treated as a black box, and are assigned target performance levels. Crosstalk and switching noise levels are specified and closely watched, since they can cause episodes of false switching. SPICE simulations are performed at the IC, package, and system level to track down any signal integrity problems or issues. Obtaining accurate package models, in particular for power and ground, are key to overall simulation accuracy. Package power and ground inductance plays a major roll in determining switching noise performance. Ball Grid Array (BGA) packages are constructed with laminate substrates that provide an efficient means for achieving minimal power and ground inductance implementation. [2] A BGA that is strategically designed will yield m e r enhancements in crosstalk and switching noise performance[l]. This is accomplished by optimal implementation and location of power, ground, and signal networks. By doing so, loop inductance created at critical locations in the BGA are reduced by mutual inductance. BGA packages use power and ground rings to provide low inductance access from Integrated Circuit (IC) bond pads to package planes[3]. These connections are typically done using many bond wires equally distributed around the perimeter of the die. Rings are used in combination with via holes, planes, and solder balls to complete the power and ground network structures. Careful attention to how the currents flow in these structures in conjunction with signal traces will yield minimal effective inductance[4]. This paper presents a characterization methodology for creating BGA electrical models. It addresses a class of BGAs that contain power and ground planes, and the Plastic BGA package is used as a vehicle. The measurements are performed in frequency domain using a vector network analyzer. Using these models, electrical performance of BGA packages will be evaluated.

The contemporary, ever increasing power density electronics lead to more and more compact packaging for which thermal management becomes a key issue. Therefore using adequate, efficient heat removal solutions is a constant concern. Along this line, due to their advantages, there is a growing interest in utilizing solid state semiconductor devices to remove the heat and keep the electronic systems and equipment within controllable, thermally safe limits. This paper presents a mathematical model -based on the gradient (temperature, electric potential) to fluxes (heat flux and current density) relations and on the specific constitutive (material) laws -and its numerical, finite element (FEM) implementation to simulate the underlying, multiphysics processes in a TEC Peltier device. The study is aimed to provide a numerical simulation approach, of controllable accuracy, usable in the thermal design of integrated circuits in lieu of the order of magnitude analytical solutions to the heat transfer problem.

Optimization of a microelectronic system is a difficult task involving a number of different disciplines. Often, an optimization in one discipline will result in a sub-optimal solution in other areas and the overall system. This paper looks into the optimization of a ...

Abstmct-This paper presents a novel approach for the analysis of crosstalk, propagation delay, and pulse distortion of interconnects in high-speed integrated circuits, packages, and circuit hoards. First, based on the frequency-domain modal analysis, a set d formulas have been derived to describe the voltage and current transfer functions of coupled interconnects with arbitrary linear termination impedances. Next the transfer function is expanded to its Taylor series form. The inverse Fourier transform is then applied to the significant terms in the series. As a result, we have obtained analytiil expressioos of the timedomain waveforms for lossless multiconductor interconnection lines. I t has been found that the weak-coupling assumption, frequently assumed in previous works, is only marginally valid. In a typical interconnection con-ration, the secondary coupling of the disturbed line on the original signal line is substantial and must be taken into account for accurate prediction of the waveforms. Simulation results are given to illustrate the influence of the layout parameters of the interconnects and the rise or fall times of the source signal. In addition, it i s s h that ground conductors need to be placed on both sides of each of the signal lines to reduce crosstalk effectively. However, the presence of the ground conductors not only increases the layout complexity, but also, more importantly, results in more severe wavetam distortion for the signal on the active line.

Two mechanisms for autoclave failure of flip chip PBGA package have been identified : Transverse hygroscopic swelling of underfill has been found to be responsible for the first failure mechanism typified by randomised solder joint failure associated with localised underfill-chip delamination around the solder joints. The localised delamination may coalesce into a larger delamination near the centre of the chip. In-plane hygroscopic swelling of underfill and substrate is responsible for the second failure mechanism. It results in extensive underfill-chip delamination initiating from chip edge before solder joint failure.

We report here on the design, fabrication and high-speed performance of a novel parallel optical module with sixteen 10-Gb/s transmitter and receiver channels for a 160-Gb/s bidirectional aggregate data rate. The module utilizes a single-chip CMOS optical transceiver containing both transmitter and receiver circuits. 16-channel high-speed photodiode (PD) and VCSEL arrays are flip-chip attached to the low-power CMOS IC. The substrate emitting/illuminated VCSEL and PD arrays operate at 985 nm and include collimating lenses integrated into the backside of the substrate. The IC-OE assembly is then flip-chip attached to a high density organic package forming the transceiver optical module. The exclusive use of flip-chip packaging for both the IC-to-optoelectronic (OE) devices and for the IC-toorganic package minimizes the module footprint and associated packaging parasitics. The OE-on-IC assembly achieves a high area efficiency of 9.4 Gb/s/mm 2 [1]. The complete organic carrier transceiver package provides a lowcost, low-profile module similar to a conventional chip-carrier that can be directly surface mounted to a circuit board using a conventional BGA solder process. SLC transceiver modules with transmitter and receiver OE-IC arrays were assembled and characterized. Operation of all 16 transmitters in the transceiver module was demonstrated at data rates >10 Gb/s. Similarly, all 16 receiver channels operated error-free at >10 Gb/s. The receiver eye-diagrams were generated using a second transceiver source and therefore constitute a full transceiver optical link.

The design of power distribution networks (PDNs) on printed circuit board (PCB) structures, or even on interconnect structures inside IC packages, typically results, with or without decoupling capacitors added, in a network full of impedance resonances. These resonances functionally hamper fast digital and RF designs from several MHz up to the GHz-range onwards and are the root cause for many EMC issues. These resonances are caused both by the physical size and geometry of the PCB and the decoupling as well as the loading components added to that PCB. Utilizing the characteristic impedance of the adjacent supply and ground layers correctly, results in a resonant free supply PDN with an impedance which can be made very low over an extremely broad frequency range. This, in combination with ‘Kelvin contact’ decoupled ICs, assures that the low impedance of the PDN can be maintained and multiple decoupling capacitors are no longer needed near to the IC pins. This offers great advantages ...

In the field of flat panel displays, packaging technology has a significant influence on display performance. The electrical interconnect between the LCD and the LCD driver circuit is an area that needs improvement to achieve finer pitch, easier assembly and greater connection reliability. For LCD driver packaging, the ideal assembly process would possess the following characteristics: low processing cost; reliability

TRW is recognized as a world class leader in high reliability microelectronics packaging technologies for space applications. A controlled insertion of plastic encapsulated microcircuits (PEMs) is demonstrated and highlights how this technology can provide a superior integrated circuit (IC) packaging solution over traditional ceramic- based assemblies. Space qualified insertion of Plastic Ball Grid Array (PBGA) packages addressing high I/O packaging

To build reliable plastic packages, it's essential to achieve excellent adhesion at all internal interfaces. One common inhibitor to good interfacial adhesion in plastic packages is surface contamination, most commonly organic in nature, accumulated prior to molding and causing poor adhesion with the mold compound. The most vulnerable and important surface is the chip's topside passivation where organic contaminants are

Inkjet printing has been extensively used over the past 30 years in the graphic arts and packaging industries. This technology involves dispensing accurately positioned droplets of ink onto a substrate, which then solidifies through the evaporation of the constituent solvent, the cross-linking of a polymer or through crystallization. The mask-less, flexible, rapid and low cost nature of inkjet printing, combined with the development of a range of functional inks, has led to the adoption of this technology in system manufacturing. The SMART Microsystems research project underway at the Institute for Integrated Systems is investigating the use of this technique in the rapid customization of CMOS foundry wafers for More-than-Moore applications.

The Laser Restructuring Laboratory at the Center for Microelectronics Research (CMR), University of South Florida has pursued rapid prototyping technologies for electronic systems using novel laser restructuring techniques. Laser restructuring of electronic circuits offers great ...

Miniaturization reduces package size, cost and board space. System on Chip (SoC) integrates a system on a common silicon substrate, however there are some shortcomings with this approach such as high manufacturing cost. Handling of different levels of voltage and current on a common silicon substrate with controller IC operating in the range of several volts and milliamps, while power MosFETs at over hundreds of volts and more dozens of amps can also pose as an issue. Nevertheless, module packages having controller IC and power MosFET co-packaged are new. Fairchild semiconductor's advancement in packaging has eliminated these drawbacks with the introduction of Multi-flip chip on lead frame over-molded IC package [1]. This new package has a novel packaging concept that uses multi-flip chip technology on the power devices combined with controller IC employing wire bonding technique on one copper lead frame based substrate. The gate and source in power MosFETs are bumped and attached to the copper lead frame by flip chip bonding technology and are routed out of package by solder balls while the drain exposed at the bottom of the package is soldered directly to the board. This is a BGA package with exposed die back for drain. The paper describes the construction of multi-flip chip on lead frame over molded package in Fairchild semiconductor, its cost effective package designs and manufacturing challenges.

This talk describes a new hermetic optoelectronics package, the Si-Pak™ optical pod. This platform technology leverages conventional silicon optical bench (SiOB) into a compact, thermally-conductive, hermetic optoelectronics package. The package offers all the features of traditional SiOB, namely reliable RF performance, efficient optical coupling, small footprint, and passive alignment. However, this new platform adds a hermetic lid directly on the SiOB, complete with hermetic RF / DC and optical feedthroughs. Optical pods can be surface-or flex-mounted, and are ready for integration into a final receptacle or pigtailed package.

We highlight several fundamental challenges to designing highperformance integrated circuits in nanometer-scale technologies (i.e. drawn feature sizes < 100 nm). Dynamic power scaling trends lead to major packaging problems. To alleviate these concerns, thermal monitoring and feedback mechanisms can limit worst-case dissipation and reduce costs. Furthermore, a flexible multi-V dd + multi-V th + re-sizing approach is advocated to leverage the inherent properties of ultrasmall MOSFETs and limit both dynamic and static power. Alternative global signaling strategies such as differential and low-swing drivers are recommended in order to curb the power requirements of crosschip communication. Finally, potential power delivery challenges are addressed with respect to ITRS packaging predictions.

The flip-chip package is introduced for modern IC designs with higher integration density and larger I/O counts. In this paper, we consider the pre-assignment flip-chip routing problem with predefined connections between driver pads and bump pads. This problem has been shown to be much more difficult than the free-assignment one, but is more popular in real-world designs because the connections between driver pads and bump pads are typically pre-determined by IC or packaging designers. Based on the concept of routing sequence exchange, we propose a very efficient global routing algorithm by computing the weighted longest common subsequence (WLCS) and the maximum planar subset of chords (MPSC) for pre-assignment flip-chips. We observe that the existing work over constrains the capacity of a routing tile, which might miss some critical solution space with a better routing solution (e.g., smaller wirelength), and provide a remedy for this insufficiency to identify a better solution in a more complete solution space. We also develop a constant-time routability analyzer to check if a given set of wires can pass through a tile. Experimental results show that our router can achieve a 122× speedup with even better solution quality (same routability with slightly smaller wire-length), compared with a state-of-the-art flip-chip router based on integer linear programming (ILP).

The miniaturisation 3D integration/stacking systems has a significant impact on both thermal resistance and thermo-mechanical reliability. The trends regarding these issues are summarised for the different 3D integration approaches: 3D-SIP, 3D-WLP and 3D-SIC. 0 0.5 1 1.5 2 2.5 3 Smith 1.00E+17 5.00E+17 8.00E+18 P-Type Doping Concentration (cm¯³) Keep-Away-Zone (µm)

With the ongoing miniaturization and 3D integration trend in microelectronics packaging, a need exists to provide for denser chip interconnect than can be achieved with photolithography based processes. One way to achieve this is via a bumpless process using a S(ubmicron) W(ire) A(nisotropic) C(onductive) F(ilm) (SW-ACF) with a parallel array of submicron metal wires embedded in this film. This paper describes the first step of SW-ACF fabrication and bumped flip-chip bonding trials. The SW-ACF is based on a polycarbonate template filled with copper wires which is bonded onto a test chip with gold stud bumps. Electrical measurements showed that viable connections were made between the copper wires and the gold bond pads, and also that electrical insulation was maintained between bond pads. The concept worked for the smallest pad-pitch structure on the test chip which was 25 µm circular pads with 25 µm spacings.

As is known, undesired simultaneous switching noise produced by high-speed digital integrated circuits (ICs) and power vias may propagate along parallel-plane structures of multilayer printed circuit boards (PCBs) and IC packages, which act as parallel-plane cavity resonators. To minimize effects of the parallelplane cavities, we need to minimize the impedance profile of a PCB power bus in the frequency range of interest. We can minimize the impedance profile by reducing power bus plane spacings, and by using local and global decoupling techniques that employ decoupling capacitors. But, in the gigahertz-range, discrete capacitors are not efficient due to the parasitic inductance of their connections to the power bus. In this paper, in addition to the analysis of cavity-mode resonances in multilayered PCBs, we derived expressions for the impedance envelope that can be used for predicting the impedance profile of a power bus. This theoretical approach and the derived envelope expressions are confirmed analytically by the cavity-model method, by a full-wave field solver, and by laboratory measurements carried out by a network analyzer.

In this paper, we firstly present the equivalent circuit model of Anisotropic Conductive Film (ACF) flip-chip interconnect using Ni-filled ball and Au-coated polymer ball. The models were extracted up to the microwave frequency region over 10 GHz. The extrected model parameters of the Ni-filled ball interconnect are compared to those of the Au-coated polymer ball interconnect with respect to impedance and resonance frequency. The ACF using the Ni-filled ball can be manufactured with reduced manufacturing cost and simplified process, while it still has comparable electrical performance compared to that using the Au-coated polymer ball. So far, the Au-coated ball interconnect has been most widely used. Sparameter measurement and subsequent microwave network analysis were used for the extraction procedure of the impedance parameters.