Vlsi Design

of minimizing the expansion ratio is the same problem as minimizing "area efficiency", whereas our objective of minimizing the point expansion ratio is the same problem as minimizing "total edge length". However, here we pay no mind to issues of whether the layouts have a natural "downward" structure to them (customarily useful for visualizing a binary tree), or whether our layouts possess symmetries, or whether we pay a cost per "bend" since our edges need not be laid out as straight line segments. See for example concerning planar straight-line orthogonal grid drawings of binary trees, in which no such "bends" are allowed. Consequently, our layout results are more suitable from a VLSI point of view than from a visualization point of view.

Emerging applications in various fields, such as Ambient Intelligence scenarios or remote biomedical monitoring, currently demand wireless sensor networks with transceivers having extremely low power consumption requirements. This is a key issue in order to decrease battery weight and size and to increase the lifetime of the battery, which usually in these sensing nodes is not replaceable. To achieve these strict power requirements, several solutions have been proposed at various layers. At the physical layer, savings in power consumption are achieved by lowvoltage operation and optimized power-to-performance ratio. Supply voltages of 1V (or less) are anyway mandatory in modern deep submicron technologies to operate reliably due to the extremely thin oxide. Furthermore reduction of the supply voltage (even of not required) strongly reduces power consumption in digital circuits since it scales with supply voltage. Although this is not so simple in analog circuits, they should operate at the same supply voltage than the digital part in mixed-mode systems to avoid the complexity involved in generating various supply voltages.

Due to continuous advances in technology scaling, modern integrated circuits consist of billions of transistors. Interconnects between the gates in these transistors were
considered as ideal conductors that propagated signals
instantaneously. While device sizes were shrinking with each
technology generation, multilevel metal structures rose higher
and higher above the surface of the silicon and soon began to
dominate the landscape of the integrated circuit. In the sub
100nm scaling regime, interconnect behavior limits the
performance and correctness of VLSI systems. The wiring in
today’s integrated circuits forms a complex geometry that
introduces capacitive, resistive, and inductive parasitics. They
can cause an increase in propagation delay, impact on energy
dissipation and the power distribution and introduce extra noise sources, which affects the reliability of the circuit. As the device size scales down the impact of interconnect in the VLSI circuits became even more significant. The performance of copper interconnects tend to get reduced in the sub 100nm range and hence we need to examine for other interconnect via options. Single Wall Carbon Nanotubes exhibit better performance in sub 100nm processing technology due to their very large current carrying capacity and large electron mean free paths. Initially we have analyzed the performances of a copper based CMOS inverter for 32nm technology node. SPICE simulations were carried out to validate the results and the results show improved performance of CNT interconnects in terms of power and delay time in comparison to traditional copper based interconnects. This work suggests using Single Wall Carbon Nanotubes (SWCNT) as interconnects for global interconnects in VLSI design as they consume less energy and gives more throughput and bandwidth when compared with traditional Copper wires.

The aim of this paper is to study 4x4 Wallace tree multiplier. In high performance processing units & computing systems, multiplication of two binary numbers is primitive and most frequently used arithmetic operation. Wallace tree multiplier is area efficient & high speed multiplier. This paper presents design and verification of Wallace tree multiplier. Design is carried out in Xilinx ISE Design Suite 14.7 using Verilog HDL and verification is carried out in Questa Sim 10.4e using System Verilog HVL environment.