Behavioral Synthesis

High-level synthesis takes an abstract behavioral specification of a digital system and finds a register-transfer level structure that realizes the given behavior. In this tutorial we will examine the high-level synthesis task, showing how it can be decomposed into a number of distinct but not independenl. subtasks. Then we will present the techniques that have been developed for solving those subtasks. Finally, we will note those areas related to high-level synthesis that are still open problems.

Molecules that exhibit magnetic bistability, commonly referred to as single-molecule magnets (SMMs), are of high interest because of their unusual physical properties and potential applications in quantum computing. [1] In contrast to traditional magnets, which are characterized by the bulk ordering of spins within a 3D solid, SMM behavior arises from the intrinsic magnetic properties of the individual molecules. The signature of an SMM is a slow paramagnetic relaxation of the magnetization evidenced by a frequency-dependent outof-phase (c 00 m ) ac susceptibility signal and hysteretic behavior. The presence of an appreciable thermal barrier for reversing the magnetization is related to the combination of a large total spin ground state (S) and negative uniaxial anisotropy (D). The existence of the phenomenon of single-molecule magnetism was first noted a decade ago in the compound [Mn 12 O 12 (O 2 CCH 3 ) 16 (OH 2 ) 4 ], which displays a ground state of S = 10. [2] Since this discovery, a number of oxo-bridged clusters containing V, Mn, [4][6] Fe, Co, and Ni have also been shown to display SMM behavior. In all cases, the molecules that have longer paramagnetic relaxation times have values of S > 3 or higher and a negative D value.

Most existing behavioral synthesis systems put emphasis on optimizing area and performance. Only recently has some research been done to consider testability during behavioral synthesis. In our previous work, we integrated hierarchical testability with behavioral synthesis of simple digital data path circuits to synthesize highly testable circuits (S. Bhatia and N.K. Jha, 1994). In the current work, we consider the testability of complete controller and data path during behavioral synthesis. The methods presented can easily handle large and complex behavioral descriptions with loops, conditionals, and allow different scheduling constructs, such as pipelining, multicycling, and chaining. The test set for the combined controller/data path is generated during synthesis in a very short time and near 100% fault coverage is obtained for almost all the synthesized circuits at practically zero overheads

We present a framework for high-level synthesis that enables the designer to explore the best choice of source level and low level parallelizing transformations for improved synthesis. Within this framework, we have implemented a methodology that applies a set of parallelizing code transformations, both at the source level and during scheduling. Using these transformations, the designer can optimize high-level synthesis results and reduce the impact of control flow constructs on the quality of results. In our methodology, we first apply a set of source level pre-synthesis transformations that include common sub-expression elimination (CSE), copy propagation, dead code elimination and loop-invariant code motion, along with more coarse level code restructuring transformations such as loop unrolling. We then explore scheduling techniques that use a set of aggressive speculative code motions to maximally parallelize the design by re-ordering, speculating and sometimes even duplicating operations in the design. In particular, we present a new technique called "Dynamic CSE" that dynamically coordinates CSE and code motions such as speculation and conditional speculation during scheduling. We also show how operation chaining across conditional boundaries can be used to optimize control flow. We have built the Spark high-level synthesis framework that takes a behavioral description in ANSI-C as input and generates synthesizable register-transfer level VHDL. Our results from three moderately complex design targets, namely, MPEG-1, MPEG-2 and the GIMP image processing tool validate the utility of our approach to the behavioral synthesis of designs with complex control flows.

This paper presents a resource-constrained scheduling scheme and a latency-constrained scheduling scheme that minimize power consumption for the case when the resources operate at multiple voltages. The resource-constrained scheduling reduces the power consumption by maximally utilizing resources operating at reduced voltages and, at the same time, reducing the latency. The latency-constrained scheduling scheme reduces the power consumption by assigning as many nodes (of the data flow graph) as possible to the resources operating at reduced voltages. Both schemes consider the effect of switching activity on the power consumption of the functional units. In addition, both schemes use heuristics to reduce the power consumed by the level shifters. Experiments with HLS benchmark examples show that the proposed schemes achieve significant power reduction when the operating voltages are 5 and 3.3 V or 5, 3.3, and 2.4 V.

SystemCoDesigner is an ESL tool developed at the University of Erlangen-Nuremberg, Germany. SystemCoDesigner offers a fast design space exploration and rapid prototyping of behavioral Sys-temC models. Together with Forte Design Systems, a fully automated approach was developed by integrating behavioral synthesis into the design flow. Starting from a behavioral SystemC model, hardware accelerators can be generated automatically using Forte Cynthesizer and can be added to the design space. The resulting design space is explored automatically by optimizing several objectives simultaneously using state of the art multi-objective optimization algorithms. As a result, SystemCoDesigner presents optimized hardware/software solutions to the designer who can select any of them for rapid prototyping on an FPGA basis. Thus, Sys-temCoDesigner bridges the gap from ESL to RTL and increases the confidence in early design decisions.

In this work we study the problem of estimating the power dissipation of the atomic components (macros) used to implement basic operations in behavioral synthesis. We first precisely define the key requisites for behavioral power macro-models and we briefly evaluate the suitability of several approaches proposed in the past. We then focus on a specific macro-modeling methodology that appears to

In this paper, we present a comprehensive highlevel synthesis system that is geared toward reducing power consumption in control-flow intensive as well as data-dominated circuits. An iterative improvement framework allows the system to search the design space by examining the interaction between the different high-level synthesis tasks. In addition to incorporating traditional high-level synthesis tasks such as scheduling, module selection, and resource sharing, we introduce a new optimization that performs power-conscious structuring of multiplexer networks, which are predominant in control-flow intensive circuits. The scheduler employed is capable of loop optimizations within and across loop boundaries. We also introduce a fast power estimation technique, based on switching activity matrices, to drive the synthesis process.

Melatonin (MLT) is a hormone produced in the brain by the pineal gland, from the amino acid tryptophan. It is also an antioxidant hormone with a particular role in the protection of nuclear and mitochondrial DNA. In recent years, many physiological properties of MLT have been described resulting in much attention in the development of synthetic compounds possessing the indole ring. Sixteen MLT analogue indole hydrazide/hydrazone derivatives were synthesized and in vitro antioxidant activity was investigated. Most of the compounds showed significantly higher activity than MLT at 10 23 M and 10 24 M concentrations.

With the rapid increase of complexity in Systemon-a-Chip (SoC) design, the electronic design automation (EDA) community is moving from RTL (Register Transfer Level) synthesis to behavioral-level and system-level synthesis. The needs of system-level verification and software/hardware codesign also prefer behavior-level executable specifications, such as C or SystemC. In this paper we present the platform-based synthesis system, named xPilot, being developed at UCLA. The first objective of xPilot is to provide novel behavioral synthesis capability for automatically generating efficient RTL code from a C or SystemC description for a given system platform and optimizing the logic, interconnects, performance, and power simultaneously. The second objective of xPilot is to provide a platform-based system-level synthesis capability, including both synthesis for application-specific configurable processors and heterogeneous multi-core systems. Preliminary experiments on FPGAs demonstrate the efficacy of our approach on a wide range of applications and its value in exploring various design tradeoffs.

The use of radio frequency identification (RFID) technology is expanding rapidly in numerous applications such as logistics, supply chain management, transportation, healthcare and aviation. Due to the variety of the current applications, typical RFID systems use application specific hardware and proprietary protocols. These systems generally have long design times, no tolerance to changes in application or standard, and hence very high system costs.

Many modern multimedia applications such as image and video processing are characterized by a unique combination of arithmetic and computational features: fixed-point arithmetic, a variety of short data types, high degree of instruction-level parallelism, strict timing constraints, and high computational requirements. Computationally intensive algorithms usually boost device's power dissipation which is often key to the efficiency of many communications and multimedia applications. Although recently virtually all general-purpose processors have been equipped with multiprecision operations, the current generation of behavioral synthesis tools for application-specific systems does not utilize this power/performance optimization paradigm. In this paper, we explore the potential of using multiple precision arithmetic units to effectively support synthesis of low-power application-specific integrated circuits. We propose a new architectural scheme for collaborate addition of sets of variable precision data. We have developed a novel resource allocation and computation assignment methodology for a set of multiple precision arithmetic units. The optimization algorithms explore the trade-off of allocating low-width bus structures and executing multiple-cycle operations. Experimental results indicate strong advantages of the proposed approach.

Having to cope with the continuously increasing complexity of modern digital systems, hardware designers are considering more and more seriously language based methodologies for parts of their designs. Last year, the introduction of a new language for hardware descriptions, the SystemC C++ class library, initiated a closer relationship between software and hardware descriptions and development tools. This paper presents a synthesis environment and the corresponding synthesis methodology, based on traditional compiler generation techniques, which incorporate SystemC, VHDL and Verilog to transform existing algorithmic software models into hardware system implementations. Following this approach, reusability of software components is introduced in the hardware world and timeto-market is decreased, as shown by experimental results.

For a nanoCMOS of sub-65nm technology, where the gate oxide (SiO 2 ) thickness is very low, the gate leakage is one of the major components of power dissipation. In this paper, we provide analytical models to describe the tunneling current and propagation delay of behavioral level components considering various physical effects in the absence of foundry data. Subsequently, we explore the use of multiple oxide thickness resources as a technique for the reduction of gate leakage. In particular, we introduce a behavioral datapath scheduler that maximizes the utilization of higher gate oxide thickness resources. We characterize behavioral components for both 65nm and 45nm technologies in order to study the trend of tunneling current as technology scales, and provide them as inputs to the scheduler. We carried out extensive experiments for several benchmarks and observed significant reduction in gate leakage.

Early performance feedback and design space exploration of complete FPGA designs are still time consuming tasks. We propose an original methodology based on estimations to reduce the impact on design time. We promote a hierarchical exploration to mitigate the complexity of the exploration process. Therefore this work takes place before any design step, such as compilation or behavioral synthesis, where the specification is still provided as a C program. The goal is to provide early area and delay evaluations of many RTL implementations to prune the design space. Two main steps compose the flow: (1) a structural exploration step defines several RTL implementations, and (2) a physical mapping estimation step computes the mapping characteristics of these onto a given FPGA device. For the structural exploration, a simple yet realistic RTL model reduces the complexity and permits a fast definition of solutions. At this stage, we focus on the computation parallelism and memory bandwidth. Advanced optimizations using for instance loop tiling, scalar replacement or data layout are not considered. For the physical estimations, an analytical approach is used to provide fast and accurate area / delay trade-offs. We do not consider the impact of routing on critical paths or other optimizations. The reduction of the complexity allows the evaluation of key design alternatives, namely target device and parallelism that can also include the effect of resource allocation, bitwidth or clock period. Due to this, a designer can quickly identify a reliable subset of solutions for which further refinement can be applied to enhance the relevance of the final architecture and reach a better use of FPGA resources, i.e. an optimal level of performance. Experiments performed with Xilinx (VirtexE) and Altera (Apex20K) FPGAs for a 2D Discrete Wavelet Transform and a G722 speech coder lead to an average error of 10% for temporal values and 18% for area estimations.

Heuristics are widely used for solving computational intractable synthesis problems. However, until now, there has been limited effort to systematically develop heuristics that can be applied to a variety of synthesis tasks. We focus on development of general optimization principles so that they can be applied to a wide range of synthesis problems. In particular, we propose a new way to realize the most constraining principle where at each step we gradually relax the constraints on the most constrained elements of the solution. This basic optimization mechanism is augmented with several new heuristic principles: minimal freedom reduction, negative thinking, calibration, simultaneous step consideration, and probabilistic modeling.

Deploying multiple supply voltages (multi-Vdds) on one chip is an important technique to reduce dynamic power consumption. In this work we present an optimality study for resource binding targeting designs with multi-Vdds. This is similar to the voltage-island design concept, except that the granularity of our voltage island is on the functional-unit level as opposed to the core level. We are interested in achieving the maximum number of low-Vdd operations and, in the same time, minimizing switching activity during functional unit binding. To the best of our knowledge, there is no known optimal solution to this problem. To compute an optimal solution for this problem and examine the quality gap between our solution and previous heuristic solutions, we formulate this problem as a min-cost network flow problem, but with special equal-flow constraints. This formulation leads to an easy reduction to the integer linear programming (ILP) solution and also enables efficient approximate solution by Lagrangian relaxation. Experimental results show that the optimal solution computed based on our formulation provides 7% more low-Vdd operations and also reduces the total switching activity by 20% compared to one of the best known heuristic algorithms that consider multi-Vdd assignments only.

The SAVANT, QUEST II, and HEPE research programs at the University of Cincinnati include the development and distribution of VHDL analysis and simulation capabilities. These capabilities are being freely distributed for non-commercial use. The SAVANT project is underway specifically to develop a VHDL analyzer with a welldocumented, extensible intermediate form; the main objective is to smooth the integration of VHDL technology into university and industrial research programs. The SAVANT project is funded through the Air Force SBIR program and is a joint activity between the University of Cincinnati and MTL Systems, Inc.

Chip architectures considered so far range from regular to fully customized topologies for application-specific designs requiring high-level bandwidth. To this end, a networkcentric design flow is necessary to support the design space exploration of complex SoCs with tight design constraints. This paper introduces four different approaches based on the orthogonalization of core mapping and topology customization applied to STNoC, the Network on-Chip developed by STMicroelecronics. The four methods are derived from the combination of the initial mappings to two standard topologies (ring and spidergon) with two types of topology customization based on the insertion of cross-links to reduce the network distance of standard topologies.

Most digital systems at some time during use have areas (modules) that are "dead" in the sense that they do not contain valid data, i.e., the data that was processed or generated by that area has been passed on to a subsequent stage and will not be required (read) again. In a synthesized system, where the flow of data is determined explicitly by an on-chip (synthesized) controller, the question of which arras will be dead or not (and when) is known in advance. There are areas and times when the "use" is data-dependent, but then the use is known to the controller at that time. This deadtime can be exploited to run a test pattern (either complete or in part) through the unused area, thereby giving the ability to continuously monitor the "health" of the overall system with very little (sometimes zero) impact on the processing capability. This has obvious applications in situations where reliability is a concern. There exist systems where an area is so heavily used that it is impossible to perform any testing at a serious rate; in this case the area may either be partially tested (or tested at a lower rate) or the processing of "real" data periodically halted to allow a more thorough test to take place with concomitant throughput degradation. This paper describes a behavioral synthesis system that can detect and exploit dead areas for automatic testing. Pertinent aspects of the controller are described, and a number of dead area statistics (including "test throughput") generated from real designs are reported.

Although behavior modeling should play a central role in model-driven application development, it is still unclear how behavior modeling should be incorporated in model transformations. This paper presents an MDA-based approach that incorporates behavior modeling at the Platform-Independent Model (PIM) level of the design process of a specific category of applications, i.e., context-aware mobile applications. This approach includes two model transformations. The first transformation is a refinement of the (external) observable application behavior into a (internal) structured behavior based on a reference architecture. The second transformation is the synthesis of this structured behavior into the behavior of individual architecture components. This paper focuses on the second transformation and targets the behavior of a coordinator component that orchestrates the interactions between all the other components. We propose a state machines-based approach that can be used for synthesizing the coordinator component behavior in order to cope with synchronization and concurrency issues.

This paper addresses the problem of true delay estimation during high level design. The existing delay estimation techniques either estimate the topological delay of the circuit which may be pessimistic, or use gate-level timing analysis for calculating the true delay, which may be prohibitively expensive.

We present minimization methodologies and an algorithm for simultaneous scheduling, binding, and allocation for the reduction of total power and power fluctuation during behavioral synthesis. We consider resources of dual gate oxide thicknesses, dual threshold voltage, and dual power supply. Statistical variations in these parameters are explicitly taken into account by using Monte Carlo simulations to characterize a datapath component library which is then used during behavioral synthesis. The formulated multi-objective cost function is optimized for various resource and time constraints. We present results on several standard benchmarks where we observed significant reduction in total power (as high as 75% without time penalty) and elimination of total power fluctuation (as high as 76% without time penalty). To the best of the authors' knowledge, this is the first-ever behavioral synthesis work addressing fluctuation in total power consumption accounting for gate and subthreshold leakage and dynamic power.

Due to exponential behavior of gate-oxide leakage current with temperature and technology scaling, leakage power plays important role in nano − CM OS circuit. In this paper, we present simultaneous scheduling and binding algorithm for optimizing leakage current during behavioral synthesis. It uses T ED (Taylor Expansion Diagram) for generating optimized DF G (Data Flow Graph). Once DF G is obtained, it selectively binds non-critical components to corresponding functional unit consisting of transistors of high oxide thickness and critical components with low oxide thickness. As the algorithm considers time-constraint explicitly, it reduces leakage current without degrading the performance of the design. Experimental results on a set of behavioral synthesis benchmarks for 45nm process show 30% to 70% reduction in leakage current compared to the results obtained by a conventional optimization flow.

This article presents methods to translate a behavioral-level analog description into a Field Programmable Analog Array (FPAA) implementation. The methods consist of several steps that are referred to as function decomposition, macrocell synthesis, placement and routing, and postplacement simulation. The focus of this article is on the first three steps. The function decomposition step deals with decomposing a high-order system function into a set of lower-order functions. We present an efficient procedure for searching for an optimal solution. This procedure is based on first formally demonstrating the equivalence of two previously used optimization criteria. The objective of the macrocell synthesis step is to generate a hardware realization. A modified signal flow graph is introduced to represent FPAA circuits and graph transformations are used to identify the realizations that comply with the FPAA hardware constraints. The modified signal flow graph also allows scaling of capacit...

high-level specifications during behavioral synthesis. Typically, the critical path of a synthesised behavioral design goes through both the datapath and the control logic; yet 7NextState most scheduling algorithms account only for datapath and , and output logic ignore control delay, leading to timing uncertainties in the Conlrol resulting designs. We present an estimation technique for Signals computing a fast, robust, scalable, and reasonably accurate approximation of the control delay from behavioral specifi-Status Signals Re El cations. The delay estimate is formulated in terms of the properties of the input specification and other inputs to the synthesis process such as resource constraints. Categories and Subject Descriptors Figure 1: Output of Behavioral Synthesis B.5.2 [Register-Transfer-Level Implementation]: Design Aids-Automatic synthesis this generated circuit, the critical path usually begins at the state register outputs, and passes through the control logic, General Terms followed by datapath elements, and terminates at datapath registers. Thus, for correct operation of the circuit, the clock Performance, Experimentation period needs to be wide enough to accommodate all these cumulative delays along with the setup and hold times of the Keywords registers. Since the scheduling step determines the mapping High Level Synthesis, FSM, Control Delay, Estimation of datapath operations to clock cycles, and takes important timing-related decisions such as chaining of operations de

As a result of aggressive technology scaling, gate leakage (gate oxide direct tunneling) has become a major component of total power dissipation. Use of dielectrics of higher permittivity (Dual-K) or use of silicon dioxide of higher thicknesses (Dual-T ) are being considered as methods for its reduction. This paper presents a comparative view of dual dielectric and dual thickness low leakage design techniques from a behavioral synthesis perspective. An algorithm is presented for the gate leakage current reduction that does simultaneous scheduling, allocation and binding during behavioral synthesis while accounting for process variations. The algorithm minimizes the gate leakage for given time constraints. We performed experiments for a number of benchmark circuits using a 45nm CMOS technology datapath library. We obtained gate leakage reduction as high as 95% for the dual-K (SiO 2 and Si 3 N 4 ) and 91% for the dual-T (1.4nm and 1.7nm) approaches. It is observed that the dual-K approach outperformed the dual-T approach for all benchmark circuits.

When synthesizing control-ow dominated descriptions based on VHDL, dierent styles of semantically equivalent descriptions may dier signicantly in quality. This paper discusses the eect of the input description on High-Level Synthesis when using VHDL. In order to show this eect, a high speed p r otocol based o n the ISO reference p r otocol Abracadabra is used. Five VHDL descriptions styles of the same protocol have been synthesized using AMICAL, a VHDL based b ehavioral synthesis tool. Discussions of the dierent results leads to a VHDL based methodology for protocol modelling in order to produce ecient designs.

In this paper, we introduce a simple procedure to predict wiring delay in bi-directional buses and a way of properly sizing the driver for each of its port. In addition, we propose a simple calibration procedure to improve its delay prediction over the Elmore delay of the RC tree. The technique is fast, accurate, and ideal for implementation in floorplanner during behavioral synthesis.

VHDGbased behavioral synthesis is appearing on the market but it still has to prove that it can have a significant impact. In the past, most applications for behavioral synthesis came from the DSP area and from the academic world. In contrast, this paper describes the results of an investigation and evaluation of several behavioral synthesis tools, carried out on recent designs of Alcatel-Bell, leading to a more detailed study of relevant industrial telecom non-DSP circuits, that were suitable for behavioral synthesis.

For CMOS technologies below 65nm, gate oxide direct tunneling current is a major component of the total power dissipation. This paper presents a simulated annealing based algorithm for the gate leakage current reduction by simultaneous scheduling, allocation and binding during behavioral synthesis. Gate leakage current reduction is based on the use of functional units of different oxide thickness while simultaneously accounting for process variations. We present a cost function that minimizes leakage and area overhead. The algorithm minimizes the cost function for a given delay trade-off factor. It uses a pre-characterized cell library for tunneling current, delay and area, expressed as analytical functions of the gate oxide thickness T ox . We tested our approach using a number of behavioral level benchmark circuits characterized for a 45nm library by integrating our algorithm into a high-level synthesis system. We obtained an average gate leakage reduction of 76.88% with an average area overhead of 17.38% for different delay trade-off factors ranging from 1.0 to 1.4.

In addition to high performance requirements, future generation mobile telecommunications brings new constraints to the semiconductor design world. In order to associate the flexibility to the highperformances and the low-energy consumption needed by this application domain we have developed a functional level dynamically reconfigurable architecture, DART. Even if this architecture supports the processing complexity of the UMTS while allowing the portability of the devices and their evolutions, another challenge is to develop efficient high-level design tools. In this paper, we discuss about a methodology allowing the definition of such development tool based on the joint used of compilation and behavioral synthesis schemes.

SystemC is a widely used electronic system-level (ESL) design language that can be used to model both hardware and software at different stages of system design. There has been a lot of research on behavior synthesis of hardware from SystemC, but relatively little work on synthesizing embedded software for SystemC designs. In this letter, we present an approach to automatic software synthesis from SystemC-based on coroutines instead of the traditional approaches based on real-time operating system (RTOS) threads. Performance evaluation results on some realistic applications show that our approach results in impressive reduction of runtime overheads compared to the thread-based approaches.

We introduce a new approach to take into account the memory architecture and the memory mapping in the Behavioral Synthesis of Real-Time VLSI circuits. We formalize the memory mapping as a set of constraints for the synthesis, and defined a Memory Constraint Graph and an accessibility criterion to be used in the scheduling step. We use a memory mapping file to include those memory constraints in our HLS tool GAUT. Our scheduling algorithm exhibits a relatively low complexity that permits to tackle complex designs in a reasonable time. Several experiments are performed to demonstrate the efficiency of our method, and to compare GAUT with an industrial behavioral synthesis tool. We finally show how to explore, with the help of GAUT, a wide range of solutions, and to reach a good tradeoff between time, power-consumption, and area.

In this paper, we introduce a simple procedure to predict wiring delay in bi-directional buses and a way of properly sizing the driver for each of its port. In addition, we pr opose a simple calibration procedure to improve its delay prediction over the Elmore delay of the RC tree. The technique is fast, accurate, and ideal for implementation,in

We introduce a new approach to take into account the memory architecture and the memory mapping in the High- Level Synthesis of Real-Time embedded systems. We formalize the memory mapping as a set of constraints for the synthesis, and defined a Memory Constraint Graph and an accessibility criterion to be used in the scheduling step. We use a memory mapping

We introduce a new approach to take into account the memory architecture and the memory mapping in behavioral synthesis. We present a new strategy for implementing signals (ageing vectors). We formalize the maturing process and explain how it may generate memory conflicts over several iterations of the algorithm. The final Compatibility Graph indicates the set of valid mappings for every signal. Several experiments are performed with our HLS tool GAUT. Our strategy exhibits a relatively low complexity memory architecture for ageing vectors that permits to tackle complex designs for data intensive applications. I. I NTRODUCTION