Behavioral Synthesis

For a nanoCMOS of sub-65nm technology, where the gate oxide (SiO 2 ) thickness is very low, the gate leakage is one of the major components of power dissipation. In this paper, we provide analytical models to describe the tunneling current and propagation delay of behavioral level components considering various physical effects in the absence of foundry data. Subsequently, we explore the use of multiple oxide thickness resources as a technique for the reduction of gate leakage. In particular, we introduce a behavioral datapath scheduler that maximizes the utilization of higher gate oxide thickness resources. We characterize behavioral components for both 65nm and 45nm technologies in order to study the trend of tunneling current as technology scales, and provide them as inputs to the scheduler. We carried out extensive experiments for several benchmarks and observed significant reduction in gate leakage.

Among the many directions of IT, the most pervasive is the fusion of information processing with physical processes-called embedded computing. It is the basic engine of innovation and source of competitiveness for broad range of industrial sectors from automotive to telecommunications and from aerospace to manufacturing. Embedded computing transforms products, creates new markets and disrupts the status quo. Embedded computing is rapidly taking over the role of being the universal system integrator for ...

Understanding the conceptual relationships between tourism and leisure is important, particularly if tourism is considered a "special" form of leisure. The paper begins with behavioral conceptualizations of tourism and leisure, followed by a comparative behavioral analysis of tourism and leisure, then an examination of social theoretical accounts of the two fields. It argues that tourism is not a special form of leisure and that differences in social theoretical analyses of tourism and leisure might result from different research ideologies. Finally, the article concludes with the presentation of a behavioral synthesis of the two fields, along with identification of areas for future research. Keywords: conceptualizations, leisure, tourism, behavioral analysis, social theoretical analysis, everyday life.

In addition to high performance requirements, future generation mobile telecommunications brings new constraints to the semiconductor design world. In order to associate the flexibility to the highperformances and the low-energy consumption needed by this application domain we have developed a functional level dynamically reconfigurable architecture, DART. Even if this architecture supports the processing complexity of the UMTS while allowing the portability of the devices and their evolutions, another challenge is to develop efficient high-level design tools. In this paper, we discuss about a methodology allowing the definition of such development tool based on the joint used of compilation and behavioral synthesis schemes.

In this paper, we introduce a simple procedure to predict wiring delay in bi-directional buses and a way of properly sizing the driver for each of its port. In addition, we pr opose a simple calibration procedure to improve its delay prediction over the Elmore delay of the RC tree. The technique is fast, accurate, and ideal for implementation,in

This paper presents a resource-constrained scheduling scheme and a latency-constrained scheduling scheme that minimize power consumption for the case when the resources operate at multiple voltages. The resource-constrained scheduling reduces the power consumption by maximally utilizing resources operating at reduced voltages and, at the same time, reducing the latency. The latency-constrained scheduling scheme reduces the power consumption by assigning as many nodes (of the data flow graph) as possible to the resources operating at reduced voltages. Both schemes consider the effect of switching activity on the power consumption of the functional units. In addition, both schemes use heuristics to reduce the power consumed by the level shifters. Experiments with HLS benchmark examples show that the proposed schemes achieve significant power reduction when the operating voltages are 5 and 3.3 V or 5, 3.3, and 2.4 V.

With the rapid increase of complexity in Systemon-a-Chip (SoC) design, the electronic design automation (EDA) community is moving from RTL (Register Transfer Level) synthesis to behavioral-level and system-level synthesis. The needs of system-level verification and software/hardware codesign also prefer behavior-level executable specifications, such as C or SystemC. In this paper we present the platform-based synthesis system, named xPilot, being developed at UCLA. The first objective of xPilot is to provide novel behavioral synthesis capability for automatically generating efficient RTL code from a C or SystemC description for a given system platform and optimizing the logic, interconnects, performance, and power simultaneously. The second objective of xPilot is to provide a platform-based system-level synthesis capability, including both synthesis for application-specific configurable processors and heterogeneous multi-core systems. Preliminary experiments on FPGAs demonstrate the efficacy of our approach on a wide range of applications and its value in exploring various design tradeoffs.

SystemCoDesigner is an ESL tool developed at the University of Erlangen-Nuremberg, Germany. SystemCoDesigner offers a fast design space exploration and rapid prototyping of behavioral Sys-temC models. Together with Forte Design Systems, a fully automated approach was developed by integrating behavioral synthesis into the design flow. Starting from a behavioral SystemC model, hardware accelerators can be generated automatically using Forte Cynthesizer and can be added to the design space. The resulting design space is explored automatically by optimizing several objectives simultaneously using state of the art multi-objective optimization algorithms. As a result, SystemCoDesigner presents optimized hardware/software solutions to the designer who can select any of them for rapid prototyping on an FPGA basis. Thus, Sys-temCoDesigner bridges the gap from ESL to RTL and increases the confidence in early design decisions.

SystemC is a widely used electronic system-level (ESL) design language that can be used to model both hardware and software at different stages of system design. There has been a lot of research on behavior synthesis of hardware from SystemC, but relatively little work on synthesizing embedded software for SystemC designs. In this letter, we present an approach to automatic software synthesis from SystemC-based on coroutines instead of the traditional approaches based on real-time operating system (RTOS) threads. Performance evaluation results on some realistic applications show that our approach results in impressive reduction of runtime overheads compared to the thread-based approaches.

We present a framework for high-level synthesis that enables the designer to explore the best choice of source level and low level parallelizing transformations for improved synthesis. Within this framework, we have implemented a methodology that applies a set of parallelizing code transformations, both at the source level and during scheduling. Using these transformations, the designer can optimize high-level synthesis results and reduce the impact of control flow constructs on the quality of results. In our methodology, we first apply a set of source level pre-synthesis transformations that include common sub-expression elimination (CSE), copy propagation, dead code elimination and loop-invariant code motion, along with more coarse level code restructuring transformations such as loop unrolling. We then explore scheduling techniques that use a set of aggressive speculative code motions to maximally parallelize the design by re-ordering, speculating and sometimes even duplicating operations in the design. In particular, we present a new technique called "Dynamic CSE" that dynamically coordinates CSE and code motions such as speculation and conditional speculation during scheduling. We also show how operation chaining across conditional boundaries can be used to optimize control flow. We have built the Spark high-level synthesis framework that takes a behavioral description in ANSI-C as input and generates synthesizable register-transfer level VHDL. Our results from three moderately complex design targets, namely, MPEG-1, MPEG-2 and the GIMP image processing tool validate the utility of our approach to the behavioral synthesis of designs with complex control flows.

This paper considers the role of performance and area estimates from behavioral synthesis in design space exploration. We have developed a compilation system that automatically maps high-level algorithms written in C to applicationspecific designs for Field Programmable Gate Arrays (FP-GAs), through a collaboration between parallelizing compiler technology and high-level synthesis tools. Using several code transformations, the compiler optimizes a design to increase parallelism and utilization of external memory bandwidth, and selects the best design among a set of candidates. Performance and area estimates from behavioral synthesis provide feedback to the compiler to guide this selection. Estimates can be derived far more quickly (up to several orders of magnitude faster) than full synthesis and place-and-route, thus allowing the compiler to consider many more designs than would otherwise be practical. In this paper, we examine the accuracy of the estimates from behavioral synthesis as compared to the fully synthesized designs for a collection of 209 designs for five multimedia kernels. Though the estimates are not completely accurate, our results show that the same design would be selected by the design space exploration algorithm, whether we use estimates or actual results from place-and-route, because it favors smaller designs and only increases complexity when the benefit is significant.

The system-on-chip design methodology is a new paradigm for electrical and computer engineering education in digital logic and microelectronics. The development of a close relationship between the undergraduate course sequence in digital logic and behavioral synthesis and that in electronics and microelectronics has been problematical until now. The system design issues considered by these two historically distinct course sequences usually did not have very much in common. The Western Design Center, Inc., Mesa, AZ, USA and the Department of Electrical and Computer Engineering, Temple University, Philadelphia, PA, USA have now established the System Chip Design Center to address these issues in engineering education and the resulting system-on-chip design methodology. The traditional undergraduate sequence in digital logic consists of three courses: combinational and sequential logic with schematic capture and a register transfer language; a processor architecture and assembly langua...

When synthesizing control-ow dominated descriptions based on VHDL, dierent styles of semantically equivalent descriptions may dier signicantly in quality. This paper discusses the eect of the input description on High-Level Synthesis when using VHDL. In order to show this eect, a high speed p r otocol based o n the ISO reference p r otocol Abracadabra is used. Five VHDL descriptions styles of the same protocol have been synthesized using AMICAL, a VHDL based b ehavioral synthesis tool. Discussions of the dierent results leads to a VHDL based methodology for protocol modelling in order to produce ecient designs.

Many techniques for power management employed in advanced RTL synthesis tools rely explicitly or implicitly on observability don't-care (ODC) conditions. In this paper we present a systematic approach to maximizing the effectiveness of these techniques by generating power-friendly RTL descriptions in a behavioral synthesis tool. We first introduce the concept of behavior-level observability and investigate its relation with observability under a given schedule, using an extension of Boolean algebra. We then propose an efficient algorithm to compute behavior-level observability on a data-flow graph. Our algorithm exploits knowledge about select and Boolean instructions, and allows certain forms of other knowledge, once uncovered, to be considered for stronger observability conditions. We also describe a behavioral synthesis flow where behavior-level observability is used to guide the scheduler toward maximizing the likelihood that execution of power-hungry instructions will be avoided under a latency constraint. Experimental results show that our approach is able to reduce total power, and it outperforms a previous method in [15] by 17.7% on average, on a set of real-world designs. To the best of our knowledge, this is the first work to use a comprehensive behavioral-level observability analysis to guide optimizations in behavioral synthesis.

... George Economakos, Petros Oikonomakos, Ioannis Panagopoulos, Ioannis Poulakis and George Papakonstantinou National Technical University of Athens Department of Electrical and Computer Engineering Zographou Campus, GR-15773 Athens, Greece ...

Early performance feedback and design space exploration of complete FPGA designs are still time consuming tasks. We propose an original methodology based on estimations to reduce the impact on design time. We promote a hierarchical exploration to mitigate the complexity of the exploration process. Therefore this work takes place before any design step, such as compilation or behavioral synthesis, where the specification is still provided as a C program. The goal is to provide early area and delay evaluations of many RTL implementations to prune the design space. Two main steps compose the flow: (1) a structural exploration step defines several RTL implementations, and (2) a physical mapping estimation step computes the mapping characteristics of these onto a given FPGA device. For the structural exploration, a simple yet realistic RTL model reduces the complexity and permits a fast definition of solutions. At this stage, we focus on the computation parallelism and memory bandwidth. Advanced optimizations using for instance loop tiling, scalar replacement or data layout are not considered. For the physical estimations, an analytical approach is used to provide fast and accurate area / delay trade-offs. We do not consider the impact of routing on critical paths or other optimizations. The reduction of the complexity allows the evaluation of key design alternatives, namely target device and parallelism that can also include the effect of resource allocation, bitwidth or clock period. Due to this, a designer can quickly identify a reliable subset of solutions for which further refinement can be applied to enhance the relevance of the final architecture and reach a better use of FPGA resources, i.e. an optimal level of performance. Experiments performed with Xilinx (VirtexE) and Altera (Apex20K) FPGAs for a 2D Discrete Wavelet Transform and a G722 speech coder lead to an average error of 10% for temporal values and 18% for area estimations.

This paper presents a resource-constrained scheduling scheme and a latency-constrained scheduling scheme that minimize power consumption for the case when the resources operate at multiple voltages. The resource-constrained scheduling reduces the power consumption by maximally utilizing resources operating at reduced voltages and, at the same time, reducing the latency. The latency-constrained scheduling scheme reduces the power consumption by assigning as many nodes (of the data flow graph) as possible to the resources operating at reduced voltages. Both schemes consider the effect of switching activity on the power consumption of the functional units. In addition, both schemes use heuristics to reduce the power consumed by the level shifters. Experiments with HLS benchmark examples show that the proposed schemes achieve significant power reduction when the operating voltages are 5 and 3.3 V or 5, 3.3, and 2.4 V.

We present a framework for high-level synthesis that enables the designer to explore the best choice of source level and low level parallelizing transformations for improved synthesis. Within this framework, we have implemented a methodology that applies a set of parallelizing code transformations, both at the source level and during scheduling. Using these transformations, the designer can optimize high-level synthesis results and reduce the impact of control flow constructs on the quality of results. In our methodology, we first apply a set of source level pre-synthesis transformations that include common sub-expression elimination (CSE), copy propagation, dead code elimination and loop-invariant code motion, along with more coarse level code restructuring transformations such as loop unrolling. We then explore scheduling techniques that use a set of aggressive speculative code motions to maximally parallelize the design by reordering , speculating and sometimes even duplicating operations in the design. In particular, we present a new technique called "Dynamic CSE" that dynamically coordinates CSE and code motions such as speculation and conditional speculation during scheduling. We also show how operation chaining across conditional boundaries can be used to optimize control flow. We have built the Spark high-level synthesis framework that takes a behavioral description in ANSI-C as input and generates synthesizable register-transfer level VHDL. Our results from three moderately complex design targets, namely, MPEG-1, MPEG-2 and the GIMP image processing tool validate the utility of our approach to the behavioral synthesis of designs with complex control flows.

Abstract Hardware resources can be shared to reduce the area of the resulting design. The synthesis system must ensure that no resource conflicts arise due to simultaneous access of a shared hardware,resource. With traditional scheduling formulations where operations are statically assigned to control steps, conflict resolution simply determines whether two operations can execute concurrently based on their control step assignment. In this case, operations are assumed,to have fixed execution delay. For hardware,models,that supports external synchronization and handshaking, however, operations may have unbounded execution delay , e.g., detecting the rising edge of a signal. The presence of unbounded,delay operations invalidates the traditional scheduling and conflict resolution approaches. We formulate in this paper conflict resolution as the task of serializing operations bound,to the same,hardware resource. A technique called constrained conflict resolution is presented to resolve resource conflicts such that the resulting design satisfies the required timing and handshaking,requirements. The timing constraint topology is used to reduce the computation,time of the algorithm. This technique extends the relative scheduling formulation to support resource sharing under timing constraints. We describe both exact and heuristic algorithms to resolve resource conflicts; these algorithms are implemented,in a synthesis system,called Hebe that is targeted towards the synthesis of Application-Specific Integrated Circuit designs. Results of applying the system to the design of benchmark,and complex,ASIC designs are presented. Keywords: Resource conflict resolution, high-level synthesis, automated synthesis, behavioral synthesis, hard-

We present a framework for high-level synthesis that enables the designer to explore the best choice of source level and low level parallelizing transformations for improved synthesis. Within this framework, we have implemented a methodology that applies a set of parallelizing code transformations, both at the source level and during scheduling. Using these transformations, the designer can optimize high-level synthesis results and reduce the impact of control flow constructs on the quality of results. In our methodology, we first apply a set of source level pre-synthesis transformations that include common sub-expression elimination (CSE), copy propagation, dead code elimination and loop-invariant code motion, along with more coarse level code restructuring transformations such as loop unrolling. We then explore scheduling techniques that use a set of aggressive speculative code motions to maximally parallelize the design by reordering , speculating and sometimes even duplicating operations in the design. In particular, we present a new technique called "Dynamic CSE" that dynamically coordinates CSE and code motions such as speculation and conditional speculation during scheduling. We also show how operation chaining across conditional boundaries can be used to optimize control flow. We have built the Spark high-level synthesis framework that takes a behavioral description in ANSI-C as input and generates synthesizable register-transfer level VHDL. Our results from three moderately complex design targets, namely, MPEG-1, MPEG-2 and the GIMP image processing tool validate the utility of our approach to the behavioral synthesis of designs with complex control flows.

In this work we study the problem of estimating the power dissipation of the atomic components (macros) used to implement basic operations in behavioral synthesis. We first precisely define the key requisites for behavioral power macro-models and we briefly evaluate the suitability of several approaches proposed in the past. We then focus on a specific macro-modeling methodology that appears to be best suited for usage in a behavioral synthesis tool fB]. We analyze its limitations and we propose several original improvements. Finally, we evaluate the impact of the proposed improvements on macro-model accuracy and flexibility.

Reconfigurable Circuit (VRC) design methodology and intrinsic evolution for the design of small sequential circuits and their implementation on a single programmable chip with an embedded hardcore processor. The evolutionary algorithm is developed in software that runs on the embedded processor. Fitness function is calculated using hardware architecture and is used to guide the evolution process. This new method is applied to the development of a 3-bit sequence detector and the evolved architecture is implemented on a Xilinx tm Virtex-II pro device. Simulations were run on the evolved architecture and on the same circuit designed using conventional Hardware Descriptive Language (HDL). Both designs showed the same functional behavior. Synthesis results show that the new method can be used in successfully implementing small sequential circuits on a reconfigurable hardware environment.

This paper presents a resource-constrained scheduling scheme and a latency-constrained scheduling scheme that minimize power consumption for the case when the resources operate at multiple voltages. The resource-constrained scheduling reduces the power consumption by maximally utilizing resources operating at reduced voltages and, at the same time, reducing the latency. The latency-constrained scheduling scheme reduces the power consumption by assigning as many nodes (of the data flow graph) as possible to the resources operating at reduced voltages. Both schemes consider the effect of switching activity on the power consumption of the functional units. In addition, both schemes use heuristics to reduce the power consumed by the level shifters. Experiments with HLS benchmark examples show that the proposed schemes achieve significant power reduction when the operating voltages are 5 and 3.3 V or 5, 3.3, and 2.4 V.

This paper describes Haydn, a hardware compilation approach which aims to combine the benefits of cycle accu-rate descriptions such as ease of control and performance, and the rapid development and design exploration facili-ties in behavioral synthesis tools. Our approach supports ...

This paper focuses on the application of Virtual Reconfigurable Circuit (VRC) design methodology and intrinsic evolution for the design of small sequential circuits and their implementation on a single programmable chip with an embedded hardcore processor. The evolutionary algorithm is developed in software that runs on the embedded processor. Fitness function is calculated using hardware architecture and is used to guide the evolution process. This new method is applied to the development of a 3-bit sequence detector and the evolved architecture is implemented on a Xilinx tm Virtex-II pro device. Simulations were run on the evolved architecture and on the same circuit designed using conventional Hardware Descriptive Language (HDL). Both designs showed the same functional behavior. Synthesis results show that the new method can be used in successfully implementing small sequential circuits on a reconfigurable hardware environment.

Abstract. In addition to high performance requirements, future gen-eration mobile telecommunications brings new constraints to the semi-conductor design world. In order to associate the flexibility to the high-performances and the low-energy consumption needed by this application domain we have developed a functional level dynamically reconfigurable architecture, DART. Even if this architecture supports the processing complexity of the UMTS while allowing the portability of the devices and their evolutions, another challenge is to develop efficient high-level design tools. In this paper, we discuss about a methodology allowing the definition of such development tool based on the joint used of compilation and behavioral synthesis schemes. 1

The use of radio frequency identification (RFID) technology is expanding rapidly in numerous applications such as logistics, supply chain management, transportation, healthcare and aviation. Due to the variety of the current applications, typical RFID systems use application specific hardware and proprietary protocols. These systems generally have long design times, no tolerance to changes in application or standard, and hence very high system costs. This paper describes an RFID tag specification and automated design flow for the creation of customized, low-power, active RFID tags. RFID primitives supported by the tag are enumerated with assembly like RFID macros. From these macros, the RFID pre-processor generates templates automatically. The behavior of each RFID primitive is specified using ANSI C where indicated within the template. The resulting file is compiled by the RFID compiler for the extensible tag. In order to save power, a smart buffer has been developed to sit between the transceiver and the tag controller. Because RFID packets are broadcast to everyone in range, the smart buffer contains minimal logic to detect whether incoming packets are intended for the tag. By doing so, the main controller may remain powered down to reduce system power consumption. Two System-on-a-Chip implementation strategies are presented. First, a microprocessor based system for which a C program is automatically generated and compiled for the system. The second replaces the microprocessor with a block of low-power FPGA logic. The user supplied RFID logic is specified in RFID macros and ANSI-C and automatically converted into combinational VHDL by the RFID compiler. Based on a test program, the processors required 183, 43, and 19 lJ per transaction for StrongARM, XScale, and EISC processors, respectively. By replacing the processor with a Coolrunner II, the controller can be reduced to 1.11 nJ per transaction.

Behavioral synthesis of synchronous systems is a well established and researched area. The transformation of behavioral description into a datapath and control graph, and hence, to a structural realization usually requires three fundamental steps: 1) scheduling (the mapping of behavioral operations onto time slots); 2) allocation (the mapping of the behavioral operations onto abstract functional units); and 3) binding (the mapping of the functional units onto physical cells). Optimization is usually achieved by intelligent manipulation of these three steps in some way. Key to the operation of such a system is the (automatically generated) control graph, which is effectively a complex sequence generator controlling the passage of data through the system in time to some synchronizing clock. The maximum clock speed is dictated by the slowest time slot. (This is the timeslot containing the longest combinational logic delay.) Timeslots containing quicker (less) logic will effectively waste time: the output of the combinational logic in the state will have settled long before the registers reading the data are enabled. If we allow the state to change as soon as the data is ready, by introducing the concepts of "ready" and "acknowledge," the control graph becomes a disjoint set of single-state machines-it effectively disappears, with the consequence that the timeslot-timeslot transitions become self controlling. Having removed the necessity for the timeslots to be of equal duration the system becomes selftiming: asynchronous. This paper describes a behavioral asynchronous synthesis system based on this concept that takes as input an algorithmic description of a design and produces an asynchronous structural implementation. Several example systems are synthesized both synchronously and asynchronously (with no modification to the high level description). In keeping with the well-established observation that asynchronous systems operate at average case time complexity rather than worse case, the asynchronous structures usually operate some 30% faster than their synchronous counterparts, although interesting counterexamples are observed. Index Terms-Asynchronous synthesis, behavioral synthesis. I. INTRODUCTION A SYNCHRONOUS circuits have many potential advantages over their synchronous equivalents [1]-[3], including lower latency, lower power consumption, and lower electromagnetic interference. However, their acceptance into industry has been slow, which may be due to a number of reasons: First, the techniques required to design synchronous circuits are well known and taught to all students of electronics, whereas few people have the skills to design asynchronous

This article presents methods to translate a behavioral-level analog description into a Field Programmable Analog Array (FPAA) implementation. The methods consist of several steps that are referred to as function decomposition, macrocell synthesis, placement and routing, and postplacement simulation. The focus of this article is on the first three steps. The function decomposition step deals with decomposing a high-order system function into a set of lower-order functions. We present an efficient procedure for searching for an optimal solution. This procedure is based on first formally demonstrating the equivalence of two previously used optimization criteria. The objective of the macrocell synthesis step is to generate a hardware realization. A modified signal flow graph is introduced to represent FPAA circuits and graph transformations are used to identify the realizations that comply with the FPAA hardware constraints. The modified signal flow graph also allows scaling of capacit...

Many techniques for power management employed in advanced RTL synthesis tools rely explicitly or implicitly on observability don't-care (ODC) conditions. In this paper we present a systematic approach to maximizing the effectiveness of these techniques by generating power-friendly RTL descriptions in a behavioral synthesis tool. We first introduce the concept of behavior-level observability and investigate its relation with observability under a given schedule, using an extension of Boolean algebra. We then propose an efficient algorithm to compute behavior-level observability on a data-flow graph. Our algorithm exploits knowledge about select and Boolean instructions, and allows certain forms of other knowledge, once uncovered, to be considered for stronger observability conditions. We also describe a behavioral synthesis flow where behavior-level observability is used to guide the scheduler toward maximizing the likelihood that execution of power-hungry instructions will be avoided under a latency constraint. Experimental results show that our approach is able to reduce total power, and it outperforms a previous method in [15] by 17.7% on average, on a set of real-world designs. To the best of our knowledge, this is the first work to use a comprehensive behavioral-level observability analysis to guide optimizations in behavioral synthesis.

With the rapid increase of complexity in Systemon-a-Chip (SoC) design, the electronic design automation (EDA) community is moving from RTL (Register Transfer Level) synthesis to behavioral-level and system-level synthesis. The needs of system-level verification and software/hardware codesign also prefer behavior-level executable specifications, such as C or SystemC. In this paper we present the platform-based synthesis system, named xPilot, being developed at UCLA. The first objective of xPilot is to provide novel behavioral synthesis capability for automatically generating efficient RTL code from a C or SystemC description for a given system platform and optimizing the logic, interconnects, performance, and power simultaneously. The second objective of xPilot is to provide a platform-based system-level synthesis capability, including both synthesis for application-specific configurable processors and heterogeneous multi-core systems. Preliminary experiments on FPGAs demonstrate the efficacy of our approach on a wide range of applications and its value in exploring various design tradeoffs.

We introduce a new approach to take into account the memory architecture and the memory mapping in the High- Level Synthesis of Real-Time embedded systems. We formalize the memory mapping as a set of constraints for the synthesis, and defined a Memory Constraint Graph and an accessibility criterion to be used in the scheduling step. We use a memory mapping

For CMOS technologies below 65nm, gate oxide direct tunneling current is a major component of the total power dissipation. This paper presents a simulated annealing based algorithm for the gate leakage current reduction by simultaneous scheduling, allocation and binding during behavioral synthesis. Gate leakage current reduction is based on the use of functional units of different oxide thickness while simultaneously accounting for process variations. We present a cost function that minimizes leakage and area overhead. The algorithm minimizes the cost function for a given delay trade-off factor. It uses a pre-characterized cell library for tunneling current, delay and area, expressed as analytical functions of the gate oxide thickness T ox . We tested our approach using a number of behavioral level benchmark circuits characterized for a 45nm library by integrating our algorithm into a high-level synthesis system. We obtained an average gate leakage reduction of 76.88% with an average area overhead of 17.38% for different delay trade-off factors ranging from 1.0 to 1.4.

Due to exponential behavior of gate-oxide leakage current with temperature and technology scaling, leakage power plays important role in nano − CM OS circuit. In this paper, we present simultaneous scheduling and binding algorithm for optimizing leakage current during behavioral synthesis. It uses T ED (Taylor Expansion Diagram) for generating optimized DF G (Data Flow Graph). Once DF G is obtained, it selectively binds non-critical components to corresponding functional unit consisting of transistors of high oxide thickness and critical components with low oxide thickness. As the algorithm considers time-constraint explicitly, it reduces leakage current without degrading the performance of the design. Experimental results on a set of behavioral synthesis benchmarks for 45nm process show 30% to 70% reduction in leakage current compared to the results obtained by a conventional optimization flow.

ABSTRACT Heterogeneous MPSoC design where flexible programmable cores are combined with optimized HW co-processors is a quite complex and challenging task. In this paper, we present a system-level design flow that uses a single functional reference for modeling both HW ...

Abstract- This paper addresses the problem of true delay estimation during high level design. The existing delay estimation techniques ei-ther estimate the topological delay of the circuit which may be pes-simistic, or use gate-level timing analysis for calculating the true de-lay, which may be prohibitively expensive. We show that the paths in the implementation of a behavioral spec-ification can be partitioned into two sets, SP and UP. While the paths in SP can affect the delay of the circuit, the paths in UP cannot. Con-sequently, the true delay of the resulting circuit can be computed by just measuring the topological delay of the paths in SP, eliminating the need for the computationally intensive process of path sensitiza-tion. Experimental results show that high-level true delay estimation can be done very fast, even when gate-level true delay estimation be-comes computationally infeasible. The high-level delay estimates are verified by comparing with delay estimates obtained ...

As we move from algorithm on a chip to system on a chip era, the design bottleneck is shifting from individual DSP functions to global control that composes a system from these functions. The practice in industry suffers from global control entering the design flow too late, discontinuity between functional modeling and implementation phase and mixing data flow with global control. MASIC-Maths to ASIC-is a methodology proposed in this paper that targets DSP SOCs and addresses these issues. Global control is specified in a grammar notation and integrates the output of functional modeling phase, the DSP functions, by referencing them. A virtual prototype is automatically built from such a specification that models the global control in VHDL and cosimulates with the DSP functions in C from the functional modeling phase. A highly efficient verification methodology based on separating the verification of global control from DSP functions is proposed. A smooth path to cycle true implementation is possible using either behavioral synthesis, IPs for the DSP functions or manual implementation. Experiments using realistic examples like GSM base band processing, rake receiver and some smaller examples have been carried out to quantify the benefits of MASIC.

We present a framework for high-level synthesis that enables the designer to explore the best choice of source level and low level parallelizing transformations for improved synthesis. Within this framework, we have implemented a methodology that applies a set of parallelizing code transformations, both at the source level and during scheduling. Using these transformations, the designer can optimize high-level synthesis results and reduce the impact of control flow constructs on the quality of results. In our methodology, we first apply a set of source level pre-synthesis transformations that include common sub-expression elimination (CSE), copy propagation, dead code elimination and loop-invariant code motion, along with more coarse level code restructuring transformations such as loop unrolling. We then explore scheduling techniques that use a set of aggressive speculative code motions to maximally parallelize the design by reordering , speculating and sometimes even duplicating operations in the design. In particular, we present a new technique called "Dynamic CSE" that dynamically coordinates CSE and code motions such as speculation and conditional speculation during scheduling. We also show how operation chaining across conditional boundaries can be used to optimize control flow. We have built the Spark high-level synthesis framework that takes a behavioral description in ANSI-C as input and generates synthesizable register-transfer level VHDL. Our results from three moderately complex design targets, namely, MPEG-1, MPEG-2 and the GIMP image processing tool validate the utility of our approach to the behavioral synthesis of designs with complex control flows.

We introduce a new approach to take into account the memory architecture and the memory mapping in behavioral synthesis. We present a new strategy for implementing signals (ageing vectors). We formalize the maturing process and explain how it may generate memory conflicts over several iterations of the algorithm. The final Compatibility Graph indicates the set of valid mappings for every signal. Several experiments are performed with our HLS tool GAUT. Our strategy exhibits a relatively low complexity memory architecture for ageing vectors that permits to tackle complex designs for data intensive applications. I. I NTRODUCTION