2018 1st Workshop on Energy Efficient Machine Learning and Cognitive Computing for Embedded Applications (EMC2), 2018
The automotive industry is undergoing a revolution with connected, autonomous and electric vehicl... more The automotive industry is undergoing a revolution with connected, autonomous and electric vehicles and the benefits they can bring to the public. Drivers enjoying their daily commute, fewer road fatalities and less pollution are all possible thanks to new technologies. Car makers need to offer these features but at the same time make sure vehicles are safe and secure. In the coming years, there will be various levels of automation until we have fully autonomous vehicles. To achieve any level of automation, cars need to connect to other vehicles, connect to the infrastructure, sense the environment through various sensors such as camera and radar and then make maneuvering decisions based on all these inputs. Artificial intelligence is and will be deployed heavily to accomplish many of the tasks of autonomous driving. Perception and decision-making based on artificial intelligence introduces an entirely new set of challenges to car makers to ensure no security compromises as well as proving the decisions being made are functionally, behaviorally and environmentally safe. The challenge can be described in a simple question: "If a machine learning based car system is accurate 99% of the time, are you willing to ride this car knowing that it will be wrong 1% of the time? What is the consequence of that incorrect decision?" Deep expertise and research in the safety and security aspects of AI are needed to ensure future mass deployment and success in the area of autonomous driving.
In this paper, we present a comprehensive high-level synthesis system that is geared towards redu... more In this paper, we present a comprehensive high-level synthesis system that is geared towards reducing power consumption in control-flow intensive circuits. An iterative improvement algorithm is at the heart of the system. The algorithm searches the design space by handling scheduling, module selection, resource sharing and multiplexer network restructuring simultaneously. The scheduler performs concurrent loop optimization and implicit loop unrolling. It minimizes the expected number of cycles of the schedule without compromising on the minimum and maximum schedule lengths. A fast simulation technique based on trace manipulation aids power estimation in driving synthesis in the right direction. Experimental results demonstrate power reduction of up to 85% with minimal overhead in area over areaoptimized designs operating at 5V.
2009 Design, Automation & Test in Europe Conference & Exhibition, 2009
Memories are increasingly dominating Systems on Chip (SoC) designs and thus contribute a large pe... more Memories are increasingly dominating Systems on Chip (SoC) designs and thus contribute a large percentage of the total system's power dissipation, area and reliability. In this paper, we present a tool which captures the effects of supply voltage V dd and temperature on memory performance and their interrelationships. We propose a Temperature-and Reliability-Aware Memory Design (TRAM) approach which allows designers to examine the effects of frequency, supply voltage, power dissipation, and temperature on reliability in a mutually interrelated manner. Our experimental results indicate that thermal unaware estimation of probability of error can be off by at least two orders of magnitude and up to five orders of magnitude from the realistic, temperature-aware cases. We also observed that thermal aware V dd selection using TRAM can reduce the total power dissipation by up to 2.5X while attaining an identical predefined limit on errors.
There is a growing need for accurate power models at the system level. Memory structures such as ... more There is a growing need for accurate power models at the system level. Memory structures such as caches, Branch Target Buffers (BTBs), and register files occupy significant area in contemporary SoC designs and are the main contributors to system leakage power dissipation. Existing models for leakage power estimation in array structures typically use coefficients derived from elaborate SPICE simulations. However, these methodologies are not applicable to array designs in a newer technology, that require power estimates early in the design cycle. In this paper, we propose analytical models for array structures that are based only on high level design parameters. Assuming typical circuit implementation styles, we identify the transistors that contribute to the leakage power in each array sub-circuit and develop models as a function of the operation (read/write/idle) on the array and organizational parameters of the array. The developed models are validated by comparing their estimates ...
2008 IEEE International Symposium on VLSI Design, Automation and Test (VLSI-DAT), 2008
ABSTRACT Summary form only given. Improvements in the speed and the size of chips due to process ... more ABSTRACT Summary form only given. Improvements in the speed and the size of chips due to process scaling come with the penalties of increased power densities and higher operating temperatures. Higher temperature not only poses a risk of thermal runaway of the chips but also increases leakage-power dissipation and reduces interconnect lifetime. Furthermore, the floorplan of a System-on-a-Chip (SoC) has a significant impact on the temperature profile and leakage power, requiring early analysis of the SoC temperature profiles. We will talk about a system level leakage estimation methodology that considers the floorplan of the SoC and also the positive feedback relation between temperature and leakage power. We also talk about a system-level Leakage-Aware Floorplanner (LEAF) that optimizes floorplans for temperature-aware leakage power along with the traditional metric of area. We observed up to 190% difference in the leakage power between leakage-unaware and leakage-aware floorplanning. Temperature also has a serious effect on the Mean Time to Failure (MTF) of interconnects because of electromigration. To address this issue, we have developed a Temperature Aware Global Router (TAGORE) that reduces the probability of chip failure due to interconnect failures. TAGORE achieves a reduction in the probability of failure by routing more wires in the colder regions of the chip and fewer wires in the hotter regions of the chip. We observed that TAGORE reduced the number of wires in the hottest region of a chip by up to 19.95% and by an average of 12.29%. This resulted in a decrease in the failure rate by up to 292 failures per million hours of operation. This approach to reliability improvement does not require any addition of redundant wires or vias. We also have an analytical examination of the reduction in the probability of interconnect failure and the failure rate due to temperature aware global routing.
Proceedings of the 2nd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis - CODES+ISSS '04, 2004
There is a growing need for accurate power models at the system level. Memory structures such as ... more There is a growing need for accurate power models at the system level. Memory structures such as caches, Branch Target Buffers (BTBs), and register files occupy significant area in contemporary SoC designs and are the main contributors to system leakage power dissipation. Existing models for leakage power estimation in array structures typically use coefficients derived from elaborate SPICE simulations. However, these methodologies are not applicable to array designs in a newer technology, that require power estimates early in the design cycle. In this paper, we propose analytical models for array structures that are based only on high level design parameters. Assuming typical circuit implementation styles, we identify the transistors that contribute to the leakage power in each array sub-circuit and develop models as a function of the operation (read/write/idle) on the array and organizational parameters of the array. The developed models are validated by comparing their estimates against the leakage power measured using SPICE simulations on industrial array designs belonging to the e500 1 processor core. The comparison shows that the models are accurate with an error margin of less than 21.5% and thus can be used in high-level power-performance exploration. Interestingly, in array designs with dual threshold voltage technology, we observed that contrary to the general expectation, the array memory core contributes to just 9% and the address decoder contributes to as much as 62% of the total leakage power.
Proceedings of the 1998 international symposium on Low power electronics and design - ISLPED '98, 1998
Page 1. Fast High-level Power Estimation for Control-flow Intensive Designs Kamal S. Khouri, Gane... more Page 1. Fast High-level Power Estimation for Control-flow Intensive Designs Kamal S. Khouri, Ganesh Lakshminarayana, and Niraj K. Jha Department of Electrical Engineering Princeton University, Princeton, NJ 08544 Abstract ...
In this paper, we present a novel scheduling algorithm targeted towards minimizing the average ex... more In this paper, we present a novel scheduling algorithm targeted towards minimizing the average execution time of control-flow intensive behavioral descriptions. Our algorithm uses a control-data flow graph (CDFG) model, which preserves the parallelism inherent in the application. It explores previously unexplored regions of the solution space through its ability to overlap the schedules of independent iterative constructs, whose bodies share resources. It also incorporates well-known optimization techniques like loop unrolling in a natural fashion. This is made possible by a general loop-handling technique, which we have devised. Application of the algorithm to several common benchmarks demonstrates up to 4.8-fold improvement in expected schedule length over existing scheduling algorithms, without paying a price in terms of the bestand worst-case schedule lengths required to execute the behavioral description (in fact, frequently, the best/worst-case schedule lengths are also better for our algorithm).
This paper presents a design methodology, called common-case com- putation (CCC), and new design ... more This paper presents a design methodology, called common-case com- putation (CCC), and new design automation algorithms for optimiz- ing power consumption or performance. The proposed techniques are applicable in conjunction with any high-level design methodol- ogy where a structural register-transfer level (RTL) descr iption and its corresponding scheduled behavioral (cycle-accurate f unctional RTL) description are available. It is a well-known
Proceedings of the 36th ACM/IEEE conference on Design automation conference - DAC '99, 1999
This paper presents a design methodology, called common-case com- putation (CCC), and new design ... more This paper presents a design methodology, called common-case com- putation (CCC), and new design automation algorithms for optimiz- ing power consumption or performance. The proposed techniques are applicable in conjunction with any high-level design methodol- ogy where a structural register-transfer level (RTL) descr iption and its corresponding scheduled behavioral (cycle-accurate f unctional RTL) description are available. It is a well-known
This paper presents a design methodology, called common-case com- putation (CCC), and new design ... more This paper presents a design methodology, called common-case com- putation (CCC), and new design automation algorithms for optimiz- ing power consumption or performance. The proposed techniques are applicable in conjunction with any high-level design methodol- ogy where a structural register-transfer level (RTL) descr iption and its corresponding scheduled behavioral (cycle-accurate f unctional RTL) description are available. It is a well-known
20th International Conference on VLSI Design held jointly with 6th International Conference on Embedded Systems (VLSID'07), 2007
In this paper we demonstrate the impact of the floorplan on the temperature-dependent leakage pow... more In this paper we demonstrate the impact of the floorplan on the temperature-dependent leakage power of a System on Chip (SoC). We propose a novel system level temperature aware and floorplan aware leakage power estimator, STEFAL, which considers both the floorplan of the SoC and the cycle-by-cycle dynamic power behavior while estimating the leakage power. We implemented our estimation methodology on ten industrial SoC designs from Freescale Semiconductor Inc. and observed up to a 190% difference in the leakage power between various floorplans, clearly showing the importance of considering the floorplans and the temperature profile during leakage power estimation.
2008 14th International Workshop on Thermal Inveatigation of ICs and Systems, 2008
Increased operating temperatures of chips have aggravated leakage and reliability issues, both of... more Increased operating temperatures of chips have aggravated leakage and reliability issues, both of which are adversely affected by high temperature. Due to thermal diffusion among IP-blocks and the interdependence of temperature and leakage power, we observe that the floorplan has an impact on both the temperatures and the leakage of the IP-blocks in a System on Chip (SoC). An increase in temperature also increases the probability of errors such as read/write errors or unstable memory accesses. In a thermal unaware paradigm, SRAM designers increase (overdrive) the supply voltage (V dd ) to increase their reliability. However, increasing V dd in turn increases the memory's leakage and dynamic power dissipation and its temperature is elevated. Thus V dd , power, temperature, and probability of errors influence each other mutually and must be considered during SRAM design. This paper addresses two issues: (i) we propose a novel system level Leakage Aware Floorplanner which optimizes floorplans for thermal-aware leakage power along with the traditional metrics of area and wire length; and (ii) we demonstrate the effect of temperature on the probability of errors of SRAM memories which helps designers select a thermal-aware operating voltage for SRAMs. We will also discuss temperatureā‡”leakage positive feedback loop. We applied our floorplanner on eight industrial SoC designs from Freescale Semiconductor Inc. and we observed up to 135% difference in the leakage power between leakage-unaware and leakage aware floorplanning. In this paper we also quantify the effect of temperature on the probability of failures in memories. We observed that by considering the effect of temperature on memories, reducing V dd can help improve both the reliability and the power dissipation. For a predefined limit on reliability, thermal aware V dd selection can reduce the total power dissipation by up to 2.5X.
2009 International Symposium on VLSI Design, Automation and Test, 2009
In current Systems-on-Chip (SoC) designs, managing peak temperature is critical to ensure operati... more In current Systems-on-Chip (SoC) designs, managing peak temperature is critical to ensure operation without failure. Our novel Communication Architecture Based Thermal Management (CBTM) scheme manages thermal behavior of components by delaying the execution of chosen IP-blocks or components by regulating the flow of data over the on-chip communication bus. This temperature aware traffic flow over the bus is achieved by dynamically changing the communication priority table in response to thermal readings from sensors. With CBTM, the temperatures of individual components can be controlled selectively. In this paper we demonstrate the effectiveness of CBTM on four industrial size SoC designs and also evaluate its performance impact. We observe that CBTM maintained thermal thresholds and reduced the peak temperature of an SoC by as much as 29 o C.
9th International Symposium on Quality Electronic Design (isqed 2008), 2008
In this paper we propose thermal aware global routing of interconnects which reduces the probabil... more In this paper we propose thermal aware global routing of interconnects which reduces the probability of failure of chips due to interconnect failures. Temperature has a very serious effect on the mean time to failure (MTF) of interconnects because of electromigration. We present TAGORE, a thermal aware global router. TAGORE achieves a reduction in the probability of failure by routing
2007 Asia and South Pacific Design Automation Conference, 2007
Process scaling and higher leakage power have resulted in increased power densities and elevated ... more Process scaling and higher leakage power have resulted in increased power densities and elevated die temperatures. Due to the interdependence of temperature and leakage power, we observe that the floorplan has an impact on both the temperatures and the leakage of the IP-blocks in a system on chip (SoC). Hence, in this paper we propose a novel system level Leakage Aware Floorplanner (LEAF) which optimizes floorplans for temperature-aware leakage power along with the traditional metrics of area and wire length. Our floorplanner takes a SoC netlist and the dynamic power profile of functional blocks to determine a placement while optimizing for temperature dependent leakage power, area, and wire length. To demonstrate the effectiveness of LEAF, we implemented our methodology on ten industrial SoC designs from Freescale Semiconductor Inc. and evaluated the trade-off between leakage power and area. We observed up to 190% difference in the leakage power between leakage-unaware and leakage aware floorplanning.
2018 1st Workshop on Energy Efficient Machine Learning and Cognitive Computing for Embedded Applications (EMC2), 2018
The automotive industry is undergoing a revolution with connected, autonomous and electric vehicl... more The automotive industry is undergoing a revolution with connected, autonomous and electric vehicles and the benefits they can bring to the public. Drivers enjoying their daily commute, fewer road fatalities and less pollution are all possible thanks to new technologies. Car makers need to offer these features but at the same time make sure vehicles are safe and secure. In the coming years, there will be various levels of automation until we have fully autonomous vehicles. To achieve any level of automation, cars need to connect to other vehicles, connect to the infrastructure, sense the environment through various sensors such as camera and radar and then make maneuvering decisions based on all these inputs. Artificial intelligence is and will be deployed heavily to accomplish many of the tasks of autonomous driving. Perception and decision-making based on artificial intelligence introduces an entirely new set of challenges to car makers to ensure no security compromises as well as proving the decisions being made are functionally, behaviorally and environmentally safe. The challenge can be described in a simple question: "If a machine learning based car system is accurate 99% of the time, are you willing to ride this car knowing that it will be wrong 1% of the time? What is the consequence of that incorrect decision?" Deep expertise and research in the safety and security aspects of AI are needed to ensure future mass deployment and success in the area of autonomous driving.
In this paper, we present a comprehensive high-level synthesis system that is geared towards redu... more In this paper, we present a comprehensive high-level synthesis system that is geared towards reducing power consumption in control-flow intensive circuits. An iterative improvement algorithm is at the heart of the system. The algorithm searches the design space by handling scheduling, module selection, resource sharing and multiplexer network restructuring simultaneously. The scheduler performs concurrent loop optimization and implicit loop unrolling. It minimizes the expected number of cycles of the schedule without compromising on the minimum and maximum schedule lengths. A fast simulation technique based on trace manipulation aids power estimation in driving synthesis in the right direction. Experimental results demonstrate power reduction of up to 85% with minimal overhead in area over areaoptimized designs operating at 5V.
2009 Design, Automation & Test in Europe Conference & Exhibition, 2009
Memories are increasingly dominating Systems on Chip (SoC) designs and thus contribute a large pe... more Memories are increasingly dominating Systems on Chip (SoC) designs and thus contribute a large percentage of the total system's power dissipation, area and reliability. In this paper, we present a tool which captures the effects of supply voltage V dd and temperature on memory performance and their interrelationships. We propose a Temperature-and Reliability-Aware Memory Design (TRAM) approach which allows designers to examine the effects of frequency, supply voltage, power dissipation, and temperature on reliability in a mutually interrelated manner. Our experimental results indicate that thermal unaware estimation of probability of error can be off by at least two orders of magnitude and up to five orders of magnitude from the realistic, temperature-aware cases. We also observed that thermal aware V dd selection using TRAM can reduce the total power dissipation by up to 2.5X while attaining an identical predefined limit on errors.
There is a growing need for accurate power models at the system level. Memory structures such as ... more There is a growing need for accurate power models at the system level. Memory structures such as caches, Branch Target Buffers (BTBs), and register files occupy significant area in contemporary SoC designs and are the main contributors to system leakage power dissipation. Existing models for leakage power estimation in array structures typically use coefficients derived from elaborate SPICE simulations. However, these methodologies are not applicable to array designs in a newer technology, that require power estimates early in the design cycle. In this paper, we propose analytical models for array structures that are based only on high level design parameters. Assuming typical circuit implementation styles, we identify the transistors that contribute to the leakage power in each array sub-circuit and develop models as a function of the operation (read/write/idle) on the array and organizational parameters of the array. The developed models are validated by comparing their estimates ...
2008 IEEE International Symposium on VLSI Design, Automation and Test (VLSI-DAT), 2008
ABSTRACT Summary form only given. Improvements in the speed and the size of chips due to process ... more ABSTRACT Summary form only given. Improvements in the speed and the size of chips due to process scaling come with the penalties of increased power densities and higher operating temperatures. Higher temperature not only poses a risk of thermal runaway of the chips but also increases leakage-power dissipation and reduces interconnect lifetime. Furthermore, the floorplan of a System-on-a-Chip (SoC) has a significant impact on the temperature profile and leakage power, requiring early analysis of the SoC temperature profiles. We will talk about a system level leakage estimation methodology that considers the floorplan of the SoC and also the positive feedback relation between temperature and leakage power. We also talk about a system-level Leakage-Aware Floorplanner (LEAF) that optimizes floorplans for temperature-aware leakage power along with the traditional metric of area. We observed up to 190% difference in the leakage power between leakage-unaware and leakage-aware floorplanning. Temperature also has a serious effect on the Mean Time to Failure (MTF) of interconnects because of electromigration. To address this issue, we have developed a Temperature Aware Global Router (TAGORE) that reduces the probability of chip failure due to interconnect failures. TAGORE achieves a reduction in the probability of failure by routing more wires in the colder regions of the chip and fewer wires in the hotter regions of the chip. We observed that TAGORE reduced the number of wires in the hottest region of a chip by up to 19.95% and by an average of 12.29%. This resulted in a decrease in the failure rate by up to 292 failures per million hours of operation. This approach to reliability improvement does not require any addition of redundant wires or vias. We also have an analytical examination of the reduction in the probability of interconnect failure and the failure rate due to temperature aware global routing.
Proceedings of the 2nd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis - CODES+ISSS '04, 2004
There is a growing need for accurate power models at the system level. Memory structures such as ... more There is a growing need for accurate power models at the system level. Memory structures such as caches, Branch Target Buffers (BTBs), and register files occupy significant area in contemporary SoC designs and are the main contributors to system leakage power dissipation. Existing models for leakage power estimation in array structures typically use coefficients derived from elaborate SPICE simulations. However, these methodologies are not applicable to array designs in a newer technology, that require power estimates early in the design cycle. In this paper, we propose analytical models for array structures that are based only on high level design parameters. Assuming typical circuit implementation styles, we identify the transistors that contribute to the leakage power in each array sub-circuit and develop models as a function of the operation (read/write/idle) on the array and organizational parameters of the array. The developed models are validated by comparing their estimates against the leakage power measured using SPICE simulations on industrial array designs belonging to the e500 1 processor core. The comparison shows that the models are accurate with an error margin of less than 21.5% and thus can be used in high-level power-performance exploration. Interestingly, in array designs with dual threshold voltage technology, we observed that contrary to the general expectation, the array memory core contributes to just 9% and the address decoder contributes to as much as 62% of the total leakage power.
Proceedings of the 1998 international symposium on Low power electronics and design - ISLPED '98, 1998
Page 1. Fast High-level Power Estimation for Control-flow Intensive Designs Kamal S. Khouri, Gane... more Page 1. Fast High-level Power Estimation for Control-flow Intensive Designs Kamal S. Khouri, Ganesh Lakshminarayana, and Niraj K. Jha Department of Electrical Engineering Princeton University, Princeton, NJ 08544 Abstract ...
In this paper, we present a novel scheduling algorithm targeted towards minimizing the average ex... more In this paper, we present a novel scheduling algorithm targeted towards minimizing the average execution time of control-flow intensive behavioral descriptions. Our algorithm uses a control-data flow graph (CDFG) model, which preserves the parallelism inherent in the application. It explores previously unexplored regions of the solution space through its ability to overlap the schedules of independent iterative constructs, whose bodies share resources. It also incorporates well-known optimization techniques like loop unrolling in a natural fashion. This is made possible by a general loop-handling technique, which we have devised. Application of the algorithm to several common benchmarks demonstrates up to 4.8-fold improvement in expected schedule length over existing scheduling algorithms, without paying a price in terms of the bestand worst-case schedule lengths required to execute the behavioral description (in fact, frequently, the best/worst-case schedule lengths are also better for our algorithm).
This paper presents a design methodology, called common-case com- putation (CCC), and new design ... more This paper presents a design methodology, called common-case com- putation (CCC), and new design automation algorithms for optimiz- ing power consumption or performance. The proposed techniques are applicable in conjunction with any high-level design methodol- ogy where a structural register-transfer level (RTL) descr iption and its corresponding scheduled behavioral (cycle-accurate f unctional RTL) description are available. It is a well-known
Proceedings of the 36th ACM/IEEE conference on Design automation conference - DAC '99, 1999
This paper presents a design methodology, called common-case com- putation (CCC), and new design ... more This paper presents a design methodology, called common-case com- putation (CCC), and new design automation algorithms for optimiz- ing power consumption or performance. The proposed techniques are applicable in conjunction with any high-level design methodol- ogy where a structural register-transfer level (RTL) descr iption and its corresponding scheduled behavioral (cycle-accurate f unctional RTL) description are available. It is a well-known
This paper presents a design methodology, called common-case com- putation (CCC), and new design ... more This paper presents a design methodology, called common-case com- putation (CCC), and new design automation algorithms for optimiz- ing power consumption or performance. The proposed techniques are applicable in conjunction with any high-level design methodol- ogy where a structural register-transfer level (RTL) descr iption and its corresponding scheduled behavioral (cycle-accurate f unctional RTL) description are available. It is a well-known
20th International Conference on VLSI Design held jointly with 6th International Conference on Embedded Systems (VLSID'07), 2007
In this paper we demonstrate the impact of the floorplan on the temperature-dependent leakage pow... more In this paper we demonstrate the impact of the floorplan on the temperature-dependent leakage power of a System on Chip (SoC). We propose a novel system level temperature aware and floorplan aware leakage power estimator, STEFAL, which considers both the floorplan of the SoC and the cycle-by-cycle dynamic power behavior while estimating the leakage power. We implemented our estimation methodology on ten industrial SoC designs from Freescale Semiconductor Inc. and observed up to a 190% difference in the leakage power between various floorplans, clearly showing the importance of considering the floorplans and the temperature profile during leakage power estimation.
2008 14th International Workshop on Thermal Inveatigation of ICs and Systems, 2008
Increased operating temperatures of chips have aggravated leakage and reliability issues, both of... more Increased operating temperatures of chips have aggravated leakage and reliability issues, both of which are adversely affected by high temperature. Due to thermal diffusion among IP-blocks and the interdependence of temperature and leakage power, we observe that the floorplan has an impact on both the temperatures and the leakage of the IP-blocks in a System on Chip (SoC). An increase in temperature also increases the probability of errors such as read/write errors or unstable memory accesses. In a thermal unaware paradigm, SRAM designers increase (overdrive) the supply voltage (V dd ) to increase their reliability. However, increasing V dd in turn increases the memory's leakage and dynamic power dissipation and its temperature is elevated. Thus V dd , power, temperature, and probability of errors influence each other mutually and must be considered during SRAM design. This paper addresses two issues: (i) we propose a novel system level Leakage Aware Floorplanner which optimizes floorplans for thermal-aware leakage power along with the traditional metrics of area and wire length; and (ii) we demonstrate the effect of temperature on the probability of errors of SRAM memories which helps designers select a thermal-aware operating voltage for SRAMs. We will also discuss temperatureā‡”leakage positive feedback loop. We applied our floorplanner on eight industrial SoC designs from Freescale Semiconductor Inc. and we observed up to 135% difference in the leakage power between leakage-unaware and leakage aware floorplanning. In this paper we also quantify the effect of temperature on the probability of failures in memories. We observed that by considering the effect of temperature on memories, reducing V dd can help improve both the reliability and the power dissipation. For a predefined limit on reliability, thermal aware V dd selection can reduce the total power dissipation by up to 2.5X.
2009 International Symposium on VLSI Design, Automation and Test, 2009
In current Systems-on-Chip (SoC) designs, managing peak temperature is critical to ensure operati... more In current Systems-on-Chip (SoC) designs, managing peak temperature is critical to ensure operation without failure. Our novel Communication Architecture Based Thermal Management (CBTM) scheme manages thermal behavior of components by delaying the execution of chosen IP-blocks or components by regulating the flow of data over the on-chip communication bus. This temperature aware traffic flow over the bus is achieved by dynamically changing the communication priority table in response to thermal readings from sensors. With CBTM, the temperatures of individual components can be controlled selectively. In this paper we demonstrate the effectiveness of CBTM on four industrial size SoC designs and also evaluate its performance impact. We observe that CBTM maintained thermal thresholds and reduced the peak temperature of an SoC by as much as 29 o C.
9th International Symposium on Quality Electronic Design (isqed 2008), 2008
In this paper we propose thermal aware global routing of interconnects which reduces the probabil... more In this paper we propose thermal aware global routing of interconnects which reduces the probability of failure of chips due to interconnect failures. Temperature has a very serious effect on the mean time to failure (MTF) of interconnects because of electromigration. We present TAGORE, a thermal aware global router. TAGORE achieves a reduction in the probability of failure by routing
2007 Asia and South Pacific Design Automation Conference, 2007
Process scaling and higher leakage power have resulted in increased power densities and elevated ... more Process scaling and higher leakage power have resulted in increased power densities and elevated die temperatures. Due to the interdependence of temperature and leakage power, we observe that the floorplan has an impact on both the temperatures and the leakage of the IP-blocks in a system on chip (SoC). Hence, in this paper we propose a novel system level Leakage Aware Floorplanner (LEAF) which optimizes floorplans for temperature-aware leakage power along with the traditional metrics of area and wire length. Our floorplanner takes a SoC netlist and the dynamic power profile of functional blocks to determine a placement while optimizing for temperature dependent leakage power, area, and wire length. To demonstrate the effectiveness of LEAF, we implemented our methodology on ten industrial SoC designs from Freescale Semiconductor Inc. and evaluated the trade-off between leakage power and area. We observed up to 190% difference in the leakage power between leakage-unaware and leakage aware floorplanning.
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Papers by Kamal Khouri