2015 IEEE 17th International Conference on High Performance Computing and Communications, 2015 IEEE 7th International Symposium on Cyberspace Safety and Security, and 2015 IEEE 12th International Conference on Embedded Software and Systems, 2015
2015 IEEE 17th International Conference on High Performance Computing and Communications, 2015 IEEE 7th International Symposium on Cyberspace Safety and Security, and 2015 IEEE 12th International Conference on Embedded Software and Systems, 2015
2015 IEEE 17th International Conference on High Performance Computing and Communications, 2015 IEEE 7th International Symposium on Cyberspace Safety and Security, and 2015 IEEE 12th International Conference on Embedded Software and Systems, 2015
10th IEEE International Symposium on Object and Component-Oriented Real-Time Distributed Computing (ISORC'07), 2007
Reconfigurable devices, such as Field Programmable Gate Arrays (FPGAs), are very popular in today... more Reconfigurable devices, such as Field Programmable Gate Arrays (FPGAs), are very popular in today's embedded systems design due to their low-cost, high-performance and flexibility. Partially Runtime-Reconfigurable (PRTR) FPGAs allow hardware tasks to be placed and removed dynamically at runtime. Hardware task scheduling on PRTR FPGAs brings many challenging issues to traditional real-time scheduling theory, which have not been adequately addressed by the real-time research community compared to software task scheduling on CPUs. In this paper, we present an efficient online task placement algorithm for minimizing fragmentation on PRTR FPGAs. First, we present a novel 2D area fragmentation metric that takes into account probability distribution of sizes of future task arrivals; second, we take into the time axis to obtain a 3D fragmentation metric; third, we use a look-ahead heuristic to find a task placement in the 3D space/time coordinate system in order to minimize fragmentation. Simulation experiments indicate that our techniques result in low ratio of task rejection and high FPGA utilization compared to existing techniques.
2007 IEEE International Parallel and Distributed Processing Symposium, 2007
Reconfigurable devices, such as Field Programmable Gate Arrays (FPGAs), are very popular in today... more Reconfigurable devices, such as Field Programmable Gate Arrays (FPGAs), are very popular in today's embedded systems design due to their low-cost, high-performance and flexibility. Partially Runtime-Reconfigurable (PRTR) FPGAs allow hardware tasks to be placed and removed dynamically at runtime. Hardware task scheduling on PRTR FPGAs brings many challenging issues to traditional real-time scheduling theory, which have not been adequately addressed by the research community compared to software task scheduling on CPUs. In this paper, we consider the schedulability analysis problem of HW task scheduling on PRPR FPGAs. We derive utilization bound tests for two variants of global EDF scheduling, and use synthetic tasksets to compare performance of the tests to existing work and simulation results.
Synchronous dataflow (SDF) is a widely-used model of computation for digital signal processing an... more Synchronous dataflow (SDF) is a widely-used model of computation for digital signal processing and multimedia applications. In this letter, we propose an automatic approach to synthesize efficient software from SDF models with improved runtime efficiency. Our synthesis technique is based on dynamic single-appearance scheduling (dynSAS), which generates software with minimized code size, the same as traditional single-appearance schedule (SAS), while requires much less buffer memory space. We enhance dynSAS systematically to reduce control flow overhead and increase memory utilization. Experiment results show that our approach can generate efficient software with enhanced runtime performance compared to related techniques.
As Moore's law comes to an end, multiprocessor systems are becoming ubiquitous in today's embedde... more As Moore's law comes to an end, multiprocessor systems are becoming ubiquitous in today's embedded systems design. In this paper, we address the problem of mapping a Homogeneous Synchronous Dataflow (HSDF) graph onto a multiprocessor platform with the objective of maximizing system throughput. We present two optimization approaches based on branch-and-bound and SAT-solving to explore the design space of all possible actorto-processor mappings and static order schedules on each processor. In the Logic-Based Benders Decomposition (LBBD) approach, we decompose the problem into a master problem of finding a feasible actor mapping and scheduling, and a sub-problem of deadlock-checking and throughput computation. In the Integrated approach, we integrate branch-and-bound search into the SAT engine to achieve more effective search tree pruning and better scalability. Performance evaluation shows that the Integrated approach outperforms the LBBD approach by a large margin. reduced actor execution times will also meet the throughput or latency constraints. In this paper, we consider all actor execution times to be constant and equal to their WCETs, and do not consider or take advantage of variations in actor execution times. Therefore, self-timed scheduling amounts to fully-static scheduling with the additional property of being work-conserving, i.e., the processor should not be idle when some actor on it is ready to fire.
2009 IEEE Computer Society Annual Symposium on VLSI, 2009
Power gating induced power/ground (P/G) noise is a major reliability problem facing by low power ... more Power gating induced power/ground (P/G) noise is a major reliability problem facing by low power MPSoCs using power gating techniques. Powering on and off a processing unit in MPSoCs will induce large P/G noise and can cause timing divergence and even functional errors in surrounding processing units. P/G noise is different from thermal or energy which is an accumulative effect. The noise level should be predicted and victim circuits should be protected before the noise is induced. Hence, the power gating-aware scheduling problem with the consideration of P/G noise should be solved using an on-line method considering the run-time variation of tasks' execution time. In this paper, we formulate an on-line task scheduling problem with the consideration of P/G noise based on our detailed P/G noise analysis platform for MPSoC.
2015 IEEE 17th International Conference on High Performance Computing and Communications, 2015 IEEE 7th International Symposium on Cyberspace Safety and Security, and 2015 IEEE 12th International Conference on Embedded Software and Systems, 2015
2015 IEEE 17th International Conference on High Performance Computing and Communications, 2015 IEEE 7th International Symposium on Cyberspace Safety and Security, and 2015 IEEE 12th International Conference on Embedded Software and Systems, 2015
2015 IEEE 17th International Conference on High Performance Computing and Communications, 2015 IEEE 7th International Symposium on Cyberspace Safety and Security, and 2015 IEEE 12th International Conference on Embedded Software and Systems, 2015
10th IEEE International Symposium on Object and Component-Oriented Real-Time Distributed Computing (ISORC'07), 2007
Reconfigurable devices, such as Field Programmable Gate Arrays (FPGAs), are very popular in today... more Reconfigurable devices, such as Field Programmable Gate Arrays (FPGAs), are very popular in today's embedded systems design due to their low-cost, high-performance and flexibility. Partially Runtime-Reconfigurable (PRTR) FPGAs allow hardware tasks to be placed and removed dynamically at runtime. Hardware task scheduling on PRTR FPGAs brings many challenging issues to traditional real-time scheduling theory, which have not been adequately addressed by the real-time research community compared to software task scheduling on CPUs. In this paper, we present an efficient online task placement algorithm for minimizing fragmentation on PRTR FPGAs. First, we present a novel 2D area fragmentation metric that takes into account probability distribution of sizes of future task arrivals; second, we take into the time axis to obtain a 3D fragmentation metric; third, we use a look-ahead heuristic to find a task placement in the 3D space/time coordinate system in order to minimize fragmentation. Simulation experiments indicate that our techniques result in low ratio of task rejection and high FPGA utilization compared to existing techniques.
2007 IEEE International Parallel and Distributed Processing Symposium, 2007
Reconfigurable devices, such as Field Programmable Gate Arrays (FPGAs), are very popular in today... more Reconfigurable devices, such as Field Programmable Gate Arrays (FPGAs), are very popular in today's embedded systems design due to their low-cost, high-performance and flexibility. Partially Runtime-Reconfigurable (PRTR) FPGAs allow hardware tasks to be placed and removed dynamically at runtime. Hardware task scheduling on PRTR FPGAs brings many challenging issues to traditional real-time scheduling theory, which have not been adequately addressed by the research community compared to software task scheduling on CPUs. In this paper, we consider the schedulability analysis problem of HW task scheduling on PRPR FPGAs. We derive utilization bound tests for two variants of global EDF scheduling, and use synthetic tasksets to compare performance of the tests to existing work and simulation results.
Synchronous dataflow (SDF) is a widely-used model of computation for digital signal processing an... more Synchronous dataflow (SDF) is a widely-used model of computation for digital signal processing and multimedia applications. In this letter, we propose an automatic approach to synthesize efficient software from SDF models with improved runtime efficiency. Our synthesis technique is based on dynamic single-appearance scheduling (dynSAS), which generates software with minimized code size, the same as traditional single-appearance schedule (SAS), while requires much less buffer memory space. We enhance dynSAS systematically to reduce control flow overhead and increase memory utilization. Experiment results show that our approach can generate efficient software with enhanced runtime performance compared to related techniques.
As Moore's law comes to an end, multiprocessor systems are becoming ubiquitous in today's embedde... more As Moore's law comes to an end, multiprocessor systems are becoming ubiquitous in today's embedded systems design. In this paper, we address the problem of mapping a Homogeneous Synchronous Dataflow (HSDF) graph onto a multiprocessor platform with the objective of maximizing system throughput. We present two optimization approaches based on branch-and-bound and SAT-solving to explore the design space of all possible actorto-processor mappings and static order schedules on each processor. In the Logic-Based Benders Decomposition (LBBD) approach, we decompose the problem into a master problem of finding a feasible actor mapping and scheduling, and a sub-problem of deadlock-checking and throughput computation. In the Integrated approach, we integrate branch-and-bound search into the SAT engine to achieve more effective search tree pruning and better scalability. Performance evaluation shows that the Integrated approach outperforms the LBBD approach by a large margin. reduced actor execution times will also meet the throughput or latency constraints. In this paper, we consider all actor execution times to be constant and equal to their WCETs, and do not consider or take advantage of variations in actor execution times. Therefore, self-timed scheduling amounts to fully-static scheduling with the additional property of being work-conserving, i.e., the processor should not be idle when some actor on it is ready to fire.
2009 IEEE Computer Society Annual Symposium on VLSI, 2009
Power gating induced power/ground (P/G) noise is a major reliability problem facing by low power ... more Power gating induced power/ground (P/G) noise is a major reliability problem facing by low power MPSoCs using power gating techniques. Powering on and off a processing unit in MPSoCs will induce large P/G noise and can cause timing divergence and even functional errors in surrounding processing units. P/G noise is different from thermal or energy which is an accumulative effect. The noise level should be predicted and victim circuits should be protected before the noise is induced. Hence, the power gating-aware scheduling problem with the consideration of P/G noise should be solved using an on-line method considering the run-time variation of tasks' execution time. In this paper, we formulate an on-line task scheduling problem with the consideration of P/G noise based on our detailed P/G noise analysis platform for MPSoC.
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Papers by Weichen Liu