Lower Power 71V256SA

3.3V CMOS Fast SRAM

256K (32K x 8-Bit)

Features Description
◆
Ideal for high-performance processor secondary cache The IDT71V256SA is a 262,144-bit high-speed static RAM organized
◆
Commercial (0°C to +70°C) and Industrial (–40°C to +85°C) as 32K x 8. It is fabricated using a high-performance, high-reliability CMOS
temperature range options technology.
◆
Fast access times: The IDT71V256SA has outstanding low power characteristics while
– Commercial and Industrial: 12/15/20ns at the same time maintaining very high performance. Address access
◆
Low standby current (maximum): times of as fast as 12ns are ideal for 3.3V secondary cache in 3.3V
– 2mA full standby desktop designs.
◆
Small packages for space-efficient layouts: When power management logic puts the IDT71V256SA in standby
– 28-pin 300 mil SOJ mode, its very low power characteristics contribute to extended battery life.
– 28-pin TSOP Type I By taking CS HIGH, the SRAM will automatically go to a low power standby
◆
Produced with advanced high-performance CMOS mode and will remain in standby as long as CS remains HIGH. Further-
technology more, under full standby mode (CS at CMOS level, f=0), power consump-
◆
Inputs and outputs are LVTTL-compatible tion is guaranteed to always be less than 6.6mW and typically will be much
◆
Single 3.3V(±0.3V) power supply smaller.
◆
Industrial temperature range (–40°C to +85°C) is available The IDT71V256SA is packaged in a 28-pin 300 mil SOJ and a 28-pin
for selected speeds 300 mil TSOP Type I.
◆
Green parts available, see ordering information

Functional Block Diagram

A0 VCC

262,144 BIT GND

ADDRESS
DECODER MEMORY ARRAY

A14

I/O0
I/O CONTROL
INPUT
DATA
CIRCUIT
I/O7

CS ,
OE CONTROL
CIRCUIT 3101 drw 01
WE

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 71V256SA
3.3V CMOS Static RAM 256K (32K x 8-Bit) Commercial and Industrial Temperature Ranges

Pin Configurations(1) Truth Table(1)

WE CS OE I/O Function
A14 1 28 V CC
A12 2 27 WE X H X High-Z Standby (ISB)
A7 3 26 A13
X VHC X High-Z Standby (ISB1)
A6 4 25 A8
A5 5 24
7 1 V 2 5 6 SA
A9 H L H High-Z Output Disable
A4 6
PJ G2 8 2 3 A11
A3 7 22 OE H L L DOUT Read
A2 8 21 A10
L L X DIN Write
A1 9 20 CS
A0 10 19 I /O 7 3101 tbl 02
I /O 0 11 18 I /O 6 NOTE:
I /O 1 1. H = VIH, L = VIL, X = Don’t Care
12 17 I /O 5
I /O 2 I /O 4
Absolute Maximum Ratings(1)
13 16
GN D 14 15 I /O 3
Symbol Rating Com'l Unit
3101 drw 02

DIP/SOJ VCC Supply Voltage

Relative to GND
-0.5 to +4.6 V

Top View
VTERM(2) Terminal Voltage -0.5 to VCC+0.5 V
Relative to GND

TBIAS Temperature Under Bias -55 to +125 o

C
OE 22 21 A10
A11 23 20 CS TSTG Storage Temperature -55 to +125 o
C
A9 24 19 I/O7
A8 25 18 I/O6 PT Power Dissipation 1.0 W
A13 26 17 I/O5
WE 27
71V256SA 16 I/O4 IOUT DC Output Current 50 mA
VCC 28 PZG28 15 I/O3
A14 1 14 GND 3101 tbl 03
A12 2 13 I/O2 NOTES:
A7 3 12 I/O1 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS
A6 4 11 I/O0 may cause permanent damage to the device. This is a stress rating only and
A5 5 10 A0
A4 6 9 A1
functional operation of the device at these or any other conditions above those
A3 7 8 A2 indicated in the operational sections of this specification is not implied. Exposure
to absolute maximum rating conditions for extended periods may affect
3101 drw 03 reliability.
TSOP 2. Input, Output, and I/O terminals; 4.6V maximum.
Top View

Capacitance
NOTE:
1. This text does not indicate orientation of actual part-marking.
(TA = +25°C, f = 1.0MHz, SOJ package)
Symbol Parameter(1) Conditions Max. Unit

CIN Input Capacitance VIN = 3dV 6 pF

Pin Descriptions
COUT Output Capacitance VOUT = 3dV 7 pF
Name Description
3101 tbl 04
NOTE:
A0 - A14 Addresses
1. This parameter is determined by device characterization, but is not production
I/O0 - I/O7 Data Input/Output tested.

CS Chip Select

WE Write Enable Recommended Operating

OE Output Enable Temperature and Supply Voltage
GND Ground Grade Temperature GND Vcc

VCC Power Commercial 0OC to +70OC 0V 3.3V ± 0.3V

3101 tbl 01 Industrial -40OC to +85OC 0V 3.3V ± 0.3V
3101 tbl 05

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 71V256SA
3.3V CMOS Static RAM 256K (32K x 8-Bit) Commercial and Industrial Temperature Ranges

Recommended DC Operating
Conditions
Symbol Parameter Min. Typ. Max. Unit

VCC Supply Voltage 3.0 3.3 3.6 V

GND Ground 0 0 0 V

VIH Input High Voltage - Inputs 2.0 ____

VCC +0.3 V

VIH Input High Voltage - I/O 2.0 ____

VCC +0.3 V
(1)
VIL Input Low Voltage -0.3 ____
0.8 V
3101 tbl 06
NOTE:
1. VIL (min.) = –2.0V for pulse width less than 5ns, once per cycle.

DC Electrical Characteristics(1)
(VCC = 3.3V ± 0.3V, VLC = 0.2V, VHC = VCC - 0.2V, Commercial and Industrial Temperature Ranges)
Symbol Parameter 71V256SA12 71V256SA15 71V256SA20 Unit
ICC Dynamic Operating Current CS < V IL, Outputs 90 85 85 mA
Open, V CC = Max., f = fMAX(2)
ISB Standby Power Supply Current (TTL Level) 20 20 20 mA
CS = V IH, V CC = Max., Outputs Open, f = fMAX(2)
ISB1 Full Standby Power Supply Current (CMOS Level) 2 2 2 mA
CS > V HC, V CC = Max., Outputs Open, f = 0(2),
V IN < V LC or V IN > V HC
3101 tbl 07
NOTES:
1. All values are maximum guaranteed values.
2. fMAX = 1/tRC, only address inputs cycling at fMAX; f = 0 means that no inputs are cycling.

DC Electrical Characteristics
(VCC = 3.3V± 0.3V)
IDT71V256SA

Symbol Parameter Test Conditions Min. Typ. Max. Unit

|ILI| Input Leakage Current VCC = Max., VIN = GND to VCC ___ ___
2 µA

|ILO| Output Leakage Current VCC = Max., CS = VIH, VOUT = GND to V CC ___ ___
2 µA

VOL Output Low Voltage IOL = 8mA, VCC = Min. ___ ___
0.4 V

VOH Output High Voltage IOH = -4mA, VCC = Min. 2.4 ___ ___
V
3101 tbl 08

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3.3V CMOS Static RAM 256K (32K x 8-Bit) Commercial and Industrial Temperature Ranges

AC Test Conditions
Input Pulse Levels GND to 3.0V
Input Rise/Fall Times 3ns
Input Timing Reference Levels 1.5V
Output Reference Levels 1.5V
AC Test Load See Figures 1 and 2
3101 tbl 09

3.3V 3.3V

320Ω 320Ω
DATA OUT DATA OUT
350Ω 30pF* 350Ω
, 5pF*
,
3101 drw 04 3101 drw 05

Figure 1. AC Test Load Figure 2. AC Test Load

(for tCLZ, tOLZ, tCHZ, tOHZ, tOW, tWHZ)
*Includes scope and jig capacitances

AC Electrical Characteristics
(VCC = 3.3V ± 0.3V, Commercial and Industrial Temperature Ranges)
71V256SA12 71V256SA15 71V256SA20

Symbol Parameter Min. Max. Min. Max. Min. Max. Unit

Read Cycle
tRC Read Cycle Time 12 ____
15 ____
20 ____
ns
tAA Address Access Time ____
12 ____
15 ____
20 ns
tACS Chip Select Access Time ____
12 ____
15 ____
20 ns

tCLZ(1) Chip Select to Output in Low-Z 5 ____

5 ____
5 ____
ns

tCHZ(1) Chip Select to Output in High-Z 0 8 0 9 0 10 ns

tOE Output Enable to Output Valid ____

6 ____
7 ____
8 ns
(1) Output Enable to Output in Low-Z 3 ____
0 ____
0 ____
ns
tOLZ
(1) Output Disable to Output in High-Z 2 6 0 7 0 8 ns
tOHZ
tOH Output Hold from Address Change 3 ____
3 ____
3 ____
ns

Write Cycle
tWC Write Cycle Time 12 ____
15 ____
20 ____
ns
tAW Address Valid to End-of-Write 9 ____
10 ____
15 ____
ns
tCW Chip Select to End-of-Write 9 ____
10 ____
15 ____
ns
tAS Address Set-up Time 0 ____
0 ____
0 ____
ns
tWP Write Pulse Width 9 ____
10 ____
15 ____
ns
tWR Write Recovery Time 0 ____
0 ____
0 ____
ns
tDW Data to Write Time Overlap 6 ____
7 ____
8 ____
ns
tDH Data Hold from Write Time 0 ____
0 ____
0 ____
ns

tOW(1) Output Active from End-of-Write 4 ____

4 ____
4 ____
ns

tWHZ(1) Write Enable to Output in High-Z 1 8 1 9 1 10 ns

3101 tbl 10

NOTE:
1. This parameter guaranteed with the AC test load (Figure 2) by device characterization, but is not production tested.

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 71V256SA
3.3V CMOS Static RAM 256K (32K x 8-Bit) Commercial and Industrial Temperature Ranges

Timing Waveform of Read Cycle No. 1(1)

t RC

ADDRESS

t AA t OH

OE
t OE (2)
(2) t OHZ
t OLZ
CS
t ACS (2)
(2) t CHZ
t CLZ
DATAOUT DATA VALID
3101 drw 06 ,
NOTES:
1. WE is HIGH for Read cycle.
2. Transition is measured ±200mV from steady state.

Timing Waveform of Read Cycle No. 2(1,2,4)

t RC

ADDRESS
t AA
t OH t OH

DATAOUT PREVIOUS DATA VALID DATA VALID

3101 drw 07 ,

Timing Waveform of Read Cycle No. 3(1,3,4)

CS

t ACS (5)
t CHZ
t CLZ (5)

DATAOUT DATA VALID

3101 drw 08
,
NOTES:
1. WE is HIGH for Read cycle.
2. Device is continuously selected, CS is LOW.
3. Address valid prior to or coincident with CS transition LOW.
4. OE is LOW.
5. Transition is measured ±200mV from steady state.

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3.3V CMOS Static RAM 256K (32K x 8-Bit) Commercial and Industrial Temperature Ranges

Timing Waveform of Write Cycle No. 1 (WE Controlled Timing)(1,2,4,6)

t WC

ADDRESS
(5)
t OHZ

OE

t AW

CS

t AS t WP (6) t WR

WE

t WHZ (5)
t OW (5)

DATAOUT (3) (3)

t DW t DH

DATAIN DATA VALID

3101 drw 09 ,
NOTES:
1. A write occurs during the overlap of a LOW CS and a LOW WE.
2. tWR is measured from the earlier of CS or WE going HIGH to the end of the write cycle.
3. During this period, I/O pins are in the output state so that the input signals must not be applied.
4. If the CS LOW transition occurs simultaneously with or after the WE LOW transition, the outputs remain in a high-impedance state.
5. Transition is measured ±200mV from steady state.
6. If OE is LOW during a WE controlled write cycle, the write pulse width must be the larger of tWP or (tWHZ + tDW) to allow the I/O drivers to turn off and data to be
placed on the bus for the required tDW. If OE is HIGH during a WE controlled write cycle, this requirement does not apply and the write pulse can be as short as the
specified tWP.

Timing Waveform of Write Cycle No. 2 (CS Controlled Timing)(1,2,3,4)

t WC

ADDRESS
t AW

CS
(5)
tAS t CW tWR
WE

t DW t DH

DATAIN DATA VALID

3101 drw 10 ,
NOTES:
1. WE or CS must be HIGH during all address transitions.
2. A write occurs during the overlap of a LOW CS and a LOW WE.
3. tWR is measured from the earlier of CS or WE going HIGH to the end of the write cycle.
4. If the CS LOW transition occurs simultaneously with or after the WE LOW transition, the outputs remain in a high-impedance state.
5. If OE is LOW during a WE controlled write cycle, the write pulse width must be the larger of tWP or (tWHZ + tDW) to allow the I/O drivers to turn off and data to be
placed on the bus for the required tDW. If OE is HIGH during a WE controlled write cycle, this requirement does not apply and the write pulse can be as short as the
specified tWP.

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 71V256SA
3.3V CMOS Static RAM 256K (32K x 8-Bit) Commercial and Industrial Temperature Ranges

Ordering Information
71V256 SA XX X X X X
Device Power Speed Package Process/
Type Temperature
Range
Blank Tube or Tray
8 Tape & Reel

Blank Commercial (0°C to +70°C)

I(1) Industrial (–40°C to +85°C)

G Green

Y 300 mil SOJ (PJG28)

PZ TSOP Type I (PZG28)

12
15 Speed in nanoseconds
20*

* Available in TSOP package only.

3101 drw 11
NOTE:
1. Contact your local sales office for industrial temp. range for other speeds, packages and powers.

Orderable Part Information

Speed Pkg. Pkg. Temp.
Orderable Part ID
(ns) Code Type Grade
12 71V256SA12PZG PZG28 TSOP C
71V256SA12PZG8 PZG28 TSOP C
71V256SA12PZGI PZG28 TSOP I
71V256SA12PZGI8 PZG28 TSOP I
71V256SA12YG PJG28 SOJ C
71V256SA12YG8 PJG28 SOJ C
71V256SA12YGI PJG28 SOJ I
71V256SA12YGI8 PJG28 SOJ I
15 71V256SA15PZG PZG28 TSOP C
71V256SA15PZG8 PZG28 TSOP C
71V256SA15PZGI PZG28 TSOP I
71V256SA15PZGI8 PZG28 TSOP I
71V256SA15YG PJG28 SOJ C
71V256SA15YG8 PJG28 SOJ C
71V256SA15YGI PJG28 SOJ I
71V256SA15YGI8 PJG28 SOJ I
20 71V256SA20PZG PZG28 TSOP C
71V256SA20PZG8 PZG28 TSOP C
71V256SA20PZGI PZG28 TSOP I
71V256SA20PZGI8 PZG28 TSOP I

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 71V256SA
3.3V CMOS Static RAM 256K (32K x 8-Bit) Commercial and Industrial Temperature Ranges

Datasheet Document History

1/7/00 Updated to new format
Pg. 1, 3, 4, 7 Expanded Industrial Temperature offerings
Pg. 1, 2, 7 Removed 28-pin 300 mil plastic DIP package offering
Pg. 6 Removed Note No. 1 from Write Cycle No. 1 diagram; renumbered notes and footnotes
Pg. 7 Revised Ordering Information
Pg. 8 Added Datasheet Document History
08/09/00 Not recommended for new designs
02/01/01 Removed "Not recommended for new designs"
06/21/02 Pg. 7 Added tape and reel option to the ordering information
01/30/04 Pg. 7 Added "restricted hazardous substance device" to order information.
02/20/09 Pg. 7 Removed "IDT" from ordering parts
06/11/12 Pg. 3 Corrected Recommended DC Operation Conditions Max VIH from 5.0 to Vcc+0.3V
Pg. 7 Added Green designator to ordering information
Pg. 7 Corrected footnote in the ordering information from "available in SOJ package only" to
"available in TSOP package only"
07/24/14 Pg.7 Added tube or tray to the ordering information
08/18/15 Pg.1 & 7 Removed commercial 10ns speed offering & added green parts available to features
Pg.2 & 7 Removed "-X"extensions from all pin configurations SOJ28 & TSOP28
Pg. 3 & 4 Removed commercial 10ns speed offering columns from the DC & AC Elec tables
Pg.7 Updated the Industrial and Green footnotes in the Ordering Information
06/02/20 Pg.1 - 9 Rebranded as Renesas datasheet
Pg.2 & 7 Updated package codes
Pg.7 Added Orderable Part Information

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