CAT28F010 Licensed Intel

1 Megabit CMOS Flash Memory second source

FEATURES
■ Fast Read Access Time: 70/90/120 ns ■ Commercial, Industrial and Automotive
■ Low Power CMOS Dissipation:
Temperature Ranges
–Active: 30 mA max (CMOS/TTL levels) ■ On-Chip Address and Data Latches
–Standby: 1 mA max (TTL levels) ■ JEDEC Standard Pinouts:
–Standby: 100 µA max (CMOS levels) –32-pin DIP
■ High Speed Programming: –32-pin PLCC
–10 µs per byte –32-pin TSOP (8 x 20)
–2 Sec Typ Chip Program ■ 100,000 Program/Erase Cycles
■ 0.5 Seconds Typical Chip-Erase ■ 10 Year Data Retention
■ 12.0V ± 5% Programming and Erase Voltage ■ Electronic Signature
■ Stop Timer for Program/Erase

DESCRIPTION
The CAT28F010 is a high speed 128K x 8-bit electrically using a two write cycle scheme. Address and Data are
erasable and reprogrammable Flash memory ideally latched to free the I/O bus and address bus during the
suited for applications requiring in-system or after-sale write operation.
code updates. Electrical erasure of the full memory
The CAT28F010 is manufactured using Catalyst’s ad-
contents is achieved typically within 0.5 second.
vanced CMOS floating gate technology. It is designed
It is pin and Read timing compatible with standard to endure 100,000 program/erase cycles and has a data
EPROM and E2PROM devices. Programming and retention of 10 years. The device is available in JEDEC
Erase are performed through an operation and verify approved 32-pin plastic DIP, 32-pin PLCC or 32-pin
algorithm. The instructions are input via the I/O bus, TSOP packages.

I/O0–I/O7
BLOCK DIAGRAM

I/O BUFFERS
ERASE VOLTAGE
SWITCH

WE COMMAND DATA SENSE

PROGRAM VOLTAGE
REGISTER CE, OE LOGIC LATCH AMP
SWITCH

CE
OE
ADDRESS LATCH

Y-GATING
Y-DECODER

A0–A16 1,048,576 BIT

MEMORY
X-DECODER ARRAY

VOLTAGE VERIFY 5108 FHD F02

SWITCH

© 2001 by Catalyst Semiconductor, Inc. Doc. No. 1019, Rev. A

Characteristics subject to change without notice 1

This datasheet has been downloaded from http://www.digchip.com at this page

CAT28F010

PIN CONFIGURATION PIN FUNCTIONS

DIP Package (P) Pin Name Type Function
VPP 1 32 VCC
A0–A16 Input Address Inputs for
A16 2 31 WE
PLCC Package (N) memory addressing
A15 3 30 N/C

VCC
VPP
A12
A15
A16

N/C
A12 4 29 A14

WE
I/O0–I/O7 I/O Data Input/Output
A7 5 28 A13
A6 6 27 A8 CE Input Chip Enable
4 3 2 1 32 31 30
A5 7 26 A9 5 29
A7 A14
A4 8 25 A11 A6 6 28 A13 OE Input Output Enable
A3 9 24 OE 7 27
A5 A8
A2 10 23 A10
A4 8 26 A9
WE Input Write Enable
A1 11 22 CE 9 25
A3 A11
A0 12 21 I/O7 10 24
VCC Voltage Supply
A2 OE
I/O0 13 20 I/O6 11 23
A1 A10 VSS Ground
I/O1 14 19 I/O5 12 22
A0 CE
I/O2 15 18 I/O4
I/O0 13 21 I/O7 VPP Program/Erase
VSS 16 17 I/O3 14 15 16 17 18 19 20
Voltage Supply
I/O1
I/O2
VSS
I/O3
I/O4
I/O5
I/O6

5108 FHD F01

5108 FHD F01
TSOP Package (Standard Pinout 8mm x 20mm) (T)

A11 1 32 OE
A9 2 31 A10
A8 3 30 CE
A13 4 29 I/O7
A14 5 28 I/O6
NC 6 27 I/O5
WE 7 26 I/O4
VCC 8 25 I/O3
VPP 9 24 VSS
A16 10 23 I/O2
A15 11 22 I/O1
A12 12 21 I/O0
A7 13 20 A0
A6 14 19 A1
A5 15 18 A2
A4 16 17 A3

TSOP Package (Reverse Pinout) (TR)

OE 1 32 A11
A10 2 31 A9
CE 3 30 A8
I/O7 4 29 A13
I/O6 5 28 A14
I/O5 6 27 NC
I/O4 7 26 WE
I/O3 8 25 VCC
VSS 9 24 VPP
I/O2 10 23 A16
I/O1 11 22 A15
I/O0 12 21 A12
A0 13 20 A7
A1 14 19 A6
A2 15 18 A5
A3 16 17 A4
5108 FHD F14

Doc. No. 1019, Rev. A

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 CAT28F010

ABSOLUTE MAXIMUM RATINGS* *COMMENT

Temperature Under Bias ................... –55°C to +95°C Stresses above those listed under “Absolute Maximum
Storage Temperature ....................... –65°C to +150°C Ratings” may cause permanent damage to the device.
These are stress ratings only, and functional operation of
Voltage on Any Pin with the device at these or any other conditions outside of those
Respect to Ground(1) ........... –2.0V to +VCC + 2.0V listed in the operational sections of this specification is not
Voltage on Pin A9 with implied. Exposure to any absolute maximum rating for
Respect to Ground(1) ................... –2.0V to +13.5V extended periods may affect device performance and
reliability.
VPP with Respect to Ground
during Program/Erase(1) .............. –2.0V to +14.0V
VCC with Respect to Ground(1) ............ –2.0V to +7.0V
Package Power Dissipation
Capability (TA = 25°C) .................................. 1.0 W
Lead Soldering Temperature (10 secs) ............ 300°C
Output Short Circuit Current(2) ........................ 100 mA

RELIABILITY CHARACTERISTICS
Symbol Parameter Min. Max. Units Test Method
NEND (3) Endurance 100K Cycles/Byte MIL-STD-883, Test Method 1033
TDR(3) Data Retention 10 Years MIL-STD-883, Test Method 1008
VZAP(3) ESD Susceptibility 2000 Volts MIL-STD-883, Test Method 3015
ILTH(3)(4) Latch-Up 100 mA JEDEC Standard 17

CAPACITANCE TA = 25°C, f = 1.0 MHz

Limits
Symbol Test Min Max. Units Conditions
CIN (3) Input Pin Capacitance 6 pF VIN = 0V
COUT(3) Output Pin Capacitance 10 pF VOUT = 0V
CVPP (3) VPP Supply Capacitance 25 pF VPP = 0V

Note:
(1) The minimum DC input voltage is –0.5V. During transitions, inputs may undershoot to –2.0V for periods of less than 20 ns. Maximum DC
voltage on output pins is VCC +0.5V, which may overshoot to VCC + 2.0V for periods of less than 20ns.
(2) Output shorted for no more than one second. No more than one output shorted at a time.
(3) This parameter is tested initially and after a design or process change that affects the parameter.
(4) Latch-up protection is provided for stresses up to 100 mA on address and data pins from –1V to VCC +1V.

Doc. No. 1019, Rev. A

3
CAT28F010

D.C. OPERATING CHARACTERISTICS

VCC = +5V ±10%, unless otherwise specified.

Limits
Symbol Parameter Min. Max. Unit Test Conditions
ILI Input Leakage Current ±1 µA VIN = VCC or VSS
VCC = 5.5V, OE = VIH
ILO Output Leakage Current ±1 µA VOUT = VCC or VSS,
VCC = 5.5V, OE = VIH
ISB1 VCC Standby Current CMOS 100 µA CE = VCC ±0.5V,
VCC = 5.5V
ISB2 VCC Standby Current TTL 1 mA CE = VIH, VCC = 5.5V
ICC1 VCC Active Read Current 30 mA VCC = 5.5V, CE = VIL,
IOUT = 0mA, f = 6 MHz
ICC2(1) VCC Programming Current 15 mA VCC = 5.5V,
Programming in Progress
ICC3(1) VCC Erase Current 15 mA VCC = 5.5V,
Erasure in Progress
ICC4(1) VCC Prog./Erase Verify Current 15 mA VCC = 5.5V, Program or
Erase Verify in Progress
IPPS VPP Standby Current ±10 µA VPP = VPPL
IPP1 VPP Read Current 200 µA VPP = VPPH
IPP2(1) VPP Programming Current 30 mA VPP = VPPH,
Programming in Progress
IPP3(1) VPP Erase Current 30 mA VPP = VPPH,
Erasure in Progress
IPP4(1) VPP Prog./Erase Verify Current 5 mA VPP = VPPH, Program or
Erase Verify in Progress
VIL Input Low Level TTL –0.5 0.8 V
VILC Input Low Level CMOS –0.5 0.8 V
VOL Output Low Level 0.45 V IOL = 5.8mA, VCC = 4.5V
VIH Input High Level TTL 2 VCC+0.5 V
VIHC Input High Level CMOS VCC*0.7 VCC+0.5 V
VOH1 Output High Level TTL 2.4 V IOH = –2.5mA, VCC = 4.5V
VOH2 Output High Level CMOS VCC–0.4 V IOH = –400µA, VCC = 4.5V
VID A9 Signature Voltage 11.4 13 V A9 = VID
IID(1) A9 Signature Current 200 µA A9 = VID
VLO VCC Erase/Prog. Lockout Voltage 2.5 V
Note:
(1) This parameter is tested initially and after a design or process change that affects the parameter.

Doc. No. 1019, Rev. A

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 CAT28F010

SUPPLY CHARACTERISTICS
Limits
Symbol Parameter Min Max. Unit
VCC VCC Supply Voltage 4.5 5.5 V
VPPL VPP During Read Operations 0 6.5 V
VPPH VPP During Read/Erase/Program 11.4 12.6 V

A.C. CHARACTERISTICS, Read Operation

VCC = +5V ±10%, unless otherwise specified.

28F010-70(8) 28F010-90(7) 28F010-12(7)

JEDEC Standard
Symbol Symbol Parameter Min. Max. Min. Max. Min. Max. Unit
tAVAV tRC Read Cycle Time 70 90 120 ns
tELQV tCE CE Access Time 70 90 120 ns
tAVQV tACC Address Access Time 70 90 120 ns
tGLQV tOE OE Access Time 28 35 50 ns
tAXQX tOH Output Hold from Address 0 0 0 ns
OE/CE Change
tGLQX tOLZ(1)(6) OE to Output in Low-Z 0 0 0 ns
tELZX tLZ(1)(6) CE to Output in Low-Z 0 0 0 ns
tGHQZ tDF(1)(2) OE High to Output High-Z 20 20 30 ns
tEHQZ tDF(1)(2) CE High to Output High-Z 30 30 40 ns
tWHGL(1) - Write Recovery Time 6 6 6 µs
Before Read

Figure 1. A.C. Testing Input/Output Waveform(3)(4)(5) Figure 2. Highspeed A.C. Testing Input/Output
Waveform(3)(4)(5)
2.4 V 3.0 V
2.0 V
INPUT PULSE LEVELS REFERENCE POINTS INPUT PULSE LEVELS 1.5 V REFERENCE POINTS
0.8 V
0.45 V 0.0 V

5108 FHD F03 5108 FHD F03A

Testing Load Circuit (example) Testing Load Circuit (example)
1.3V
1.3V

1N914
1N914

3.3K
3.3K
DEVICE
OUT DEVICE
UNDER
UNDER OUT
TEST
CL = 100 pF TEST
CL = 30 pF
CL INCLUDES JIG CAPACITANCE
CL INCLUDES JIG CAPACITANCE
5108 FHD F04
5108 FHD F05
Note:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
(2) Output floating (High-Z) is defined as the state where the external data line is no longer driven by the output buffer.
(3) Input Rise and Fall Times (10% to 90%) < 10 ns.
(4) Input Pulse Levels = 0.45V and 2.4V. For High Speed Input Pulse Levels 0.0V and 3.0V.
(5) Input and Output Timing Reference = 0.8V and 2.0V. For High Speed Input and Output Timing Reference = 1.5V.
(6) Low-Z is defined as the state where the external data may be driven by the output buffer but may not be valid.
(7) For load and reference points, see Fig. 1
(8) For load and reference points, see Fig. 2

Doc. No. 1019, Rev. A

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CAT28F010

A.C. CHARACTERISTICS, Read Operation

VCC = +5V ±10%, unless otherwise specified.

28F010-70 28F010-90 28F010-12

\JEDEC Standard
Symbol Symbol Parameter Min. Max Min. Max. Min. Max. Unit
tAVAV tWC Write Cycle Time 70 90 120 ns
tAVWL tAS Address Setup Time 0 0 0 ns
tWLAX tAH Address Hold Time 40 40 40 ns
tDVWH tDS Data Setup Time 40 40 40 ns
tWHDX tDH Data Hold Time 10 10 10 ns
tELWL tCS CE Setup Time 0 0 0 ns
tWHEH tCH CE Hold Time 0 0 0 ns
tWLWH tWP WE Pulse Width 40 40 40 ns
tWHWL tWPH WE High Pulse Width 20 20 20 ns
tWHWH1(2) - Program Pulse Width 10 10 10 µs
tWHWH2(2) - Erase Pulse Width 9.5 9.5 9.5 ms
tWHGL Write Recovery Time
- Before Read 6 6 6 µs
tGHWL Read Recovery Time
- Before Write 0 0 0 µs
tVPEL - VPP Setup Time to CE 100 100 100 ns

ERASE AND PROGRAMMING PERFORMANCE (1)

28F010-55 28F010-70 28F010-90 28F010-12
Parameter Min. Typ. Max. Min. Typ. Max. Min. Typ. Max Min. Typ. Max. Unit
Chip Erase Time (3)(5) 0.5 10 0.5 10 0.5 10 0.5 10 Sec
Chip Program Time (3)(4) 2 12.5 2 12.5 2 12.5 2 12.5 Sec

Note:
(1) Please refer to Supply characteristics for the value of VPPH and VPPL. The VPP supply can be either hardwired or switched. If VPP is
switched, VPPL can be ground, less than VCC + 2.0V or a no connect with a resistor tied to ground.
(2) Program and Erase operations are controlled by internal stop timers.
(3) ‘Typicals’ are not guaranteed, but based on characterization data. Data taken at 25°C, 12.0V VPP.
(4) Minimum byte programming time (excluding system overhead) is 16 µs (10 µs program + 6 µs write recovery), while maximum is 400 µs/
byte (16 µs x 25 loops). Max chip programming time is specified lower than the worst case allowed by the programming algorithm since
most bytes program significantly faster than the worst case byte.
(5) Excludes 00H Programming prior to Erasure.

Doc. No. 1019, Rev. A

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 CAT28F010

FUNCTION TABLE(1)
Pins
Mode CE OE WE VPP I/O Notes
Read VIL VIL VIH VPPL DOUT
Output Disable VIL VIH VIH X High-Z
Standby VIH X X VPPL High-Z
Signature (MFG) VIL VIL VIH X 31H A0 = VIL, A9 = 12V
Signature (Device) VIL VIL VIH X B4H A0 = VIH, A9 = 12V
Program/Erase VIL VIH VIL VPPH DIN See Command Table
Write Cycle VIL VIH VIL VPPH DIN During Write Cycle
Read Cycle VIL VIL VIH VPPH DOUT During Write Cycle

WRITE COMMAND TABLE

Commands are written into the command register in one or two write cycles. The command register can be altered
only when VPP is high and the instruction byte is latched on the rising edge of WE. Write cycles also internally latch
addresses and data required for programming and erase operations.
Pins
First Bus Cycle Second Bus Cycle
Mode Operation Address DIN Operation Address DIN DOUT
Set Read Write X 00H Read AIN DOUT
Read Sig. (MFG) Write X 90H Read 00 31H
Read Sig. (Device) Write X 90H Read 01 B4H
Erase Write X 20H Write X 20H
Erase Verify Write AIN A0H Read X DOUT
Program Write X 40H Write AIN DIN
Program Verify Write X C0H Read X DOUT
Reset Write X FFH Write X FFH
Note:
(1) Logic Levels: X = Logic ‘Do not care’ (VIH, VIL, VPPL, VPPH)

Doc. No. 1019, Rev. A

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CAT28F010

READ OPERATIONS
Read Mode
A Read operation is performed with both CE and OE low The conventional mode is entered as a regular READ
and with WE high. VPP can be either high or low, mode by driving the CE and OE pins low (with WE high),
however, if VPP is high, the Set READ command has to and applying the required high voltage on address pin A9
be sent before reading data (see Write Operations). The while all other address lines are held at VIL.
data retrieved from the I/O pins reflects the contents of
A Read cycle from address 0000H retrieves the binary
the memory location corresponding to the state of the 17
code for the IC manufacturer on outputs I/O0 to I/O7:
address pins. The respective timing waveforms for the
read operation are shown in Figure 3. Refer to the AC CATALYST Code = 00110001 (31H)
Read characteristics for specific timing parameters.
A Read cycle from address 0001H retrieves the binary
Signature Mode code for the device on outputs I/O0 to I/O7.
The signature mode allows the user to identify the IC
28F010 Code = 1011 0100 (B4H)
manufacturer and the type of device while the device
resides in the target system. This mode can be activated Standby Mode
in either of two ways; through the conventional method
With CE at a logic-high level, the CAT28F010 is placed
of applying a high voltage (12V) to address pin A9 or by
in a standby mode where most of the device circuitry is
sending an instruction to the command register (see
disabled, thereby substantially reducing power con-
Write Operations).
sumption. The outputs are placed in a high-impedance
state.

Figure 3. A.C. Timing for Read Operation

POWER UP STANDBY DEVICE AND OUPUTS DATA VALID STANDBY POWER DOWN
ADDRESS SELECTION ENABLED

ADDRESSES ADDRESS STABLE

tAVAV (tRC)

CE (E)

tEHQZt(DF)

OE (G)
tWHGL tGHQZ (tDF)

WE (W) tGLQV (tOE)

tELQV (tCE) tAXQXt(OH)

tGLQX (tOLZ)
tELQX (tLZ)
HIGH-Z HIGH-Z
DATA (I/O) OUTPUT VALID

tAVQV (tACC)
28F010 F05

Doc. No. 1019, Rev. A

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 CAT28F010

WRITE OPERATIONS Signature Mode

An alternative method for reading device signature (see
The following operations are initiated by observing the
Read Operations Signature Mode), is initiated by writing
sequence specified in the Write Command Table.
the code 90H into the command register while keeping
Read Mode VPP high. A read cycle from address 0000H with CE and
OE low (and WE high) will output the device signature.
The device can be put into a standard READ mode by
initiating a write cycle with 00H on the data bus. The CATALYST Code = 00110001 (31H)
subsequent read cycles will be performed similar to a
standard EPROM or E2PROM Read. A Read cycle from address 0001H retrieves the binary
code for the device on outputs I/O0 to I/O7.

28F010 Code = 1011 0100 (B4H)

Figure 4. A.C. Timing for Erase Operation

VCC POWER-UP SETUP ERASE ERASE ERASING ERASE VERIFY ERASE VCC POWER-DOWN/
& STANDBY COMMAND COMMAND COMMAND VERIFICATION STANDBY

ADDRESSES
tWC tWC tWC tRC

tAS tAH

CE (E)
tCS tCH
tCH tEHQZ
tCH tCS

OE (G)
tGHWL
tWHWH2 tWHGL tDF
tWPH

WE (W)
tWP tWP tWP tOE
tDH tDH tDH tOH
tDS tDS tDS tOLZ
HIGH-Z
DATA (I/O) DATA IN DATA IN DATA IN
= 20H = 20H = A0H
tLZ VALID
DATA OUT
tCE

VCC 5.0V
0V tVPEL

VPP VPPH
VPPL
28F010 F11

Doc. No. 1019, Rev. A

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CAT28F010

Figure 5. Chip Erase Algorithm(1)

START ERASURE BUS

OPERATION COMMAND COMMENTS

APPLY VPPH VPP RAMPS TO VPPH

(OR VPP HARDWIRED)

ALL BYTES SHALL BE

PROGRAM ALL PROGRAMMED TO 00
BYTES TO 00H STANDBY
BEFORE AN ERASE
OPERATION

INITIALIZE INITIALIZE ADDRESS

ADDRESS

INITIALIZE
PLSCNT = 0 PLSCNT = PULSE COUNT

ACTUAL ERASE
WRITE ERASE
WRITE ERASE NEEDS 10ms
DATA PULSE,
= 20H
SETUP COMMAND
DATA = 20H

WRITE ERASE
WRITE ERASE DATA = 20H
COMMAND

TIME OUT 10ms WAIT

ADDRESS = BYTE TO VERIFY

WRITE ERASE ERASE 40H;
WRITE DATA = 20H;
A0H
VERIFY COMMAND VERIFY
STOPS ERASE OPERATION

TIME OUT 6µs WAIT

INCREMENT
ADDRESS
READ DATA
READ READ BYTE TO
FROM DEVICE
VERIFY ERASURE
NO

DATA = NO INC PLSCNT COMPARE OUTPUT TO FF

STANDBY
FFH? 1000 ?
= 3000 INCREMENT PULSE COUNT
YES YES

NO LAST
ADDRESS?

YES

WRITE READ DATA = 00H

COMMAND WRITE READ RESETS THE REGISTER
FOR READ OPERATION

VPP RAMPS TO VPPL

APPLY VPPL APPLY VPPL STANDBY
(OR VPP HARDWIRED)

ERASURE ERASE
COMPLETED ERROR

Note:
(1) The algorithm MUST BE FOLLOWED to ensure proper and reliable operation of the device.
5108 FHD F10

Doc. No. 1019, Rev. A

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 CAT28F010

Erase Mode Erase-Verify Mode

During the first Write cycle, the command 20H is written The Erase-verify operation is performed on every byte
into the command register. In order to commence the after each erase pulse to verify that the bits have been
erase operation, the identical command of 20H has to be erased.
written again into the register. This two-step process
ensures against accidental erasure of the memory con- Programming Mode
tents. The final erase cycle will be stopped at the rising The programming operation is initiated using the pro-
edge of WE, at which time the Erase Verify command gramming algorithm of Figure 7. During the first write
(A0H) is sent to the command register. During this cycle, cycle, the command 40H is written into the command
the address to be verified is sent to the address bus and register. During the second write cycle, the address of
latched when WE goes low. An integrated stop timer the memory location to be programmed is latched on the
allows for automatic timing control over this operation, falling edge of WE, while the data is latched on the rising
eliminating the need for a maximum erase timing speci- edge of WE. The program operation terminates with the
fication. Refer to AC Characteristics (Program/Erase) next rising edge of WE. An integrated stop timer allows
for specific timing parameters. for automatic timing control over this operation, eliminat-
ing the need for a maximum program timing specifica-
tion. Refer to AC Characteristics (Program/Erase) for
specific timing parameters.

Figure 6. A.C. Timing for Programming Operation

VCC POWER-UP SETUP PROGRAM LATCH ADDRESS PROGRAM PROGRAM VCC POWER-DOWN/
& STANDBY COMMAND & DATA VERIFY VERIFICATION STANDBY
PROGRAMMING COMMAND

ADDRESSES
tWC tWC tRC

tAS tAH

CE (E)
tCS tCH
tCH tEHQZ
tCH tCS

OE (G)
tGHWL
tWHWH1 tWHGL tDF
tWPH

WE (W)
tWP tWP tWP tOE
tDH tDH tDH tOH
tDS tDS tDS tOLZ
HIGH-Z
DATA (I/O) DATA IN DATA IN DATA IN
= 40H = C0H
tLZ VALID
DATA OUT
tCE

5.0V
VCC
0V tVPEL

VPPH
VPP
VPPL
28F010 F08

Doc. No. 1019, Rev. A

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CAT28F010

Figure 7. Programming Algorithm(1)

START BUS
PROGRAMMING OPERATION COMMAND COMMENTS

APPLY VPPH VPP RAMPS TO VPPH

STANDBY
(OR VPP HARDWIRED)

INITIALIZE
ADDRESS INITIALIZE ADDRESS

PLSCNT = 0 INITIALIZE PULSE COUNT

PLSCNT = PULSE COUNT

WRITE SETUP 1ST WRITE WRITE

PROG. COMMAND DATA = 40H
CYCLE SETUP

WRITE PROG. CMD 2ND WRITE PROGRAM VALID ADDRESS AND DATA
ADDR AND DATA CYCLE

TIME OUT 10µs WAIT

WRITE PROGRAM 1ST WRITE PROGRAM

DATA = C0H
VERIFY COMMAND CYCLE VERIFY

TIME OUT 6µs WAIT

READ DATA READ READ BYTE TO VERIFY

FROM DEVICE PROGRAMMING

NO

NO INC
VERIFY STANDBY COMPARE DATA OUTPUT
PLSCNT
DATA ? TO DATA EXPECTED
= 25 ?
YES YES

INCREMENT NO LAST
ADDRESS ADDRESS?

YES
DATA = 00H
WRITE READ 1ST WRITE
READ SETS THE REGISTER FOR
COMMAND CYCLE READ OPERATION

APPLY VPPL APPLY VPPL VPP RAMPS TO VPPL

STANDBY
(OR VPP HARDWIRED)

PROGRAMMING PROGRAM
COMPLETED ERROR
Note:
(1) The algorithm MUST BE FOLLOWED to ensure proper and reliable operation of the device.
5108 FHD F06

Doc. No. 1019, Rev. A

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 CAT28F010

Program-Verify Mode POWER UP/DOWN PROTECTION

A Program-verify cycle is performed to ensure that all
The CAT28F010 offers protection against inadvertent
bits have been correctly programmed following each
programming during VPP and VCC power transitions.
byte programming operation. The specific address is
When powering up the device there is no power-on
already latched from the write cycle just completed, and
sequencing necessary. In other words, VPP and VCC
stays latched until the verify is completed. The Program-
may power up in any order. Additionally VPP may be
verify operation is initiated by writing C0H into the
hardwired to VPPH independent of the state of VCC and
command register. An internal reference generates the
any power up/down cycling. The internal command
necessary high voltages so that the user does not need
register of the CAT28F010 is reset to the Read Mode on
to modify VCC. Refer to AC Characteristics (Program/
power up.
Erase) for specific timing parameters.

Abort/Reset POWER SUPPLY DECOUPLING

An Abort/Reset command is available to allow the user
to safely abort an erase or program sequence. Two To reduce the effect of transient power supply voltage
consecutive program cycles with FFH on the data bus spikes, it is good practice to use a 0.1µF ceramic
will abort an erase or a program operation. The abort/ capacitor between VCC and VSS and VPP and VSS. These
reset operation can interrupt at any time in a program or high-frequency capacitors should be placed as close as
erase operation and the device is reset to the Read possible to the device for optimum decoupling.
Mode.

Figure 8. Alternate A.C. Timing for Program Operation

VCC POWER-UP SETUP PROGRAM LATCH ADDRESS PROGRAM PROGRAM VCC POWER-DOWN/
& STANDBY COMMAND & DATA VERIFY VERIFICATION STANDBY
PROGRAMMING COMMAND

ADDRESSES
tWC tWC tRC

tAVEL tELAX

WE (W)
(E)
tWLEL tEHWH
tWLEL tEHWH tEHQZ
tEHWH tWLEL

OE (G)
tGHEL tEHEH tEHGL tDF
tEHEL

CE (E)
(W)
tELEH tELEH tOE
tEHDX tEHDX tEHDX tOH
tDVEH tDVEH tDVEH tOLZ
HIGH-Z
DATA (I/O) DATA IN DATA IN DATA IN
= 40H = C0H
tLZ VALID
DATA OUT
tCE
5.0V
VCC
0V tVPEL

VPPH
VPP
VPPL
28F010 F10

Doc. No. 1019, Rev. A

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CAT28F010

A.C. CHARACTERISTICS, Read Operation

VCC = +5V ±10%, unless otherwise specified.

28F010-70 28F010-90 28F010-12

JEDEC Standard
Symbol Symbol Parameter Min. Max Min. Max Min. Max. Unit
tAVAV tWC Write Cycle Time 70 90 120 ns
tAVEL tAS Address Setup Time 0 0 0 ns
tELAX tAH Address Hold Time 40 40 40 ns
tDVEH tDS Data Setup Time 40 40 40 ns
tEHDX tDH Data Hold Time 10 10 10 ns
tEHGL Write Recovery Time
- Before Read 0 0 0 µs
tGHEL Read Recovery Time
- Before Write 0 0 0 µs
tWLEL tWS WE Setup time Before CE 0 0 0 ns
tEHWH - WE Hold Time After CE 0 0 0 ns
tELEH tCP Write Pulse Width 40 40 40 ns
tEHEL tCPH Write Pulse Width High 20 20 20 ns
tVPEL - VPP Setup Time to CE Low 100 100 100 ns

ORDERING INFORMATION
Prefix Device # Suffix

CAT 28F010 N I -90 T

Product Temperature Range Tape & Reel

Number Blank = Commercial (0˚C to +70˚C) T: 500/Reel
I = Industrial (-40˚C to +85˚C)
A = Automotive (-40˚C to +105˚C)*

Optional Package Speed

Company ID N: PLCC 70: 70ns
P: PDIP 90: 90ns
T: TSOP (8mmx20mm) 12: 120ns
TR: TSOP (Reverse Pinout)
28F010 F12
* -40˚ to +125˚ is available upon request.
Note:
(1) The device used in the above example is a CAT28F010NI-90T(PLCC, Industrial Temperature, 90 ns access time, Tape & Reel).

Catalyst Semiconductor, Inc.

Corporate Headquarters
1250 Borregas Avenue
Sunnyvale, CA 94089 Publication #: 1019
Phone: 408.542.1000 Revison: A
Fax: 408.542.1200 Issue date: 09/27/01
www.catalyst-semiconductor.com
Doc. No. 1019, Rev. A
Type: Final
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