UVEPROM

SMJ27C256
Austin Semiconductor, Inc.
256K UVEPROM PIN ASSIGNMENT
UV Erasable Programmable (Top View)
Read-Only Memory 32-Pin DIP (J)
(600 MIL)
AVAILABLE AS MILITARY
VPP 1 28 Vcc
SPECIFICATIONS A12 2 27 A14
A7 3 26 A13
• SMD 5962-86063 A6 4 25 A8
• MIL-STD-883 A5 5 24 A9
A4 6 23 A11
A3 7 22 G\
A2 8 21 A10
FEATURES A1 9 20 E\
A0 10 19 DQ7
• Organized 32,768 x 8 DQ0 11 18 DQ6
12 17 DQ5
• Single +5V ±10% power supply DQ1
DQ2 13 16 DQ4
• Pin-compatible with existing 256K ROM’s and GND 14 15 DQ3

EPROM’s
• All inputs/outputs fully TTL compatible Pin Name Function
• Power-saving CMOS technology A0 - A14 Address Inputs
• Very high-speed SNAP! Pulse Programming DA0-DQ7 Inputs (programming)/Outputs
• 3-state output buffers E\ Chip Enable/Power Down
• 400-mV DC assured noise immunity with standarad G\ Output Enable
GND Ground
TTL loads
VCC 5V Supply
• Latchup immunity of 250 mA on all input and output
pins VPP 13V Programming Power Supply
• Low power dissipation (CMOS Input Levels)
PActive - 165mW Worst Case
PStandby - 1.7mW Worst Case (CMOS-input levels) GENERAL DESCRIPTION
The SMJ27C256 series is a set of 262,144 bit, ultraviolet-
light erasable, electrically programmable read-only
OPTIONS MARKING memories. These devices are fabricated using power-saving
• Timing
CMOS technology for high speed and simple interface with
150ns access -15
MOS and bipolar circuits. All inputs (including program data
170ns access -17
inputs) can be driven by Series 54 TTL circuits without the
200ns access -20
use of external pullup resistors. Each output can drive one
250ns access -25
Series 54 TTL circuit without external resistors. The data
300ns access -30
outputs are 3-state for connecting multiple devices to a
common bus. The SMJ27C256 is pin-compatible with
• Package(s)
28-pin 256K ROMs and EPROMs. It is offered in a 600mil
Ceramic DIP (600mils) J No. 110
dual-in-line ceramic pagackage (J suffix) rated for operation
from -55°C to 125°C.
• Operating Temperature Ranges
Because this EPROM operates from a single 5V supply (in
Military (-55oC to +125oC) M
the read mode), it is ideal for use in microprocessor-based
systems. One other supply (13V) is needed for programming.
All programming signals are TTL level. This device is
For more products and information programmable by the SNAP! Pulse programming algorithm.
The SNAP! Pulse programming algorithm uses a VPP of 13V
please visit our web site at
and a VCC of 6.5V for a nominal programming time of four
www.austinsemiconductor.com
seconds. For programming outside the system, existing
EPROM programmers can be used. Locations can be
programmed singly, in blocks, or at random.

SMJ27C256 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
Rev. 1.0 9/01
1
 UVEPROM
SMJ27C256
Austin Semiconductor, Inc.

FUNCTIONAL BLOCK DIAGRAM*

EPROM 32,768 x 8
10 0
A0
A1 9
8
A2
7
A3
6
A4
5 11
A5 A DQ0
4 12
A6 A DQ1
3 13
A7 A DQ2
25 15
A8 0 A DQ3
24 A 16
A9 32,767 A DQ4
21 17
A10 A DQ5
23 18
A11 A DQ6
2 19
A12 A DQ7
26
A13
27 14
A14
E\ 20 [PWR DWN]
&
22
G\ EN

* This symbol is in accordance with ANSI/IEEE std 91-1984 and IEC Publication 617-12.

OPERATION
The seven modes of operation for the SMJ27C256 are listed in Table 1. The read mode requires a single 5V supply. All
inputs are TTL level except for VPP during programming (13V for SNAP! Pulse), and (12V) on A9 for signature mode.

TABLE 1. OPERATION MODES

MODE*
FUNCTION
OUTPUT PROGRAM
(PINS) READ STANDBY PROGRAMMING VERIFY SIGNATURE MODE
DISABLE INHIBIT
E\ (20) VIL VIL VIH VIL VIH VIH VIL
G\ (22) VIL VIH X VIH VIL X VIL
VPP (1) VCC VCC VCC VPP VPP VPP VCC
VCC (28) VCC VCC VCC VCC VCC VCC VCC
A9 (24) X X X X X X VID VID
A0 (10) X X X X X X VIL VIH
CODE
DQ0-DQ7
Data Out High-Z High-Z Data In Data Out High-Z MFG DEVICE
(11-13, 15-19)
97 04
* X can be VIL or VIH.
SMJ27C256 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
Rev. 1.0 9/01
2
 UVEPROM
SMJ27C256
Austin Semiconductor, Inc.
READ/OUTPUT DISABLE SNAP! PULSE PROGRAMMING
When the outputs of two or more SMJ27C256s are connected The SMJ27C256 EPROM is programmed by using the SNAP!
in parallel on the same bus, the output of any particular device Pulse programming algorithm as illustrated by the flowchart
in the circuit can be read with no interference from the in Figure 1. This algorithm programs the device in a nominal
competing outputs of the other devices. To read the output of time of 4 seconds. Actual programming time varies as a
the selected SMJ27C256, a low-level signal is applied to E\ function of the programmer used.
and G\. All other devices in the circuit should have their
outputs disabled by applying a high-level signal to one of these Data is presented in parallel (eight bits) on pins DQ0 to DQ7.
pins. Output data is accessed at pins DQ0 through DQ7. Once addresses and data are stable, E\ is pulsed.

LATCHUP IMMUNITY The SNAP! Pulse programming algorithm uses initial pulses
Latchup immunity on the SMJ27C256 is a minimum of 250mA of 100 microseconds (µs) followed by a byte-verification step
on all inputs and outputs. This feature provides latchup to determine when the addressed byte has been successfully
immunity beyond any potential transients at the printed programmed. Up to ten 100µs pulses per byte are provided
circuit board level when the EPROM is interfaced to industry before a failure is recognized.
standard TTL or MOS logic devices. Input/output layout
approach controls latchup without compromising performance The programming mode is achieved when V PP = 13V,
or packing density. VCC= 6.5V, G\ = VIH, and E\ = VIL. More than one device can
be programmed when the devices are connected in parallel.
POWER DOWN Locations can be programmed in any order. When the SNAP!
Active I CC supply current can be reduced from 25mA Pulse programming routine is completed, all bits are verified
(SMJ27C256-15 through SMJ27C256-25) to 500µA (TTL- with VCC = VPP = 5V.
level inputs) or 300µA (CMOS-level inputs) by applying a high
TTL/CMOS signal to the E\ pin. In this mode all outputs are PROGRAM INHIBIT
in the high-impedance state. Programming can be inhibited by maintaining a high-level
input on E\.
ERASURE
Before programming, the SMJ27C256 is erased by exposing PROGRAM VERIFY
the chip through the transparent lid to a high-intensity ultra- Programmed bits can be verified with VPP = 13V when
violet light (wavelength 2537 Å). EPROM erasure before
G\ = VIL, and E\ = VIH.
programming is necessary to ensure that all bits are in the
logic-high state. Logic-lows are programmed into the desired
locations. A programmed logic-low can be erased only by SIGNATURE MODE
ultraviolet light. The recommended minimum exposure dose The signature mode provides access to a binary code
(UV intensity x exposure time) is 15W•s/cm 2. A typical identifying the manufacturer and device type. This mode is
12mW/cm 2 , filterless UV lamp erases the device in activated when A9 is forced to 12V ±0.5V. Two identifier
21 minutes. The lamp should be located about 2.5cm above bytes are accessed by A0 (terminal 10); i.e., A0=VIL accesses
the chip during erasure. After erasure, all bits are in the high the manufacturer code, which is output on DQ0-DQ7; A0=VIH
state. It should be noted that normal ambient light contains accesses the device code, which is also output on DQ0-DQ7.
the correct wavelength for erasure; therefore, when using the All other addresses must be held at VIL. Each byte contains
SMJ27C256, the window should be covered with an opaque odd parity on bit DQ7. The manufacturer code for these
label. devices is 97h and the device code is 04h.

SMJ27C256 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
Rev. 1.0 9/01
3
 UVEPROM
SMJ27C256
Austin Semiconductor, Inc.

FIGURE 1. SNAP! PULSE PROGRAMMING FLOW CHART

START

Address = First Location

VCC = 6.5V, VPP = 13V Program

Mode
Program One Pulse = tW = 100µs Increment Address

Last
Address? No

Yes
Address = First Location

X=0
Program One Pulse = tW(E)PR = 100µs
No

Verify Fail
Increment
Byte X = X+1 X = 10?
Address

Interactive
Pass
Mode

Last
No
Address?

Yes Yes
VCC = VPP = 5V ± 10% Device Failed

Compare Final
All Bytes Fail Verification
to Original
Data

Pass
Device Passed

SMJ27C256 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
Rev. 1.0 9/01
4
 UVEPROM
SMJ27C256
Austin Semiconductor, Inc.
ABSOLUTE MAXIMUM RATINGS* *Stresses greater than those listed under "Absolute Maximum
Supply Voltage Range, VCC**...........................-0.6V to +7.0V Ratings" may cause permanent damage to the device. This is
Supply Voltage Range, Vpp**.........................-0.6V to +14.0V a stress rating only and functional operation of the device at
these or any other conditions above those indicated in the
Input Voltage Range, All inputs except A9**..-0.6V to +6.5V
operation section of this specification is not implied.
A9.....-0.6V to +13.5V Exposure to absolute maximum rating conditions for extended
Output Voltage Range**...............................-0.6V to VCC +1V periods may affect reliability.
Minimum Operating Free-air Temperature, TA..............-55°C ** All voltage values are with respect to GND.
Maximum Operating Case Temperature, TC...................125°C
Storage Temperature Range, Tstg.....................-65°C to 150°C

RECOMMENDED OPERATING CONDITIONS

MIN TYP MAX UNIT
1
Read Mode 4.5 5 5.5 V
VCC Supply Voltage
SNAP! Pulse programming algorithm 6.25 6.5 6.75 V
2
Read Mode VCC-0.6 V
VPP Supply Voltage
SNAP! Pulse programming algorithm 12.75 13 13.25 V
TTL inputs 2 VCC+1 V
VIH High-level input voltage
CMOS inputs VCC-0.2 VCC+1 V
TTL inputs -0.5 0.8 V
VIL Low-level input voltage
CMOS inputs -0.5 0.2 V
VID Voltage level on A9 for signature mode 11.5 13 V
TA Operating free-air temperature -55 °C
TC Operating case temperature +125 °C
NOTES:
1. VCC must be applied before or at the same time as VPP and removed after or at the same time as VPP. The deivce must not be inserted into or removed from the
board when VPP or VCC is applied.
2. VPP can be connected to VCC directly (except in the program mode). VCC supply current in this case would be ICC2 + IPP1.

ELECTRICAL CHARACTERISTICS OVER RECOMMENDED RANGES OF SUPPLY VOLTAGE AND

OPERATING FREE-AIR TEMPERATURE
1
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VOH High-level output voltage IOH = -400µA 2.4 V
VOL Low-level output voltage IOL = 2.1mA 0.4 V
II Input current (leakage) VI = 0V to 5.5V ±1 µA
IO Output current (leakage) VO = 0V to VCC ±1 µA
IPP1 VPP supply current VPP = VCC = 5.5V 10 µA
2
IPP2 VPP supply current (during program pulse) VPP = 13V 35 50 mA
TTL-Input Level VCC = 5.5V, E\=VIH 500 µA
ICC1 VCC supply current (standby)
CMOS-Input Level VCC = 5.5V, E\=VCC 300 µA
'27C256-15 E\=VIL, VCC=5.5V
'27C256-17
ICC2 VCC supply current (active) tcycle = minimum, outputs 15 25 mA
'27C256-20
'27C256-25 open

IOS Output current (leakage) 100 mA

NOTES:
1. Typical values are at TA=25°C and nominal voltages.
2. This parameter has been characterized at 25°C and is not tested.
SMJ27C256 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
Rev. 1.0 9/01
5
 UVEPROM
SMJ27C256
Austin Semiconductor, Inc.
CAPACITANCE OVER RECOMMENDED RANGES OF SUPPLY VOLTAGE AND OPERATING
FREE-AIR TEMPERATURE, f = 1MHz*
PARAMETER TEST CONDITIONS TYP** MAX UNIT
Ci Input capacitance VI = 0V 6 10 pF
Co Output capacitance VO = 0V 10 14 pF

* Capacitance measurements are made on a sample basis only.

** Typical values are at TA = 25°C and nominal voltages.

SWITCHING CHARACTERISTICS OVER RECOMMENDED RANGES OF SUPPLY VOLTAGE

AND OPERATING FREE-AIR TEMPERATURE1,2
TEST -15 -17
PARAMETER 1, 2 UNIT
CONDITIONS MIN MAX MIN MAX
ta(A) Access time from address 150 170 ns
ta(E) Access time from E\ 150 170 ns
ten(G)R Output enable time from G\ 70 70 ns
Disable time of output from G\ or E\, see Figure 2
tdis 3 0 55 0 55 ns
whichever occurs first
Output data valid time after change of
tv(A) 3 0 0 ns
address, E\, or G\, whichever occurs first

TEST -20 -25 -30

PARAMETER 1, 2 UNIT
CONDITIONS MIN MAX MIN MAX MIN MAX
ta(A) Access time from address 200 250 300 ns
ta(E) Access time from E\ 200 250 300 ns
ten(G)R Output enable time from G\ 75 100 120 ns
Disable time of output from G\ or E\, see Figure 2
tdis 3 0 60 0 60 0 105 ns
whichever occurs first
Output data valid time after change of
tv(A) 3 0 0 0 ns
address, E\, or G\, whichever occurs first
NOTES:
1.Timing measurements are made at 2V for logic high and 0.8V for logic low (see figure 2).
2. Common test conditions apply for tdis except during programming.
3. Value calculated from 0.5V delta to measured output level. This parameter is only sampled and not 100% tested.

SWITCHING CHARACTERISTICS FOR PROGRAMMING: VCC = 6.5V and VPP = 13V (SNAP!
Pulse), TA = 25°C
PARAMETER MIN MAX UNIT
tdis(G) Output disable time from G\ 0 130 ns
ten(G)W Output enable time from G\ 150 ns

SMJ27C256 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
Rev. 1.0 9/01
6
 UVEPROM
SMJ27C256
Austin Semiconductor, Inc.
RECOMMENDED TIMING REQUIREMENTS FOR PROGRAMMING: VCC = 6.5 and VPP = 13
(SNAP! Pulse), TA = 25°C (See Figure 2)
MIN TYP MAX UNIT
th(A) Hold Time, Address 0 µs
th(D) Hold Time, Data 2 µs
tw(E)PR Pulse Duration, Initial Program 95 100 105 µs
tsu(A) Setup Time, Address 2 µs
tsu(G) Setup Time, G\ 2 µs
tsu(E) Setup Time, E\ 2 µs
tsu(D) Setup Time, Data 2 µs
tsu(VPP) Setup Time, VPP 2 µs
tsu(VCC) Setup Time, VCC 2 µs

PARAMETER MEASUREMENT INFORMATION

2.08V

RL = 800Ω

Output Under Test

CL = 100 pF1

NOTES:
1. CL includes probe and fixture capacitance.

The AC testing inputs are driven at 2.4V for logic high and 0.4V for logic low. Timing measurements are
made at 2V for logic high and 0.8V for logic low for both inputs and outputs.

FIGURE 2. LOAD CIRCUIT AND VOLTAGE WAVEFORMS

SMJ27C256 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
Rev. 1.0 9/01
7
 UVEPROM
SMJ27C256
Austin Semiconductor, Inc.
FIGURE 3. READ-CYCLE TIMING

FIGURE 4. PROGRAM-CYCLE TIMING (SNAP! PULSE PROGRAMMING)

SMJ27C256 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
Rev. 1.0 9/01
8
 UVEPROM
SMJ27C256
Austin Semiconductor, Inc.

MECHANICAL DEFINITION*

ASI Case #110 (Package Designator CW)

SMD 5962-86063, Case Outline X

D S2
A
Q
E L

e
S1 b2 b

eA
c

SMD SPECIFICATIONS
SYMBOL MIN MAX
A --- 0.232
b 0.014 0.026
b2 0.045 0.065
c 0.008 0.018
D --- 1.490
E 0.500 0.610
eA 0.600 BSC
e 0.100 BSC
L 0.125 0.200
Q 0.015 0.060
S1 0.005 ---
S2 0.005 ---
NOTE: These dimensions are per the SMD. ASI's package dimensional limits
may differ, but they will be within the SMD limits.

*All measurements are in inches.

SMJ27C256 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
Rev. 1.0 9/01
9
 UVEPROM
SMJ27C256
Austin Semiconductor, Inc.

ORDERING INFORMATION

EXAMPLE: SMJ27C256-30JM

Device Package Operating

Speed ns
Number Type Temp.
SMJ27C256 -15 J *

SMJ27C256 -17 J *

SMJ27C256 -20 J *

SMJ27C256 -25 J *

SMJ27C256 -30 J *

*AVAILABLE PROCESSES
M = Extended Temperature Range -55oC to +125oC

SMJ27C256 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
Rev. 1.0 9/01
10
 UVEPROM
SMJ27C256
Austin Semiconductor, Inc.

ASI TO DSCC PART NUMBER

CROSS REFERENCE*

ASI Package Designator J

TI Part #** SMD Part #
SMJ27C256-15JM 5962-8606305XA
SMJ27C256-17JM 5962-8606304XA
SMJ27C256-20JM 5962-8606301XA
SMJ27C256-25JM 5962-8606302XA
SMJ27C256-30JM 5962-8606303XA

* ASI part number is for reference only. Orders received referencing the SMD part number will be processed per the SMD.
** Parts are listed on SMD under the old Texas Instruments part number. ASI purchased this product line in November of 1999.
SMJ27C256 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
Rev. 1.0 9/01
11