HM-65162

2K x 8 Asynchronous
March 1997 CMOS Static RAM

Features Description
• Fast Access Time. . . . . . . . . . . . . . . . . . . . 70/90ns Max The HM-65162 is a CMOS 2048 x 8 Static Random Access
• Low Standby Current. . . . . . . . . . . . . . . . . . . .50µA Max Memory manufactured using the Intersil Advanced SAJI V
process. The device utilizes asynchronous circuit design for
• Low Operating Current . . . . . . . . . . . . . . . . . 70mA Max
fast cycle time and ease of use. The pinout is the JEDEC 24
• Data Retention at 2.0V . . . . . . . . . . . . . . . . . . .20µA Max pin DIP, and 32 pad 8-bit wide standard which allows easy
• TTL Compatible Inputs and Outputs memory board layouts flexible to accommodate a variety of
industry standard PROMs, RAMs, ROMs and EPROMs. The
• JEDEC Approved Pinout (2716, 6116 Type) HM-65162 is ideally suited for use in microprocessor based
• No Clocks or Strobes Required systems with its 8-bit word length organization. The conve-
• Equal Cycle and Access Time nient output enable also simplifies the bus interface by allow-
ing the data outputs to be controlled independent of the chip
• Single 5V Supply enable. Gated inputs lower operating current and also elimi-
• Gated Inputs nate the need for pull-up or pull-down resistors.
• No Pull-Up or Pull-Down Resistors Required

Ordering Information
PACKAGE TEMP. RANGE 70ns/20µA (NOTE 1) 90ns/40µA (NOTE 1) 90ns/300µA (NOTE 1) PKG. NO.
CERDIP -40oC to +85oC HM1-65162B-9 HM1-65162-9 HM1-65162C-9 F24.6
JAN# -55oC to +125oC 29110BJA 29104BJA - F24.6
SMD# -55oC to +125oC 8403606JA 8403602JA 8403603JA F24.6
CLCC -40oC to +85oC HM4-65162B-9 HM4-65162-9 HM4-65162C-9 J32.A
SMD# -55oC to 125oC 8403606ZA 8403602ZA 8403603ZA J32.A
NOTE:
1. Access time/data retention supply current.

Pinouts
HM-65162 HM-65162
(CERDIP) (CLCC)
TOP VIEW TOP VIEW
PIN DESCRIPTION
VCC
NC

NC

NC

NC

NC
A7

A7 1 24 VCC NC No Connect
4 3 2 1 32 31 30
A6 2 23 A8 A6 5 29 A8 A0 - A10 Address Input
A5 3 22 A9 6 28 A9
A5
A4 4 21 W E Chip Enable/Power Down
A4 7 27 NC
A3 5 20 G VSS/GND Ground
A3 8 26 W
A2 6 19 A10
A2 9 25 G DQ0 - DQ7 Data In/Data Out
A1 7 18 E
A0 8 17 DQ7 A1 10 24 A10 VCC Power (+5V)
DQ0 9 16 DQ6 A0 11 23 E
W Write Enable
DQ1 10 15 DQ5 NC 12 22 DQ7
DQ2 11 14 DQ4 G Output Enable
DQ0 13 21 DQ6
GND 12 13 DQ3 14 15 16 17 18 19 20
NC
DQ1

DQ2

DQ3

DQ4

DQ5
GND

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. File Number 3000.1
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999
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 HM-65162

Functional Diagram
A1
A
A2
A3 7
ROW 128 X 128
A4 ROW
ADDRESS MEMORY ARRAY
A5 DECODER 128
BUFFER A
A6
A7 7 1 OF 8
DQ0
128 THRU
8 DQ7
COLUMN DECODER
AND DATA
E INPUT / OUTPUT (X8)

4 4
A A
G COLUMN
ADDRESS BUFFER

A0 A8 A9 A10

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 HM-65162

Absolute Maximum Ratings Thermal Information

Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +7.0V Thermal Resistance θJA (oC/W) θJC (oC/W)
Input, Output or I/O Voltage . . . . . . . . . . . GND -0.3V to VCC +0.3V CERDIP Package . . . . . . . . . . . . . . . . 48 8
Typical Derating Factor . . . . . . . . . . 05mA/MHz Increase in ICCOP CLCC Package . . . . . . . . . . . . . . . . . . 66 12
ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1 Maximum Storage Temperature Range . . . . . . . . .-65oC to +150oC
Maximum Junction Temperature. . . . . . . . . . . . . . . . . . . . . . +175oC
Operating Conditions Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . +300oC

Operating Voltage Range . . . . . . . . . . . . . . . . . . . . . +4.5V to +5.5V

Operating Temperature Range Die Characteristics
HM-65162S-9, HM-65162B-9, Gate Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26000 Gates
HM-65162-9, HM65162C-9. . . . . . . . . . . . . . . . . . -40oC to +85oC
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating
and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

DC Electrical Specifications VCC = 5V ±10%; TA = -40oC to +85oC (HM-65162S-9, HM-65162B-9, HM-65162-9, HM-65162C-9)

LIMITS
SYMBOL PARAMETER MIN MAX UNITS TEST CONDITIONS
ICCSB1 Standby Supply Current - 50 µA HM-65162B-9, IO = 0mA,
E = VCC - 0.3V, VCC = 5.5V
- 100 µA HM-65162S-9, HM65162-9,
IO = 0mA, E = VCC - 0.3V,
VCC = 5.5V
- 900 µA HM-65162C-9, IO = 0mA,
E = VCC - 0.3V, VCC = 5.5V
ICCSB Standby Supply Current - 8 mA E = 2.2V, IO = 0mA, VCC = 5.5V
ICCEN Enabled Supply Current - 70 mA E = 0.8V, IO = 0mA, VCC = 5.5V
ICCOP Operating Supply Current (Note 1) - 70 mA E = 0.8V, IO = 0mA, f = 1MHz,
VCC = 5.5V
ICCDR Data Retention Supply Current - 20 µA HM-65162B-9, IO = 0mA,
VCC = 2.0V, E = VCC - 0.3V
- 40 µA HM-65162S-9, HM-65162-9,
IO = 0mA, VCC = 2.0V,
E = VCC - 0.3V
- 300 µA HM-65162C-9, IO = 0mA,
VCC = 2.0V, E = VCC - 0.3V
VCCDR Data Retention Supply Voltage 2.0 - V
II Input Leakage Current -1.0 +1.0 µA VI = VCC or GND, VCC = 5.5V
IIOZ Input/Output Leakage Current -1.0 +1.0 µA VIO = VCC or GND, VCC = 5.5V
VIL Input Low Voltage -0.3 0.8 V VCC = 4.5V
VIH Input High Voltage 2.2 VCC +0.3 V VCC = 5.5V
VOL Output Low Voltage - 0.4 V IO = 4.0mA, VCC = 4.5V
VOH1 Output High Voltage 2.4 - V IO = -1.0mA, VCC = 4.5V
VOH2 Output High Voltage (Note 2) VCC -0.4 - V IO = -100µA, VCC = 4.5V

Capacitance TA = +25oC
SYMBOL PARAMETER MAX UNITS TEST CONDITIONS
CI Input Capacitance (Note 2) 10 pF f = 1MHz, All measurements are
referenced to device GND
CIO Input/Output Capacitance (Note 2) 12 pF
NOTES:
1. Typical derating 5mA/MHz increase in ICCOP.
2. Tested at initial design and after major design changes.

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 HM-65162

AC Electrical Specifications VCC = 5V ±10%, TA = -40oC to +85oC (HM-65162S-9, HM-65162B-9, HM65162-9, HM-65162C-9)

LIMITS
HM-65162S-9 HM-65162B-9 HM-65162-9 HM-65162C-9
SYMBOL PARAMETER MIN MAX MIN MAX MIN MAX MIN MAX UNITS CONDITIONS
READ CYCLE
(1) TAVAX Read Cycle Time 55 - 70 - 90 - 90 - ns (Notes 1, 3)
(2) TAVQV Address Access Time - 55 - 70 - 90 - 90 ns (Notes 1, 3, 4)
(3) TELQV Chip Enable Access - 55 - 70 - 90 - 90 ns (Notes 1, 3)
Time
(4) TELQX Chip Enable Output 5 - 5 - 5 - 5 - ns (Notes 2, 3)
Enable Time
(5) TGLQV Output Enable Access - 35 - 50 - 65 - 65 ns (Notes 1, 3)
Time
(6) TGLQX Output Enable Output 5 - 5 - 5 - 5 - ns (Notes 2, 3)
Enable Time
(7) TEHQZ Chip Enable Output - 35 - 35 - 50 - 50 ns (Notes 2, 3)
Disable Time
(8) TGHQZ Output Enable Output - 30 - 35 - 40 - 40 ns (Notes 2, 3)
Disable Time
(9) TAVQX Output Hold From 5 - 5 - 5 - 5 - ns (Notes 1, 3)
Address Change
WRITE CYCLE
(10) TAVAX Write Cycle Time 55 - 70 - 90 - 90 - ns (Notes 1, 3)
(11) TELWH Chip Selection to End of 45 - 45 - 55 - 55 - ns (Notes 1, 3)
Write
(12) TAVWL Address Setup Time 5 - 10 - 10 - 10 - ns (Notes 1, 3)
(13) TWLWH Write Enable Pulse 40 - 40 - 55 - 55 - ns (Notes 1, 3)
Width
(14) TWHAX Write Enable Read 10 - 10 - 10 - 10 - ns (Notes 1, 3)
Setup Time
(15) TGHQZ Output Enable Output - 30 - 35 - 40 - 40 ns (Notes 2, 3)
Disable Time
(16) TWLQZ Write Enable Output - 30 - 40 - 50 - 50 ns (Notes 2, 3)
Disable Time
(17) TDVWH Data Setup Time 25 - 30 - 30 - 30 - ns (Notes 1, 3)
(18) TWHDX Data Hold Time 10 - 10 - 15 - 15 - ns (Notes 1, 3)
(19) TWHQX Write Enable Output 0 - 0 - 0 - 0 - ns (Notes 1, 3)
Enable Time
(20) TWLEH Write Enable Pulse 45 - 40 - 55 - 55 - ns (Notes 1, 3)
Setup Time
(21) TDVEH Chip Enable Data 25 - 30 - 30 - 30 - ns (Notes 1, 3)
Setup Time
(22) TAVWH Address Valid to End of 45 - 50 - 65 - 65 - ns (Notes 1, 3)
Write
NOTES:
1. Input pulse levels: 0 to 3.0V; Input rise and fall times: 5ns (max); Input and output timing reference level: 1.5V; Output load: 1 TTL gate
equivalent and CL = 50pF (min) - for CL greater than 50pF, access time is derated by 0.15ns per pF.
2. Tested at initial design and after major design changes.
3. VCC = 4.5 and 5.5V.
4. TAVQV = TELQV + TAVEL.

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 HM-65162

Timing Waveforms
(1) TAVAX
(2) TAVQV

ADDRESS

(8) TGHQZ

(5) TGLQV (7) TEHQZ

(6) TGLQX
E

(3) TELQV (9) TAVQX

(4) TELQX

NOTE:
1. W is high for a Read Cycle.

FIGURE 1. READ CYCLE

Addresses must remain stable for the duration of the read low continuously until all desired locations are accessed.
cycle. To read, G and E must be ≤ VIL and W ≥ VIH. The When E is low, addresses must be driven by stable logic
output buffers can be controlled independently by G while E levels and must not be in the high impedance state.
is low. To execute consecutive read cycles, E may be tied

(10) TAVAX

ADDRESS

(11) TELWH (14) TWHAX

(12) TAVWL (13) TWLWH

(20) TWLEH
W

(16) TWLQZ (19) TWHQX

Q
(21)
TDVEH

(17) TDVWH (18) TWHDX

(22) TAVWH

NOTE:
1. G is low throughout Write Cycle.

FIGURE 2. WRITE CYCLE I

To write, addresses must be stable, E low and W falling low and input data of the opposite phase to the outputs must not
for a period no shorter than TWLWH. Data in is referenced be applied, (Bus contention). If E transitions low
with the rising edge of W, (TDVWH and TWHDX). While simultaneously with the W line transitioning low, or after the
addresses are changing, W must be high. When W falls low, W transition, the output will remain in a high impedance
the I/O pins are still in the output state for a period of TWLQZ state. G is held continuously low.

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 HM-65162

Timing Waveforms (Continued)

(10) TAVAX

ADDRESS

(22) TAVWH

G
(14)
(11) TELWH
TWHAX

(12) TAVWL (13) TWLWH

TGHQZ
(15)
Q

(21) TDVEH

(17) TDVWH (18) TWHDX

FIGURE 3. WRITE CYCLE II

In this write cycle G has control of the output after a period, TGHQZ. When W transitions high, the data in can change
TGHQZ. G switching the output to a high impedance state after TWHDX to complete the write cycle.
allows data in to be applied without bus contention after

Low Voltage Data Retention

Intersil CMOS RAMs are designed with battery backup in 2. On RAMs which have selects or output enables (e.g., S,
mind. Data retention voltage and supply current are guaran- G), one of the selects or output enables should be held in
teed over temperature. The following rules ensure data the deselected state to keep the RAM outputs high im-
retention: pedance, minimizing power dissipation.
1. Chip Enable (E) must be held high during data retention; 3. Inputs which are to be held high (e.g., E) must be kept be-
within VCC -0.3V to VCC +0.3V. tween VCC +0.3V and 70% of VCC during the power up
and down transitions.
4. The RAM can begin operation > 55ns after VCC reaches
the minimum operating voltage (4.5V).

DATA
RETENTION
TIMING

VCC ≥ 02.0V
VCC
4.5V 4.5V

>55ns

VCC -0.3V TO VCC +0.3V

E

FIGURE 4. DATA RETENTION TIMING

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 HM-65162

Typical Performance Curve

-3
VCC = 2.0V
-4

-5

-6

LOG (ICC/(1A))
-7

-8

-9

-10

-11

-12
-55 -35 -15 5 25 45 65 85 105 125
TA (oC)

FIGURE 5. TYPICAL ICCDR vs TA

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Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate
and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which
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