CAT28C16A

16 kb CMOS Parallel
EEPROM
Description
The CAT28C16A is a fast, low power, 5V−only CMOS Parallel
EEPROM organized as 2K x 8−bits. It requires a simple interface for http://onsemi.com
in−system programming. On−chip address and data latches,
self−timed write cycle with auto−clear and VCC power up/down write
protection eliminate additional timing and protection hardware. DATA
Polling signals the start and end of the self−timed write cycle.
Additionally, the CAT28C16A features hardware write protection.
The CAT28C16A is manufactured using ON Semiconductor’s
advanced CMOS floating gate technology. It is designed to endure
100,000 program/erase cycles and has a data retention of 100 years. SOIC−24
The device is available in JEDEC approved 24−pin DIP and SOIC or J, K, W, X SUFFIX
CASE 751BK
32−pin PLCC packages.

Features
• Fast Read Access Times: 90 ns, 120 ns, 200 ns
• Low Power CMOS Dissipation:
PDIP−24 PLCC−32
– Active: 25 mA Max.
L SUFFIX N, G SUFFIX
– Standby: 100 mA Max. CASE 646AD CASE 776AK
• Simple Write Operation:
– On−chip Address and Data Latches PIN FUNCTION
– Self−timed Write Cycle with Auto−clear
Pin Name Function
• Fast Write Cycle Time: 10 ms Max
A0−A10 Address Inputs
• End of Write Detection: DATA Polling
• Hardware Write Protection I/O0−I/O7 Data Inputs/Outputs

• CMOS and TTL Compatible I/O CE Chip Enable

• 100,000 Program/Erase Cycles OE Output Enable

• 100 Year Data Retention WE Write Enable
• Commercial, Industrial and Automotive Temperature Ranges VCC 5 V Supply
VSS Ground
PIN CONFIGURATION
NC No Connect
DIP Package (L) PLCC Package (N, G)
SOIC Package (J, K, W, X)
VCC
WE
NC
NC
NC

NC
A7

A7 1 24 VCC ORDERING INFORMATION

A6 2 23 A8 4 3 2 1 32 31 30 See detailed ordering and shipping information in the package
3 22 A6 5 29 A8 dimensions section on page 10 of this data sheet.
A5 A9
4 21 A5 6 28 A9
A4 WE
A4 7 27 NC
A3 5 20 OE
A3 8 26 NC
A2 6 19 A10
A2 9 TOP VIEW 25 OE
A1 7 18 CE A1 10 24 A10
A0 8 17 I/O7 A0 11 23 CE
I/O0 9 16 I/O6 NC 12 22 I/O7
I/O1 10 15 I/O5 I/O0 13 21 I/O6
I/O2 11 14 I/O4 14 15 16 17 18 19 20
VSS 12 13 I/O3
NC
VSS
I/O1
I/O2

I/O3
I/O4
I/O5

© Semiconductor Components Industries, LLC, 2009 1 Publication Order Number:

October, 2009 − Rev. 6 CAT28C16A/D
 CAT28C16A

ADDR. BUFFER ROW 2,048 x 8

A4−A10 & LATCHES DECODER EEPROM
ARRAY

INADVERTENT HIGH VOLTAGE

VCC WRITE GENERATOR
PROTECTION

CE
OE CONTROL
WE LOGIC
I/O BUFFERS

TIMER DATA POLLING

I/O0−I/O7
ADDR. BUFFER
A0−A3 COLUMN
& LATCHES
DECODER

Figure 1. Block Diagram

Table 1. MODE SELECTION

Mode CE WE OE I/O Power
Read L H L DOUT ACTIVE
Byte Write (WE Controlled) L H DIN ACTIVE

Byte Write (CE Controlled) L H DIN ACTIVE

Standby, and Write Inhibit H X X High−Z STANDBY

Read and Write Inhibit X H H High−Z ACTIVE

Table 2. CAPACITANCE (TA = 25°C, f = 1.0 MHz, VCC = 5 V)

Symbol Test Max Conditions Units
CI/O (Note 1) Input/Output Capacitance 10 VI/O = 0 V pF
CIN (Note 1) Input Capacitance 6 VIN = 0 V pF
1. This parameter is tested initially and after a design or process change that affects the parameter.

Table 3. ABSOLUTE MAXIMUM RATINGS

Parameters Ratings Units
Temperature Under Bias –55 to +125 °C
Storage Temperature –65 to +150 °C
Voltage on Any Pin with Respect to Ground (Note 2) –2.0 V to +VCC + 2.0 V V
VCC with Respect to Ground −2.0 to +7.0 V
Package Power Dissipation Capability (TA = 25°C) 1.0 W
Lead Soldering Temperature (10 secs) 300 °C
Output Short Circuit Current (Note 3) 100 mA
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
2. The minimum DC input voltage is −0.5 V. During transitions, inputs may undershoot to −2.0 V for periods of less than 20 ns. Maximum DC
voltage on output pins is VCC + 0.5 V, which may overshoot to VCC + 2.0 V for periods of less than 20 ns.
3. Output shorted for no more than one second. No more than one output shorted at a time.

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 CAT28C16A

Table 4. RELIABILITY CHARACTERISTICS (Note 4)

Symbol Parameter Min Max Units
NEND (Note 5) Endurance 100,000 Cycles/Byte
TDR (Notes 5) Data Retention 100 Years
VZAP ESD Susceptibility 2,000 V
ILTH (Note 6) Latch−Up 100 mA
4. This parameter is tested initially and after a design or process change that affects the parameter.
5. For the CAT28C16A−20, the minimum endurance is 10,000 cycles and the minimum data retention is 10 years.
6. Latch−up protection is provided for stresses up to 100 mA on address and data pins from −1 V to VCC + 1 V.

Table 5. D.C. OPERATING CHARACTERISTICS (VCC = 5 V ±10%, unless otherwise specified.)

Limits

Symbol Parameter Test Conditions Min Typ Max Units

ICC VCC Current (Operating, TTL) CE = OE = VIL, 35 mA
f = 1/tRC min, All I/O’s Open

ICCC (Note 7) VCC Current (Operating, CMOS) CE = OE = VILC, 25 mA

f = 1/tRC min, All I/O’s Open

ISB VCC Current (Standby, TTL) CE = VIH, All I/O’s Open 1 mA

ISBC (Note 8) VCC Current (Standby, CMOS) CE = VIHC, All I/O’s Open 100 mA
ILI Input Leakage Current VIN = GND to VCC −10 10 mA
ILO Output Leakage Current VOUT = GND to VCC, −10 10 mA
CE = VIH

VIH (Note 8) High Level Input Voltage 2 VCC + 0.3 V

VIL (Note 7) Low Level Input Voltage −0.3 0.8 V
VOH High Level Output Voltage IOH = −400 mA 2.4 V
VOL Low Level Output Voltage IOL = 2.1 mA 0.4 V
VWI Write Inhibit Voltage 3.0 V
7. VILC = −0.3 V to +0.3 V
8. VIHC = VCC − 0.3 V to VCC + 0.3 V

Table 6. A.C. CHARACTERISTICS, READ CYCLE (VCC = 5 V ±10%, unless otherwise specified.)
28C16A−90 28C16A−12 28C16A−20

Symbol Parameter Min Max Min Max Min Max Units

tRC Read Cycle Time 90 120 200 ns
tCE CE Access Time 90 120 200 ns
tAA Address Access Time 90 120 200 ns
tOE OE Access Time 50 60 80 ns
tLZ (Note 9) CE Low to Active Output 0 0 0 ns
tOLZ (Note 9) OE Low to Active Output 0 0 0 ns
tHZ (Notes 9, 10) CE High to High−Z Output 50 50 55 ns
tOHZ (Notes 9, OE High to High−Z Output 50 50 55 ns
10)

tOH (Note 9) Output Hold from Address Change 0 0 0 ns

9. This parameter is tested initially and after a design or process change that affects the parameter.
10. Output floating (High−Z) is defined as the state when the external data line is no longer driven by the output buffer.

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 CAT28C16A

2.4 V
2.0 V
INPUT PULSE LEVELS REFERENCE POINTS
0.8 V
0.45 V

Figure 2. A.C. Testing Input/Output Waveform (Note 11)

11. Input rise and fall times (10% and 90%) < 10 ns.

1.3V

1N914

3.3K
DEVICE
UNDER OUT
TEST
CL = 100 pF

CL INCLUDES JIG CAPACITANCE

Figure 3. A.C. Testing Load Circuit (example)

Table 7. A.C. CHARACTERISTICS, WRITE CYCLE (VCC = 5 V ±10%, unless otherwise specified.)
28C16A−90 28C16A−12 28C16A−20

Symbol Parameter Min Max Min Max Min Max Units

tWC Write Cycle Time 5 5 10 ms
tAS Address Setup Time 0 0 10 ns
tAH Address Hold Time 100 100 100 ns
tCS CE Setup Time 0 0 0 ns
tCH CE Hold Time 0 0 0 ns
tCW (Note 12) CE Pulse Time 110 110 150 ns
tOES OE Setup Time 0 0 15 ns
tOEH OE Hold Time 0 0 15 ns
tWP (Note 12) WE Pulse Width 110 110 150 ns
tDS Data Setup Time 60 60 50 ns
tDH Data Hold Time 0 0 10 ns
tDL Data Latch Time 5 10 5 10 50 ns
tINIT (Note 13) Write Inhibit Period After Power−up 0.05 100 0.05 100 5 20 ms
12. A write pulse of less than 20 ns duration will not initiate a write cycle.
13. This parameter is tested initially and after a design or process change that affects the parameter.

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 CAT28C16A

DEVICE OPERATION

Read
Data stored in the CAT28C16A is transferred to the data bus when WE is held high, and both OE and CE are held low. The
data bus is set to a high impedance state when either CE or OE goes high. This 2−line control architecture can be used to
eliminate bus contention in a system environment.

tRC

ADDRESS

tCE
CE

tOE
OE

VIH tOLZ
WE
tLZ
tAA tOHZ

tOH tHZ
HIGH−Z
DATA OUT DATA VALID DATA VALID

Figure 4. Read Cycle

tWC

ADDRESS

tAS tAH

tCS tCH
CE

OE

tOES tWP tOEH

WE

tDL
HIGH−Z
DATA OUT

DATA IN
DATA VALID

tDS tDH

Figure 5. Byte Write Cycle [WE Controlled]

Byte Write edge of WE or CE, whichever occurs last. Data, conversely,

A write cycle is executed when both CE and WE are low, is latched on the rising edge of WE or CE, whichever occurs
and OE is high. Write cycles can be initiated using either WE first. Once initiated, a byte write cycle automatically erases
or CE, with the address input being latched on the falling the addressed byte and the new data is written within 10 ms.

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 CAT28C16A

DATA Polling complement of that data on I/O7 (I/O0–I/O6 are

DATA polling is provided to indicate the completion of a indeterminate) until the programming cycle is complete.
byte write cycle. Once a byte write cycle is initiated, Upon completion of the self−timed byte write cycle, all I/O’s
attempting to read the last byte written will output the will output true data during a read cycle.

tWC

ADDRESS

tAS tAH tDL

tCW
CE

tOEH

OE
tOES
tCS tCH

WE

HIGH−Z
DATA OUT

DATA IN DATA VALID

tDS tDH

Figure 6. Byte Write Cycle [CE Controlled]

ADDRESS

CE

WE

tOEH tOES
tOE

OE

tWC

I/O7 DIN = X DOUT = X DOUT = X

Figure 7. DATA Polling

Hardware Data Protection

The following is a list of hardware data protection features a write sequence, after VCC has reached 3.0 V
that are incorporated into the CAT28C16A. min.
1. VCC sense provides for write protection when VCC 3. Write inhibit is activated by holding any one of
falls below 3.0 V min. OE low, CE high or WE high.
2. A power on delay mechanism, tINIT (see AC 4. Noise pulses of less than 20 ns on the WE or CE
characteristics), provides a 5 to 20 ms delay before inputs will not result in a write cycle.

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 CAT28C16A

PACKAGE DIMENSIONS

PLCC 32
CASE 776AK−01
ISSUE O
PIN#1 IDENTIFICATION

E1 E E2

D1 A2
D A3

TOP VIEW END VIEW

SYMBOL MIN NOM MAX

b1 A2 0.38
A3 2.54 2.80
b 0.33 0.54
b1 0.66 0.82
D 12.32 12.57
b e
D1 11.36 11.50
D2
D2 9.56 11.32
SIDE VIEW E 14.86 15.11
E1 13.90 14.04
Notes:
E2 12.10 13.86
(1) All dimensions are in millimeters.
(2) Complies with JEDEC MS-016. e 1.27 BSC

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 CAT28C16A

PACKAGE DIMENSIONS

SOIC−24, 300 mils

CASE 751BK−01
ISSUE O

SYMBOL MIN NOM MAX

A 2.35 2.65
A1 0.10 0.30
A2 2.05 2.55
b 0.31 0.51
E1 E c 0.20 0.33
D 15.20 15.40
E 10.11 10.51
E1 7.34 7.60
e 1.27 BSC
h 0.25 0.75
b e L 0.40 1.27
θ 0º 8º
PIN#1 IDENTIFICATION
θ1 5º 15º
TOP VIEW

D h
h
q1

A A2 q

L q1
A1 c

SIDE VIEW END VIEW

Notes:
(1) All dimensions are in millimeters. Angles in degrees.
(2) Complies with JEDEC MS-013.

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 CAT28C16A

PACKAGE DIMENSIONS

PDIP−24, 600 mils

CASE 646AD−01
ISSUE A

SYMBOL MIN NOM MAX

A 6.35
A1 0.39
A2 3.18 4.95

E1 E b 0.36 0.55
b1 0.77 1.77
c 0.21 0.38
D 31.50 32.25
E 15.24 15.87
D
E1 12.32 14.73
e 2.54 BSC
TOP VIEW eB 15.24 17.78
L 2.93 5.08

A2 A

c
L
A1
b1 e b eB

SIDE VIEW END VIEW

Notes:
(1) All dimensions are in millimeters.
(2) Complies with JEDEC MS-011.

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 CAT28C16A

Example of Ordering Information

Prefix Device # Suffix

CAT 28C16A N I − 20 T

Company ID Product Number Temperature Range Speed Tape & Reel (Note 15)
(Optional) 28C16A Blank = Commercial (0°C to +70°C) −90: 90 ns T: Tape & Reel
I = Industrial (−40°C to +85°C) −12: 120 ns
A = Automotive (−40°C to +105°C) −20: 200 ns

Package
N: PLCC
J: SOIC (JEDEC)
K: SOIC (EIAJ)
L: PDIP (Lead Free, Halogen Free)
G: PLCC (Lead Free, Halogen Free)
W: SOIC (JEDEC) (Lead Free, Halogen Free)
X: SOIC (EIAJ) (Lead Free, Halogen Free)

14. The device used in the above example is a CAT28C16ANI−20T (PLCC, Industrial Temperature, 200 ns Access Time, Tape & Reel).
15. For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.

ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
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and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
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