Analog Integrated Circuits

The increasing complexity of circuit design needs to be managed with appropriate optimization algorithms and accurate statistical description of design models in order to reach the design specifics, guaranteeing ''zero defects''. In the Design for Yield open problems are the design of effective optimization algorithms and statistical analysis for yield design, which require time consuming techniques. New methods have to balance accuracy, robustness and computational effort. Typical analog integrated circuit optimization problems are computationally hard and require the handling of multiple, conflicting, and non-commensurate objectives having strong nonlinear interdependence. This paper tackles the problem by evolutionary algorithms to produce tradeoff solutions on the Pareto Front. In this research work Integrated Circuit (IC) design has been formulated as a constrained multi-objective optimization problem defined in a mixed integer/discrete/continuous domain. The following real-life circuits, RF Low Noise Amplifier, Leapfrog Filter, and Ultra Wideband LNA, were selected as test bed. The proposed algorithm, A-NSGAII, was shown to produce acceptable and robust solutions in the tested applications, where state-of-art algorithms and circuit designers failed. The results show significant improvement in all the chosen IC design problems.

In this paper, we review the recent advances of CMOS-based capacitive sensors for Lab-on-chip (LoC) applications. LoC design is a multidisciplinary approach of adapting classical biochemical assays to a miniaturized platform by exploiting advances in microelectronic and microfluidic technologies. By offering low cost and integrated devices, CMOS based LoCs could be amenable to a large number of biological and biochemical assays for disease diagnostics and biotechnology in the near future. While an exhaustive, all-encompassing review of CMOSbased LoCs is beyond the scope of this review, we have focused on the design and implementation of CMOS-based capacitive sensor LoCs for the most important biochemical applications. For each application, the corresponding biochemical sensing layer, interface circuit and microfluidic packaging technique are discussed based on the recent literature studies.

Geometric programming (GP) has been employed in automatic design of analog integrated circuits. Its major advantage is the ability to find the globally optimum solution to a problem. It however, suffers from dependency on the accuracy of the initial equations and the parameters used in these equations. This, in circuit design, causes discrepancies between GP predictions and simulation results-especially in sub-micron devices-thus resulting in a non-globally optimum circuit design. In this paper, two major sources of this discrepancy are introduced and resolved by an iterative simulation-equation-based design methodology based on GP for operational amplifiers. In order to show the effectiveness of the methodology, it has been applied to two op-amp architectures.

The implementation of a VHDL-AMS to SPICE converter (Vhdl2Spice) to be inserted in a complete CAD environment [1] is described. Vhdl2Spice generates a SPICE netlist by tracing down the VHDL IIR parse tree available from the already existing VHDL analyzer. ...

The use of two frequency compensation schemes for three-stage operational transconductance amplifiers, namely the reversed nested Miller compensation with nulling resistor (RN-MCNR) and reversed active feedback frequency compensation (RAFFC), is presented in this paper. The techniques are based on the basic RNMC and show an inherent advantage over traditional compensation strategies, especially for heavy capacitive loads. Moreover, they are implemented without entailing extra transistors, thus saving circuit complexity and power consumption. A well-defined design procedure, introducing phase margin as main design parameter, is also developed for each solution. To verify the effectiveness of the techniques, two amplifiers have been fabricated in a standard 0.5-m CMOS process. Experimental measurements are found in good agreement with theoretical analysis and show an improvement in small-signal and large-signal amplifier performances. Finally, an analytical comparison with the nonreversed counterparts topologies, which shows the superiority of the proposed solutions, is also included.

This paper presents a physically based model for the metal-oxide-semiconductor (MOS) transistor suitable for analysis and design of analog integrated circuits. Static and dynamic characteristics of the MOS field-effect transistor are accurately described by single-piece functions of two saturation currents in all regions of operation. Simple expressions for the transconductance-to-current ratio, the drain-to-source saturation voltage, and the cutoff frequency in terms of the inversion level are given. The design of a common-source amplifier illustrates the application of the proposed model. Index Terms-Circuit modeling, integrated circuit design, MOS analog integrated circuits, MOS devices.

Power consumption is one of the main design challenges in very-low-voltage high-speed analog integrated circuits. In this paper, different techniques to reduce the power consumption in low-voltage fastsettling operational amplifiers for switched-capacitor applications are discussed. These techniques include the cascode compensation, a new class-A/AB output stage and a novel dynamic allocation of settling time parameters. Design considerations for a 1.5-V very-low-power operational amplifier merging these techniques are addressed. HSPICE simulation results of the circuit in a 0.25-mm CMOS process confirm the effectiveness of the approaches to considerably reduce the power consumption of high-speed operational amplifiers. r

This paper deals with problems of porting integrated circuit (IC) designs to new, scaled, process node. A problem arises especially when analog part of the chip has to be transferred. New process nodes provide many high end capabilities e.g. high speed and low power consumption. On the other more and more parasitic and higher order effects comes in to play. Therefore, extensive simulations of standard MOS device are obligated in order to unveil true device behaviour which is crucial in the world of analog IC design. For the characterization purposes Cadence ® Open Command Environment for Analysis (OCEAN) in conjunction with GNU Octave is exploited. Conclusions regarding design strategies are extracted. Important trade-offs are to be pointed out, as well.

The effects of device geometry, oxide thickness, and bias condition on the thermal noise of MOSFET's are investigated. The experimental results show that the conventional MOSFET thermal noise models do not accurately predict the thermal noise of MOSFET's. A model that is capable of predicting the thermal noise of both long and short channel devices in both the triode and saturation regions is presented. This model, which can be easily implemented into existing circuit simulators such as SPICE, has been verified by a wide variety of measurements.

We present design techniques that make possible the operation of analog circuits with very low supply voltages, down to 0.5 V. We use operational transconductance amplifier (OTA) and filter design as a vehicle to introduce these techniques. Two OTAs, one with body inputs and the other with gate inputs, are designed. Biasing strategies to maintain common-mode voltages and attain maximum signal swing over process, voltage, and temperature are proposed. Prototype chips were fabricated in a 0.18-m CMOS process using standard 0.5-V devices. The body-input OTA has a measured 52-dB DC gain, a 2.5-MHz gain-bandwidth, and consumes 110 W. The gate-input OTA has a measured 62-dB DC gain (with automatic gain-enhancement), a 10-MHz gain-bandwidth, and consumes 75 W. Design techniques for active-RC filters are also presented. Weak-inversion MOS varactors are proposed and modeled. These are used along with 0.5-V gate-input OTAs to design a fully integrated, 135-kHz fifth-order elliptic low-pass filter. The prototype chip in a 0.18-m CMOS process with of 0.5-V also includes an on-chip phase-locked loop for tuning. The 1-mm 2 chip has a measured dynamic range of 57 dB and draws 2.2 mA from the 0.5-V supply.

In this paper, a basic cell for low-power and/or lowvoltage operation is identified. It is evidenced how different versions of this cell, coined as "flipped voltage follower (FVF)" have been used in the past for many applications. A detailed classification of basic topologies derived from the FVF is given. In addition, a comprehensive list of recently proposed low-voltage/low-power CMOS circuits based on the FVF is given. Although the paper has a tutorial taste, some new applications of the FVF are also presented and supported by a set of simulated and experimental results. Finally, a design example showing the application of the FVF to build systems based on translinear loops is described which shows the potential of this cell for the design of high-performance low-power/low-voltage analog and mixed-signal circuits.

A low-voltage fully differential CMOS operational amplifier withconstant-gmand rail-to-rail input and output stages ispresented. It is the fully differential version of a previously realizedsingle-ended operational amplifier where a novel circuit to ensure constanttransconductance has been implemented [1]. The input stage is a rail-to-railstructure formed by two symmetrical OTAs in parallel (the input transistorsare operating in weak inversion). The class-AB output

This paper presents an improved low voltage cascode and flipped voltage follower (FVF) based current mirror with the enhancement of the bandwidth obtained by using a compensation resistor between the gates of the primary transistor pair. In this technique a carefully determined resistance is used in the diode connected MOS transistor of the current mirror for enhancing the bandwidth. Active realization of the compensation resistance using MOS operating in the triode region has also been applied to both the cascode and FVF based current mirror circuits. The proposed circuits have been simulated using PSpice for 0.25 lm CMOS technology and the obtained results are compared with their uncompensated topologies to show their effectiveness.

Failures induced on analog integrated circuits by electromagnetic interference (EMI) will be analyzed with particular emphasis on integrated operational amplifiers built with different technologies. Additionally, the correlation found between EMI susceptibility and large-signal opamp behavior will be discussed. Some criteria for the design of Io_w EMI susceptibility opamps will be derived. Finally, as an application example, the design ofa BiCMOS opamp with an extremely low-probability EMI-induced failure will be presented.

A 1-GHz operational amplifier with a gain of 76 dB while driving a 50-load is presented. The equivalent input noise voltage is as low as 1.2 nV/ p Hz. This combination of extremely high bandwidth, high gain, and low noise is the result of a threestage all-n-p-n topology combined with a multipath nested Miller compensation. Using 10-GHz f T n-p-n transistors, the realizable bandwidth could be of the order of 2-3 GHz. However, bond-wire inductances restrict the useful bandwidth to 1 GHz. The amplifier occupies an active area of 0.26 mm 2 and has been realized in the bipolar part of a 1-m BiCMOS process.

This paper discusses the implementation and performance of square root domain ®lters, which can be considered as the CMOS equivalent of the bipolar log domain technique. The square root design methodology is based on exploiting the MOSFET large-signal square law characteristic to implement ®lters which are input-output linear, but operate with internally non-linear signals. The design of subcircuits required for the implementation of square root domain ®lters is described based on the MOSFET translinear principle, and various performance issues are discussed. Simulation and measured results are also presented to con®rm the validity of this approach, which may be attractive for low-voltage operation at frequencies in the MHz range.

In this paper, a "composite" source-follower is presented. Using a positive-feedback, the structure synthesizes complex poles with a single branch. This allows to realize a single-branch biquadratic cell. Moreover, due to the intrinsic feedback present in any source-follower, the proposed cell performs larger linearity for smaller ov (= GS TH ). This is the opposite of other active filters and allows saving the power otherwise used to increase linearity. A fourth-order prototype satisfy typical WLAN 802.11.a/b/g baseband filter specifications has been realized in a 0.18 m CMOS at 1.8-V supply. It achieves a 17.5-dBm IIP3 and a 40 dB HD3 for a 600-mV pp di input signal amplitude. A 24-V rms noise gives a DR = 79 dB, with 2.25-mA current consumption.

The symbolic simulator ISAAC (Interactive Symbolic Analysis of Analog Circuits) is presented. The program derives all ac characteristics for any analog integrated circuit (both time-continuous and switchedcapacitor, CMOS, JFET, and bipolar) as symbolic expressions in the circuit parameters. This yields analytic formulas for transfer functions, CMRR, PSRR, impedances, noise, etc. Two novel features are included in the program. First, the expressions can be simplified with a heuristic criterion based on the magnitudes of the elements. This yields interpretable formulas showing only the dominant terms. Secondly, the explicit representation of mismatch terms allows the accurate calculation of second-order effects, such as the PSRR.

Layout design of analog integrated circuits suffers from a lack of automation due to the multitude of complex design constraints. Most of them are specified and considered manually by expert designers (expert knowledge). We present a new methodology that enables the automatic inclusion of expert knowledge in the form of layout constraints. The resulting comprehensive constraint-driven design approach allows defining and verifying the analog layout constraints by transforming them between the different design domains. In order to verify our methodology, we present a new constraintdriven placement optimization engine. It includes a deterministic decision maker. The decision maker is used to solve effectively the hard instances of the optimization problem that are resulting from complex correlations between the constraints. We have verified our methodology successfully by applying it to the placement of analog circuits in an industrial design environment.

A configuration for the realization of voltage-mode second-order filters employing a single operational transresistance amplifier (OTRA) as the active element is presented. This topology can synthesize lowpass, highpass, bandpass, notch and allpass filtering functions. The presented filters are suitable for MOS-C implementation, yielding the filter parameters to be electronically tunable. Theoretical analysis is verified with PSPICE simulation.

In this paper a new basic cell for low-power and/or low-voltage operation is identified. It is shown that different versions of this cell, called "flipped voltage follower", have been used in the past for different applications. New circuits using this cell are also proposed here

Operational transconductance amplifiers (OTAs) are widely used in the design of electronically tunable circuits. However, electronic tunability ranges of the OTA based filters are restricted by the limited bandwidth of the transconductance gain of the OTA. Furthermore, stability conditions and the linearity of the OTA which depends on the control current restrict the tunability. In this paper, some trade-offs in the electronically tunable filters are investigated. In addition, the tunability ranges of some first and second order OTA-C and OTA-RC filters are comparatively examined. Moreover, an OTA-C all-pass filter circuit is presented. SPICE simulations are performed and stability analyses are given for both of the OTA-C and OTA-RC filters. Operation of the presented all-pass filter is verified experimentally.

This paper describes a highly linear current four quadrant multiplier. The circuit is designed to operate in a fully differential way. It is based on the square-law characteristic of MOS transistors in saturation region. Experimental results for 2 µm CMOS technology are provided.

This paper presents a new approach for detecting defects in analog integrated circuits using the feedforward neural network trained by the resilient error back-propagation method. A feed-forward neural network has been used for detecting catastrophic faults randomly injected in a simple analog CMOS circuit by classification the differences observed in supply current responses of good and faulty circuit. The experimental classification was performed for time and frequency domain, followed by a comparison of results achieved in both domains. It was shown that neural networks might be very efficient and versatile approach for test of analog circuits since an arbitrary fault class or circuit's parameter can be analyzed. Considered defect types and their successful detection by the neural network; and a possible off-chip hardware implementation of the proposed technique are discussed as well. Moreover, optimized hardware architecture of the selected neural network type was designed using VHDL for FPGA realization.

The goal of this paper is to present a tool for automatic sizing of analog basic integrated blocks using heuristics of non-linear optimization and an external electrical simulator. The methodology is based on the minimization of a cost function and constraint parameters related to circuit electrical characteristics. The methodology was implemented in Matlab using two heuristics of non-linear optimization, Simulated Annealing (SA) and Genetic Algorithms (GA). As electrical simulations we used the Smash simulator and the ACM MOSFET model. As design example, this paper shows the application of this methodology for the design of an active load differential amplifier using AMS 0.35µm technology.

We solve the manufacturing problem of identifying the model statistical parameters ensuring a satisfactory quality of analog circuits produced in a photolithographic process. We formalize it in a statistical framework as the problem of inverting the mapping from the population of the circuit production variables to the performances’ population. Both variables and performances are random. From a sample of the joint population we want to identify the statistical features of the former producing a performance distribution that satisfies the design constraints with a good preassigned probability. The key idea of the solution method we propose consists of describing the above mapping in terms of a mixture of granular functions, where each is responsible for a fuzzy set within the input-output space, hence for a cluster therein. The way of synthesizing the whole space as a mixture of these clusters is learnt directly from the examples. As a result we have an analytical form both of the mapping approximating complex Spice models in terms of polynomials in the production variables, and of the distribution law of the induced performances that allows a relatively quick and easy management of the production variables’ statistical parameters as a function of the probability with which we plan to satisfy the design constraint. We apply the method to case studies and real production data where our method outperforms current methods’ running times and accuracies.

With the continuous increase of integration densities and complexities, secure integrated circuits (ICs) are more and more required to guarantee reliability for safety-critical applications in the presence of soft and hard faults. Thus, testing has become a real challenge for enhancing the reliability of safety-critical systems. This paper presents a Self-Test and Self-Repair approach which can be used to tolerate the most likely defects of bridging type that create a resistive path between V DD supply voltage and the ground occurring in analog CMOS circuits during the manufacturing process. The proposed testing approach is designed using the 65 nm CMOS technology. We then used an operational amplifier (OPA) to validate the technique and correlate it with post layout simulation results.

Design centering is the term used for a procedure of obataining enhanced parametric yield of a circuit despite variations in device and design parameters. The process variability in nanometer regimes manifest into these device and design paramters. During design space exploration of analog circuits, a methodology to find design-instances with better yield is necessitated; this would ensure that the circuit will function as per specifications after fabrication even with impact of statistical variations. We need to evaluate circuit performance for a given instance of a circuit-design identified by possessing a set of nomial values of device-design parameters. A lot of instantces need be searhed having different sizes for a given circuit topology. HSPICE is very compute intensive. Instead, we employ macromodeling approach for analog circuits based on support vector machine (SVM), which enables efficient evaluation of performance of such circuits of different sizings during yield optimization loops. These performance macromodels are found to be as accurate as SPICE and at the same time time-efficicient for use in sizing of analog circuits with optimal yield. Process variability aware SVM macromodels are first trained and then used inside the Genetic algorithm loops for design centering of different circuits, subsequently resulting into sized-circuit instances having optimal yield. Post design centering, the sized circuits will be able to provide functions as per specifications upon fabrication. The application this design centering approach as process variability analysis tool is illustrated on various circuits e.g. two stage op amp, voltage controlled oscillator and mixer circuit with layouts drawn into 90 nm AMC technology.

In this paper, we describe a low-power low-voltage CMOS very low signal acquisition analog frontend of sensor electronic interfaces. These interfaces are mainly dedicated to biomedical implantable devices. In this work, we focus on the implantable bladder controller. Since the nerve signal has very low amplitude and low frequency, it is, at first fed to a low-voltage chopper amplifier to reduce the flicker (1/f ) noise and then amplified with a programmable gain high CMRR instrumentation amplifier. This is followed by an analog signal processing circuit to rectify and bin-integrate (RBI) the amplified signal. The resulting RBI is then converted to digital and transferred to the implant's central processor where information about bladder can be extracted. The numerous analog modules of the system have been implemented in CMOS 0.35 µm, 3.3 V technology. The design, simulation and measurement results of the proposed interface are presented. At supply voltage of 2.2 V the power dissipation is less than 1.4 mW, the input equivalent noise is 56 nV/ √ Hz and the error in RBI calculation is less than 0.15%.

This paper presents a programmable analog synapse for use in both feedforward and feedback neural networks. The synapse consists of two complementary floating-gate MOSFETs which are programmable in both directions by Fowler-Nordheim tunneling. The P-transistor and the N-transistor are programmable independently with pulses of different amplitude and duration, and hence finer weight adjustment is made possible. An experimental 4×4 synapse array has been designed, which in addition has 32 analog CMOS switches and x−y decoders to select a synapse cell for programming. It has been fabricated using a standard 2-μm, double-polysilicon CMOS technology. Simulation results confirm that output current of synapse is proportional to the product of the input voltage and weight and also shows both inhibitory and excitatory current. Current summing effect has been observed at the input of a neuron. This array is designed using modular and regular structured elements, and hence is easily expandable to larger networks.

Based on a physical understanding of phase-noise mechanisms, a passive LC filter is found to lower the phase-noise factor in a differential oscillator to its fundamental minimum. Three fully integrated LC voltage-controlled oscillators (VCOs) serve as a proof of concept. Two 1.1-GHz VCOs achieve 153 dBc/Hz at 3 MHz offset, biased at 3.7 mA from 2.5 V. A 2.1-GHz VCO achieves 148 dBc/Hz at 15 MHz offset, taking 4 mA from a 2.7-V supply. All oscillators use fully integrated resonators, and the first two exceed discrete transistor modules in figure of merit. Practical aspects and repercussions of the technique are discussed.

Absfract-In this paper ALSYN (Analog Layout SYNthesis), a new tool that synthesizes layout from netlist-level descriptions for a broad range of analog integrated circuits, is presented. User-defined rules derive partitioning and other control information, based on parameters and topology of the circuit. Equivalent control information can also be set individually, e.g., supplied in the input netlist by preceding circuit synthesis or during interactive usage of the synthesis system. This flexible concept enables designers to incorporate their own reusable knowledge into the synthesis process and to explore design space with the assistance of ALSYN. A flexible module generator environment and easy technology database access offer support for extending the library of parameterized layout primitives with variable shapes. Fast tools for constructive placement, using the MinCut/slicing tree approach, and for maze-style routing and postprocessing, offer various means to cope with the individual requirements of most analog applications. where he is engaged in the design of integrated analog CMOS circuits. His current interests are the design of custom analog/digital CMOS circuits, sensor electronics, and analog design automation.

A hybrid two-dimensional position sensing system is designed for mouse applications. The system measures the acceleration of handmovements which are converted into two-dimensional location coordinates. The system consists of four major components: 1) MEMS accelerometers, 2) CMOS analog read-out circuitry, 3) an acceleration magnitude extraction module, and 4) a 16-bit RISC microprocessor: Mechanical and analog circuit simulation shows that the designed padless mouse system can detect accelerations as small as 5.3 mg and operate up to 18MHz.

This paper presents a new approach for generating saturation constraints and DC performance expressions for analog integrated circuits. It also proposes a generalized method to develop AC performance expressions of the same in posynomial form. The developed posynomial expressions can be used for well established geometric programming (GP) based sizing optimization. The equation generation method takes very less time and does not require any manual intervention. The proposed method for AC performance expression generation is built on two levels of abstraction of a circuit. At the higher level, referred as macromodel, circuit performance metrics are modeled as function of device parameters such as transconductance (g m ), drain conductance (g d ), small-signal parasitic capacitances and overdrive voltage (V ov ). Whereas, at lower level of the abstraction the device parameters are monomial functions of device sizes and their biases. The two-level abstraction helps to develop technology independent performance model of a circuit. Whereas, the technology dependency is captured through device models. The proposed methods are applied to two well-known CMOS op-amp topologies namely, twostage and folded-cascode to generate saturation constraints, DC and AC performance expressions. With the developed constraints, both the circuits are designed through GP based circuit optimization in a 0.18 µm UMC technology. Performances of both are verified at their final design points.

In this paper we present an analog integrated circuit containing a matched pair of silicon cochleae and an address event interface. Each section of the cochlea, modeled by a second-order low-pass filter, is followed by a simplified Inner Hair Cell circuit and a Spiking Neuron circuit. When the neuron spikes, an Address Event is generated on the asynchronous data bus. Measurements with pure tones played from different positions are presented. 0-7803-8834-8/05/$20.00 ©2005 IEEE.

There is a growing demand for low-power, small-size and ambulatory biopotential acquisition systems. A crucial and important block of this acquisition system is the analog readout front-end. We have implemented a low-power and low-noise readout front-end with configurable characteristics for Electroencephalogram (EEG), Electrocardiogram (ECG), and Electromyogram (EMG) signals. Key to its performance is the new AC-coupled chopped instrumentation amplifier (ACCIA), which uses a low power current feedback instrumentation amplifier (IA). Thus, while chopping filters the 1/f noise of CMOS transistors and increases the CMRR, AC coupling is capable of rejecting differential electrode offset (DEO) up to 50 mV from conventional Ag/AgCl electrodes. The ACCIA achieves 120 dB CMRR and 57 nV/ Hz input-referred voltage noise density, while consuming 11.1 A from a 3 V supply. The chopping spike filter (CSF) stage filters the chopping spikes generated by the input chopper of ACCIA and the digitally controllable variable gain stage is used to set the gain and the bandwidth of the front-end. The front-end is implemented in a 0.5 m CMOS process. Total current consumption is 20 A from 3V.

In this paper, we present an analog integrated circuit design for an active 2-D cochlea and measurement results from a fabricated chip. The design includes a quality factor control loop that incorporates some of the nonlinear behavior exhibited in the real cochlea. This control loop varies the gain and the frequency selectivity of each cochlear resonator based on the amplitude of the input signal.

An efficient approach and an associated tool to optimize the performance of integrated analog circuits is described. The main objectives with the approach are to significantly speed up the design process and to obtain better overall, possibly optimal, circuit performance compared to a manual, simulation-based, approach. In order to achieve good agreement with circuit simulators high accuracy transistor models are used. A key feature is the automatic generation of the performance metrics and cost function from the circuit netlist. As a design example we select a current-mirror operational transconductance amplifier.

Typical analog and radio frequency (RF) circuit sizing optimization problems are computationally hard and require the handling of several conflicting cost criteria. Many researchers have used sequential stochastic refinement methods to solve them, where the different cost criteria can either be combined into a single-objective function to find a unique solution, or they can be handled by multiobjective optimization methods to produce tradeoff solutions on the Pareto front. This paper presents a method for solving the problem by the former approach. We propose a systematic method for incorporating the tradeoff wisdom inspired by the circuit domain knowledge in the formulation of the composite cost function. Key issues have been identified and the problem has been divided into two parts: a) normalization of objective functions and b) assignment of weights to objectives in the cost function. A nonlinear, parameterized normalization strategy has been proposed and has been shown to be better than traditional linear normalization functions. Further, the designers' problem specific knowledge is assembled in the form of a partially ordered set, which is used to construct a hierarchical cost graph for the problem. The scalar cost function is calculated based on this graph. Adaptive mechanisms have been introduced to dynamically change the structure of the graph to improve the chances of reaching the near-optimal solution. A correlated double sampling offset-compensated switched capacitor analog integrator circuit and an RF low-noise amplifier in an industry-standard 0.18 m CMOS technology have been chosen for experimental study. Optimization results have been shown for both the traditional and the proposed methods. The results show significant improvement in both the chosen design problems.

In this study, a general current-mode high output impedance sinusoidal oscillator configuration is proposed. The proposed oscillator configuration uses a single four terminal floating nullor (FTFN), two capacitors and five resistors. The oscillator configuration ...