Tolerance Analysis

The goal of the design and optimization phase in analog integrated circuits conception is to get the structure yielding the best system performance. The parameters of various components (resistance, capacitance, transistors, etc) of the circuit are set to the optimized nominal values, but no guarantee exists that these values will be conserved during the fabrication process. As a matter of

This paper describes a framework for an automotive body assembly process design system. It is a computer-aided intelligent system that can automatically generate the optimal joint types and assembly sequences for the best dimensional quality. The backbone of this system is the Case-Based Reasoning (CBR) methodology, which works by searching through a case library created from previous designs whose identifying features resemble the current case. Algorithms for initial solution generation, dimension chain generation, joint design selections, assembly sequence generation, and tolerance analysis and optimization are developed. Based on the framework, a software tool called Body Build Advisor, or BBA, is developed. The software allows process designers to analyze candidate assembly schemes and achieve the best assembly process design prior to having detailed knowledge of geometry of the parts, and thus is ideal for architectural process design. In addition, the system has the advantage of an open structure that can be easily modified and adapted to accommodate existing assemblies and to suggest areas for improvement. q

The scaling of semiconductor technologies from 90to 45-nm nodes highlights the need for accurate and predictive compact models that address the regime where small-scale physical effects become dominant. These demanding requirements on compact models extend beyond the core model to a suite of design tools that include extraction tools and statistical methods to account for unpredictable variation (e.g., random dopant fluctuations and polysilicon linewidth variation) and predictable variation (e.g., transistor response differences that are layout dependent). Layout-dependent or local environment differences are driven by factors such as lithography and novel performanceenhancing process techniques such as dual-stress nitride liner films. Sources of variation such as rapid thermal annealing temperature, low-frequency noise, and modeling of back-end-of-line elements need to be considered. The modeling of intradie and interdie variations, updated for small geometries, should be properly positioned in the design flow. This paper presents the challenges and results of compact modeling at the 65-nm node and beyond.

A statistical weld process monitoring system is described. Using data (voltage, current, wire feed speed, gas flow rate, travel speed, and elapsed arc time) collected while welding, the welding statistical process control (SPC) tool provides weld process quality control by implementing techniques of data trending analysis, tolerance analysis, and sequential analysis. The SPC system computes the mean, standard deviation, and range of each of the parameters sampled by the data collection system. Changes in the mean, standard deviation, and range are displayed using control (or trend) charts. The control chart displays a function of a parameter with respect to the ordering of the weld records (for a single weld) or weld number (for multiple welds). The SPC tool also permits plotting tolerance charts of the mean, standard deviation, and range for each of the sampled parameters. The tolerance chart is plotted versus the record number (or weld number) and consists of a vertical line for each record (or weld number) showing the minimum and maximum value of that parameter for that record (or weld number). The upper control limit (UCL), lower control limit (LCL), and nominal value may also be displayed on the tolerance chart printout. The SPC also performs sequential analysis, which allows the user to examine the process as it goes along, which in turn may permit the user to locate a possible change in the process before it goes out of control. Sequential analysis makes use of the running average and running standard deviation. Simply stated, the mean and standard deviation are constantly being updated as new values are read into the list. By examining each new value versus the accumulated information concerning previous values, a determination can be made of any suspect nature of the weld just completed. Work directed toward developing an expert interpreter of the voluminous statistical output generated by the SPC is also described.

A computer aided tolerance analysis tool is presented that assists the designer in evaluating worst case quality of assembly after tolerances have been specified. In tolerance analysis calculations, sets of equations are generated. The number of equations can be restricted by using a minimum number of points in which quality of assembly is calculated. The number of points needed depends

Variation in transistor characteristics is increasing as CMOS transistors are scaled to nanometer feature sizes. This increase in transistor variability poses a serious challenge to the cost-effective utilization of scaled technologies. Meeting this challenge requires comprehensive and efficient approaches for variability characterization, minimization, and mitigation. This paper describes an efficient infrastructure for characterizing the various types of variation in transistor characteristics. A sample of results obtained from applying this infrastructure to a number of technologies at the 90-, 65-, and 45-nm nodes is presented. This paper then illustrates the impact of the observed variability on SRAM, analog and digital circuit blocks used in system-on-chip designs. Different approaches for minimizing transistor variation and mitigating its impact on product performance and yield are also described.

A substantial amount of all quality problems that arise during assembly can be referred back to the geometrical design, and especially the geometrical concept of the product, i.e. the way in which parts are designed and located with each other. Special emphasis should thus be put on geometry design, especially during the early design phases, to try to ®nd robust concepts and avoid solutions that may cause down-stream production problems.

This study characterized Pokkali-derived quantitative trait loci (QTLs) for seedling stage salinity tolerance in preparation for use in marker-assisted breeding. An analysis of 100 SSR markers on 140 IR29/Pokkali recombinant inbred lines (RILs) confirmed the location of the Saltol QTL on chromosome 1 and identified additional QTLs associated with tolerance. Analysis of a series of backcross lines and near-isogenic lines (NILs) developed to better characterize the effect of the Saltol locus revealed that Saltol mainly acted to control shoot Na + /K + homeostasis. Multiple QTLs were required to acquire a high level of tolerance. Unexpectedly, multiple Pokkali alleles at Saltol were detected within the RIL population and between backcross lines, and representative lines were compared with seven Pokkali accessions to better characterize this allelic variation. Thus, while the Saltol locus presents a complex scenario, it provides an opportunity for markerassisted backcrossing to improve salt tolerance of popular varieties followed by targeting multiple loci through QTL pyramiding for areas with higher salt stress.