Analog VLSI

The fact that wide bandgap semiconductors are capable of electronic functionality at much higher temperatures than silicon has partially fueled their development, particularly in the case of SiC. It appears unlikely that wide bandgap semiconductor devices will find much use in low-power transistor applications until the ambient temperature exceeds approximately 300°C, as commercially available silicon and silicon-on-insulator technologies are already satisfying requirements for digital and analog VLSI in this temperature range. However practical operation of silicon power devices at ambient temperatures above 200°C appears problematic, as self-heating at higher power levels results in high internal junction temperatures and leakages. Thus, most electronic subsystems that simultaneously require high-temperature and high-power operation will necessarily be realized using wide bandgap devices, once they become widely available. Technological challenges impeding the realization of beneficial wide bandgap high ambient temperature electronics, including material growth, contacts, and packaging, are briefly discussed.

Abstmct-A wide-band, fast settling CMOS complementary folded ascode (CFC) transconductance amplifier for use in analog VLSI high frequency signal processing applications is introduced. The superior performance of the CFC architecture over that of the folder ascode (FC) or mirrored cascode (MC) approaches for VLSI ampliers is demonstrated. The symmetrically configured complementary input stage provides a wide common-mode input voltage range. The amplifier performs as an operational transconductance amplifier (OTA) and displays a first-order dominant pole when loaded by a shunt capacitor. The transconductance amplifier is small in area (0.016 mm'), and well suited for high frequency analog signal processing applications. Simulation and experimental results demonstrate a dc gain of approximately 50 dB, witth a 0.1% settling response of under 10 ns for loads varied from 0 to 2 pF.

Four cross-coupled MOS transistors operating as switches implement a very compact, fast, low-power and precise minimum and maximum current selector. Local positive feedback allows the circuit to work without the need of any control inputs and ensures very high sensitivity. Experimental results confirm the simulations and the analyzed second-order effects. Applications include min-max current selection and precision differential rectification. An application example of the cell to build a similarity circuit is reported.

In recent years it is growing need to think about development of rural areas by creating the source of income to villagers with the use of simple and user-friendly technology which reduces their losses and creating way to do business as well as employment for villagers. In this paper attempt has been given on reducing post harvesting losses and developing solar dryer as approach to increase the income in rural area. In the given work different type of drying techniques are studied and found the research gap with consideration of objective and design the solar dryer to overcome all the lacunas found. The experimentation had done at Yadrav (Maharashtra) which has latitude 16.7140° N and longitude 74.4882°E in the month of May and June. The research mechanism is designed for 30 kg capacity for fruits and vegetables. The innovations make dryer fully renewable, user-friendly with well-maintained drying condition which gives perfectly dried product suitable for international markets. The ...

Electrical activity in the brain spans a wide range of spatial and temporal scales, requiring simultaneous recording of multiple modalities of neurophysiological signals in order to capture various aspects of brain state dynamics. Here, we present a 16-channel neural interface integrated circuit fabricated in a 0.5 μm 3M2P CMOS process for selective digital acquisition of biopotentials across the spectrum of neural signal modalities in the brain, ranging from single spike action potentials to local field potentials (LFP), electrocorticograms (ECoG), and electroencephalograms (EEG). Each channel is composed of a tunable bandwidth, fixed gain front-end amplifier and a programmable gain/resolution continuous-time incremental ΔΣ analog-to-digital converter (ADC). A two-stage topology for the front-end voltage amplifier with capacitive feedback offers independent tuning of the amplifier bandpass frequency corners, and attains a noise efficiency factor (NEF) of 2.9 at 8.2 kHz bandwidth for spike recording, and a NEF of 3.2 at 140 Hz bandwidth for EEG recording. The amplifier has a measured midband gain of 39.6 dB, frequency response from 0.2 Hz to 8.2 kHz, and an input-referred noise of 1.94 μV rms while drawing 12.2 μA of current from a 3.3 V supply. The lower and higher cutoff frequencies of the bandpass filter are adjustable from 0.2 to 94 Hz and 140 Hz to 8.2 kHz, respectively. At 10-bit resolution, the ADC has an SNDR of 56 dB while consuming 76 μW power. Time-modulation feedback in the ADC offers programmable digital gain (1-4096) for auto-ranging, further improving the dynamic range and linearity of the ADC. Experimental recordings with the system show spike signals in rat somatosensory cortex as well as alpha EEG activity in a human subject.

We present and characterize an analog VLSI network of 4 spiking neurons and 12 conductance-based synapses, implementing a silicon model of biophysical membrane dynamics and detailed channel kinetics in 384 digitally programmable parameters. Each neuron in the analog VLSI chip (NeuroDyn) implements generalized Hodgkin-Huxley neural dynamics in 3 channel variables, each with 16 parameters defining channel conductance, reversal potential, and voltage-dependence profile of the channel kinetics. Likewise, 12 synaptic channel variables implement a rate-based first-order kinetic model of neurotransmitter and receptor dynamics, accounting for NMDA and non-NMDA type chemical synapses. The biophysical origin of all 384 parameters in 24 channel variables supports direct interpretation of the results of adapting/tuning the parameters in terms of neurobiology. We present experimental results from the chip characterizing single neuron dynamics, single synapse dynamics, and multi-neuron network dynamics showing phase-locking behavior as a function of synaptic coupling strength. Uniform temporal scaling of the dynamics of membrane and gating variables is demonstrated by tuning a single current parameter, yielding variable speed output exceeding real time. The 0.5 m CMOS chip measures 3 mm 3 mm, and consumes 1.29 mW. Index Terms-Neuromorphic engineering, reconfigurable neural and synaptic dynamics, silicon neurons, subthreshold metal-oxide semiconductor (MOS), translinear circuits.

The sum-product algorithm (belief/probability propagation) can be naturally mapped into analog transistor circuits. These circuits enable the construction of analog-VLSI decoders for turbo codes, low-density parity-check codes, and similar codes.

We present a mixed-mode analog/digital VLSI device comprising an array of leaky integrate-and-fire (I&F) neurons, adaptive synapses with spike-timing dependent plasticity, and an asynchronous event based communication infrastructure that allows the user to (re)configure networks of spiking neurons with arbitrary topologies. The asynchronous communication protocol used by the silicon neurons to transmit spikes (events) off-chip and the silicon synapses to receive spikes from the outside is based on the "address-event representation" (AER). We describe the analog circuits designed to implement the silicon neurons and synapses and present experimental data showing the neuron's response properties and the synapses characteristics, in response to AER input spike trains. Our results indicate that these circuits can be used in massively parallel VLSI networks of I&F neurons to simulate real-time complex spike-based learning algorithms.

New CMOS rail to rail second generation current conveyor circuits are proposed. First a class A current conveyor circuit which operates from a single supply of 1.5 V with a rail to rail voltage swing capability is given. The circuit is then modified to work as a class AB while maintaining the rail to rail swing capability. The class AB circuit works from supply voltages down to +1.1 V with standby current of 56 A. These new current conveyor realizations are insensitive to the threshold voltage variation caused by the body effect, which minimizes the layout area and makes both circuits a valuable addition to the analog VLSI libraries. PSpice simulation confirms the attractive properties of the proposed circuits.

Many time-critical neural network applications require fully parallel hardware implementations for maximal throughput. We first survey the rich array of technologies that are being pursued, then focus on the analog CMOS VLSI medium. Although analog VLSI holds great promise for implementing dense neural networks in a fully parallel manner, the medium is "messy" in that limited dynamic range, offset voltages, and noise sources all conspire to reduce precision. Many traditional neural models may be difficult to implement in analog technology. In this paper, we examine how neqral networks may be directly implemented in analog VLSI, giving examples of approaches that have been pursued to date. Two important application areas are highlighted Optimization, because neural hardware may offer a speed advantage of orders of magnitude over other methods, and supervised learning, because of the widespread use and generality of gradient-descent learning algorithms as applied to feedforward networks.

Motion perception is arguably a fundamental mechanism used by natural species to accomplish a number of tasks, such as navigating freely in an unknown environment. Traditional motion perception methods tend to be computationally intensive, requiring powerful computers and large memories. However, by copying biological mechanisms, such as elementary motion discrimination at the early stages of the visual processing paths, it

Using a two-dimension array of MOSFET switches, a robust, high speed object tracking CMOS sensor is presented. The edges of the image scene are extracted by the in-pixel differential comparators and a region (object) of interest, which is selected by the user, is segmented using the switch network. Tracking is performed by automatic reselection of the desired region. The proposed design presents less sensitivity to threshold adjustments compared to the binarization technique. The processing is mainly performed in analog domain, thus reducing dynamic power dissipation and making the chip ideal for low power applications. The sensor has been designed as a 50 Â 50 pixel VLSI CMOS chip in the 0.6 mm technology. Features such as power dissipation, output latency, and operating frequency are reported.

Analog VLSI on-chip learning Neural Networks represent a mature technology for a large number of applications involving industrial as well as consumer appliances. This is particularly the case when low power consumption, small size and/or very high speed are required. This approach exploits the computational features of Neural Networks, the implementation efficiency of analog VLSI circuits and the adaptation capabilities of the on-chip learning feedback schema. High-speed video cameras are powerful tools for investigating for instance the biomechanics analysis or the movements of mechanical parts in manufacturing processes. In the past years, the use of CMOS sensors instead of CCDs has enabled the development of high-speed video cameras offering digital outputs, readout flexibility, and lower manufacturing costs. In this paper, we propose a high-speed smart camera based on a CMOS sensor with embedded Analog Neural Network.

We propose margin propagation as an alternative to probability propagation in forward decoding. In contrast to sumproduct probability propagation, margin propagation only incurs addition and subtraction in the computation and thus leads to reduced complexity of implementation. Simulations indicate that margin based forward decoding is more robust to input noise and parameter mismatch than sumproduct probability decoding, and offers superior decoding performance. We also present an analog VLSI implementation of the margin propagation network independent of MOS device models, and provide experimental results from a prototype fabricated in a ¢ ¤ £¥ § ¦ process.

An auditory perception model for noise-robust speech feature extraction is presented. The model assumes continuous-time filtering and rectification, amenable to real-time, low-power analog VLSI implementation. A 3mm ¢ 3mm CMOS chip in 0.5£ ¥ ¤ CMOS technology implements the general form of the model with digitally programmable filter parameters. Experiments on the TI-DIGIT database demonstrate consistent robustness of the new features to noise of various statistics, yielding significant improvements in digit recognition accuracy over models identically trained using Mel-scale frequency cepstral coefficient (MFCC) features.

The aim of biologically inspired electronics is to emulate biology in building ultra low power, realtime, compact systems from an analog circuit engineer's or physicist's point of view. Such systems are useful as smart sensors. They are also useful in biomedical applications where the low power and biomimetic capabilities are particularly advantageous. Biologically inspired systems yield insights into how biology works via engineering synthesis that would be very hard to attain via scientific analysis. Work in the group focuses on three projects, the low-power bionic ear project, the time-based hybrid computing project, and the analog VLSI vision systems project.

A new CMOS programmable balanced output transconductor (BOTA) is introduced. The BOTA is a useful block for continuous-time analog signal processing. A new CMOS realization based on MOS transistors operating in the saturation region is given. Application of the BOTA in realizing bandpass-lowpass-allpass-notch biquad mixed mode filter using four BOTAs and two grounded capacitors and in realizing current mode MOS-C oscillators using three or four BOTAs and two grounded capacitors are given. PSpice simulation results for the BOTA circuit and for its applications are also included. ᭧

We study a range of neural dynamics under variations in biophysical parameters underlying extended Morris-Lecar and Hodgkin-Huxley models in three gating variables. The extended models are implemented in NeuroDyn, a four neuron, twelve synapse continuous-time analog VLSI programmable neural emulation platform with generalized channel kinetics and biophysical membrane dynamics. The dynamics exhibit a wide range of time scales extending beyond 100 ms neglected in typical silicon models of tonic spiking neurons. Circuit simulations and measurements show transition from tonic spiking to tonic bursting dynamics through variation of a single conductance parameter governing calcium recovery. We similarly demonstrate transition from graded to all-or-none neural excitability in the onset of spiking dynamics through the variation of channel kinetic parameters governing the speed of potassium activation. Other combinations of variations in conductance and channel kinetic parameters give rise to phasic spiking and spike frequency adaptation dynamics. The NeuroDyn chip consumes 1.29 mW and occupies 3 mm 3 mm in 0.5 m CMOS, supporting emerging developments in neuromorphic silicon-neuron interfaces.

Iterative decoding of high-performance error-correcting codes, such as turbo and related codes, is computationally demanding. This paper presents the application of a new type of analog computing network that enables the construction of all-analog decoders for such codes which outperform digital decoders in terms of speed and/or power consumption. The analog networks are based on the observation that certain computations

An analog continuous-time neural network with on-chip learning is presented. The 4-3-2 feed-forward network with a modified back-propagation learning scheme was build using micropower building blocks in a double poly, double metal 2/z CMOS process. The weights are stored in non-volatile UV-light programmable analog floating gate memories. A differential signal representation is used to design simple building blocks which may be utilized to build very large neural networks. Measured results from on-chip learning are shown and an example of generalization is demonstrated. The use of micro-power building blocks allows very large networks to be implemented without significant power consumption.

We are developing robot controllers based on biomimetic design principles. The goal is to realise the adaptive capabilities of the animal models in natural environments. We report feasibility studies of a hybrid architecture that instantiates a command and coordinating level with computed discrete-time map-based (DTM) neuronal networks and the central pattern generators with analogue VLSI (Very Large Scale Integration) electronic neuron (aVLSI) networks. DTM networks are realised using neurons based on a 1-D or 2-D Map with two additional parameters that define silent, spiking and bursting regimes. Electronic neurons (ENs) based on Hindmarsh-Rose (HR) dynamics can be instantiated in analogue VLSI and exhibit similar behaviour to those based on discrete components. We have constructed locomotor central pattern generators (CPGs) with aVLSI networks that can be modulated to select different behaviours on the basis of selective command input. The two technologies can be fused by interfacing the signals from the DTM circuits directly to the aVLSI CPGs. Using DTMs, we have been able to simulate complex sensory fusion for rheotaxic behaviour based on both hydrodynamic and optical flow senses. We will illustrate aspects of controllers for ambulatory biomimetic robots. These studies indicate that it is feasible to fabricate an electronic nervous system controller integrating both aVLSI CPGs and layered DTM exteroceptive reflexes.

We present a compact circuit architecture for analog VLSI realization of event-addressable neuromorphic arrays with conductance-based synaptic dynamics. Synaptic input events are time-multiplexed, pooled by synapse type according to common reversal potential and activation dynamics. One such physical synapse element per postsynaptic neuron is provided for each type, selected by type index along with postsynaptic address. A log-domain encoding of first-order linear dynamics of synaptic conductance results in a compact circuit realization with three MOS transistors per synapse element. Circuit simulations show low-power operation with linear dynamics in conductance.

This work studies the problem of CMOS operational am- plifiers (OpAmps) design optimisation. The synthesis of these amplifiers can be translated into a multiple-objective optimisation task, in which a large number of specifications has to be taken into account, i.e., GBW, area, power con- sumption and others. We introduce and apply the Genetic Algorithm (4) (GA) optimisation technique to the

The sum-product algorithm (belief/probability propagation) can be naturally mapped into analog transistor circuits. These circuits enable the construction of analog-VLSI decoders for turbo codes, low-density parity-check codes, and similar codes.

A vision sensor for low-cost, fast, and robust vision systems is described. The sensor includes an on-chip analog computation of contrast magnitude and direction of image features. A temporal ordering of this information according to the contrast magnitude is used to reduce the amount of data delivered. This sensor, realized in a 0.5-μm two-poly three-metal technology, features a contrast sensitivity of 2%, a contrast direction precision of ±3°, and an illumination dynamic range of 120 dB. Applications with uncontrolled lighting conditions are ideal for this sensor.

Next-generation bionic ears or cochlear implants will be fully implanted inside the body of the patient and consequently have very stringent requirements on the power consumption used for signal processing. We describe a low-power programmable analog VLSI processing channel that implements bandpass filtering, envelope detection, logarithmic mapping and analog-to-digital conversion. A bionic ear processor may be implemented through the use of several such parallel channels. In a proof-of-concept 1.5 pm AMI MOSS implementation, the most power-hungry channel of OUT system (7.5kHz center frequency) consumed 7.8 pW of power, had an internal dynamic range (IDR) of 51dB. and provided 64 discriminable levels of loudness per channel. Such numbers already satisfy the requirements of today's commercial bionic ear processors and can lower the power consumption of even advanced DSP processing schemes of the future by an order of magnitude. Our processing channel is also well suited for use in low power speech recognition front ends, which commonly require the same sequence of operations in cepshum-like front ends. Future improvements in the interfaces between the various stages of our processing channel, which were nut optimized in this implementation, promise a potential intemal dynamic range of more than 60dB with little or no increase in power.

We describe an analog VLSI circuit implementing spike-driven synaptic plasticity, embedded in a network of integrate-and-fire neurons. This biologically inspired synapse is highly effective in learning to classify complex stimuli in semisupervised fashion. The circuits presented are designed in subthreshold CMOS consuming extremely low power. The pulsebased neural network communicates with the outside world using the Address Event Representation in an asynchronous fashion. We present measurements from a test chip, characterizing all the modules of the circuit and show how they match well with theoretical expectations. We finally demonstrate that the learning mechanism of the synapse is fully functional by stimulating it with Poisson distributed spike trains.

A partial review of neuromorphic vision sensors that are suitable for use in autonomous systems is presented. Interfaces are being developed to multiplex the high-dimensional output signals of arrays of such sensors and to communicate them in standard formats to off-chip devices for higher-level processing, actuation, storage and display. Alternatively, on-chip processing stages may be implemented to extract sparse image parameters, thereby obviating the need for multiplexing. Autonomous robots are used to test neuromorphic vision chips in real-world environments and to explore the possibilities of data fusion from different sensing modalities. Examples of autonomous mobile systems that use neuromorphic vision chips for line tracking and optical flow matching are described.

We describe and demonstrate a neuromorphic, analog VLSI chip (termed F-LANN) hosting 128 integrate-and-fire (IF) neurons with spike-frequency adaptation, and 16,384 plastic bistable synapses implementing a self-regulated form of Hebbian, spike-driven, stochastic plasticity. The chip is designed to offer a high degree of reconfigurability: each synapse may be individually configured at any time to be either excitatory or inhibitory and to receive either recurrent input from an on-chip neuron or AER-based input from an off-chip neuron. The initial state of each synapse can be set as potentiated or depressed, and the state of each synapse can be read and stored on a computer.

In this paper we present an analog circuit that determines the direction of incoming sound using two microphones. The circuit is inspired by biology and uses two silicon cochlea to determine the azimuthal angle of the sound source with respect to the axis of the two microphones using the time difference between the two microphone signals. A new algorithm, adapted to an analog VLSI implementation, is presented together with simulation and measurement results.

We present an analog VLSI address-event transceiver containing an array of integrate-and-fire neurons and a scheme for implementing a reconfigurable neural network with probabilistic synapses. Neural “spikes” are transmitted through address-event representation-the address of the sending neuron is communicated through an asynchronous request and acknowledgment cycle. Continuous-valued synaptic weights are implemented by probabilistically routing address events. Results from a prototype system ...

Abstruct-Current Implantable Cardioverter Defibrillators (ICD's) use timing based decision trees for cardiac arrhythmia classification. Timiig alone does not distinguish all rhythms for all patients. Hence, more computationally intensive morphology analysis is required for complete diagnosis. An analog VLSI neural network has been designed and tested to perform cardiac morphology classification tasks. Analog techniques were chosen to meet the strict power and area requirements of the implantable system while incurring the design difficulties of noise, drift and offsets inherent in analog approaches. The robustness of the neural network architecture however, to a large extent, overcomes these inherent shortcomings of the analog approach. The network is a 106:3 multilayer perceptron with on chip digital weight storage. The chip also includes a bucket brigade input to feed the Intracardiac Electrogram (ICEG) to the network and a Winner Take All circuit for converting classifications to a binary representation. The training system trained the network in loop and included a commercial implantable defibrillator in the signal processing path. The system has successfully distinguished two arrhythmia classes on a morphological basis for seven different patients with an average of 95% true positive and 97% true negative detections for the dangerous rhythm. The chip was implemented in 1.2 pm CMOS and consumes less than 200 nW maximum average power from a 3 V supply in an area of 2.2 x 2.2 mm'. 0018-9200/95$04.00 0 1995 IEEE COGGINS et al.: A HYBRID ANALOG AND DIGITAL VLSl NEURAL. NETWORK FOR INTRACARDIAC MORPHOLOGY CLASSlFlCATION

Inspired by a visual motion detection model for the rabbit retina and by a computational architecture used for early audition in the barn owl, we have designed a chip that employs a correlation model to report the one-dimensional eld motion of a scene in real time. Using subthreshold analog VLSI techniques, we have fabricated and successfully tested a 8000 transistor chip using a standard MOSIS process.

The original "analog electronic cochlea" of Lyon and Mead (1988) used a cascade of second-order filter sections in subthreshold analog VLSI to implement a low-power, realtime model of early auditory processing. Experience with many silicon-cochlea chips has allowed the identification of a number of important design issues, namely dynamic range, stability, device mismatch, and compactness. In this paper, the original design is discussed in light of these issues, and circuit and layout techniques are described which significantly improve its performance, robustness, and efficiency. Measurements from test chips verify the improved performance.

An analog very large scale integration (VLSI) neural network intended for cost-sensitive, battery-powered, highvolume applications is described. Weights are stored in the analog domain using a combination of dynamic and nonvolatile memory that allows both fast learning and reliable long-term storage. The synapse occupies 4.9 K m 2 in a 2-m technology. On-chip controlled perturbation-based gradient descent allows fast learning with very little external support. Other distinguishing features include a reconfigurable topology and a temperature-independent feedforward path. An eight-neuron, 64-synapse proof-of-concept chip reliably solves the exclusive-or problem in ten's of milliseconds and 4-b parity in hundred's of milliseconds. Index Terms-Analog nonvolatile memory, analog VLSI neural network, on-chip learning, perturbation learning, reconfigurable neural network topology, temperature-independent CMOS transconductance.

An auditory perception model for noise-robust speech feature extraction is presented. The model assumes continuous-time filtering and rectification, amenable to real-time, low-power analog VLSI implementation. A 3mm ¢ 3mm CMOS chip in 0.5£ ¥ ¤ CMOS technology implements the general form of the model with digitally programmable filter parameters. Experiments on the TI-DIGIT database demonstrate consistent robustness of the new features to noise of various statistics, yielding significant improvements in digit recognition accuracy over models identically trained using Mel-scale frequency cepstral coefficient (MFCC) features.

The extraction of accurate self-motion information from the visual world is a difficult problem that has been solved very efficiently by biological organisms utilizing non-linear processing. Previous bio-inspired models for motion detection based on a correlation mechanism have been dogged by issues that arise from their sensitivity to undesired properties of the image, such as contrast, which vary widely between images. Here we present a model with multiple levels of non-linear dynamic adaptive components based directly on the known or suspected responses of neurons within the visual motion pathway of the fly brain. By testing the model under realistic high-dynamic range conditions we show that the addition of these elements makes the motion detection model robust across a large variety of images, velocities and accelerations. Furthermore the performance of the entire system is more than the incremental improvements offered by the individual components, indicating beneficial non-li...

The polarimetric vector is a more general descriptor of light than intensity information alone, and it con- tains physical information about the imaged objects in a scene that traditional intensity based sensors ig- nore. Polarimeters - devices that measure polarization - are used to extract physical features from an im- age such as specularities, occluding contours, and material properties. Scientists

Novel on-chip algorithms are proposed for face analysis on pictures obtained from a multi-camera surveillance system. According to the objective of the face detection sub-system, spatial positional relations to be presented for which the methodology we used is detailed in the paper. The uniqueness of the approach is the methodology we applied provides superior performance (50 fps) on standard database compared to most of the known face detection systems. In the general model based face part identification schema we relied on, the heavy use of morphologic operations gave robust results, even in analog VLSI implementation.

This paper discusses some of the fundamental issues in the design of highly parallel, dense, low-power motion sensors in analog VLSI. Since photoreceptor circuits are an integral part of all visual motion sensors, we discuss how the sizing of photosensitive areas can afSect the peformance of such systems. We review the classic gradient and correlation algorithms and give a survey of analog motion-sensing architectures inspired by them. We calculate how the measurable speed range scales with signal-to-noise ratio (SNR)

We describe the response properties of a compact, low power, analog circuit that implements a model of a leaky-Integrate & Fire (I&F) neuron, with spike-frequency adaptation, refractory period and voltage threshold modulation properties. We investigate the statistics of the circuit's output response by modulating its operating parameters, like refractory period and adaptation level and by changing the statistics of the input current. The results show a clear match with theoretical prediction and neurophysiological data in a given range of the parameter space. This analysis defines the chip's parameter working range and predicts its behavior in case of integration into large massively parallel very-large-scaleintegration (VLSI) networks.

A high-speed analog VLSI image acquisition and preprocessing system has been designed and fabricated in a 0.35 m standard CMOS process. The chip features a massively parallel architecture enabling the computation of programmable low-level image processing in each pixel. Extraction of spatial gradients and convolutions such as Sobel or Laplacian filters are implemented on the circuit. For this purpose, each 35 m 35 m pixel includes a photodiode, an amplifier, two storage capacitors, and an analog arithmetic unit based on a four-quadrant multiplier architecture. The retina provides address-event coded output on three asynchronous buses: one output dedicated to the gradient and the other two to the pixel values.