A bandwidth enhanced patch antenna based on stacked resonators is proposed. Simulation results sh... more A bandwidth enhanced patch antenna based on stacked resonators is proposed. Simulation results show a bandwidth of 18.9 GHz with a center frequency of 295.65 GHz, while the antenna gain and radiation efficiency are 1.2 dB and 44.6% respectively. Compared to a regular patch antenna, the proposed design has 3x larger bandwidth. The antenna is realized in 0.13 μm CMOS technology and connected to a THz plasmonic detector at the gate terminal. The measured frequency response of the fabricated detector shows a 3 dB bandwidth of 17 GHz with a peak responsivity of 570 V/W at 300 GHz.
Journal of Micromechanics and Microengineering, Nov 18, 2016
This paper reports on electrostatic MEMS vibration energy harvesters with gapclosing interdigitat... more This paper reports on electrostatic MEMS vibration energy harvesters with gapclosing interdigitated electrodes, designed for and tested on HVAC air ducts. The harvesters were fabricated on SOI wafers with 200 m device layer using a custom microfabrication process. Designs with aspects ratio (electrodes' gap versus depth) of 10 and 20 were implemented, while the overall footprint was approximately 1 cm x 1 cm in both cases. In order to enhance the power output, a dual-level physical stopper system was designed to control the minimum gap between the electrodes, which is a key parameter in the conversion process. The dual-level stopper utilizes cantilever beams to absorb a portion of the impact energy as the electrodes approach the impact point, and a film of parylene with nanometer thickness deposited on the electrode sidewalls. The parylene layer defines the absolute minimum gap and provides electrical insulation. The fabricated devices were first tested on a vibration shaker to characterize the resonant behavior. Devices with aspect ratio 10 were found to exhibit frequency up-conversion, which enhances the amount of converted power. Devices with both aspect ratios were found to exhibits spring hardening due to impact with the stoppers and spring softening behavior at increasing voltage bias. The highest power measured on shaker table for sinusoidal vibrations was 3.13 W (includes enhancement due to frequency up-conversion driven by impact) for aspect ratio 10, and 0.166 W for aspect ratio 20. The corresponding dimensional figure-of-merit, defined as the power output normalized to vibration acceleration and frequency, squared voltage and device mass, was in the range of 1010-8 m/V 2 for both devices, about an order of magnitude higher than state-of-the-art. Testing was carried out on HVAC air duct vibrating with an RMS acceleration of 155 mg RMS , a primary frequency of 60 Hz and a PSD of 7.1510-2 g 2 /Hz. The peak power measured was 118nW with a PSD of 1.91x10-9 W/Hz at 120 Hz (four times of the primary frequency of 60 Hz), some of the highest values reported to date.
This paper presents a free-space 4-channels imaging multiple-input multiple-output (MIMO) system ... more This paper presents a free-space 4-channels imaging multiple-input multiple-output (MIMO) system for On-Off-Keying (OOK) Visible-Light-Communication (VLC) links. An aggregate data-rate of 600 Mb/s is measured over 6 meters link distance with a bit-error-rate (BER) below 10−3 with the 4-channels simultaneously modulated. While the majority of published VLC works to date use components-off-the-shelf (COTS) PIN or Avalanche PDs that require both non-standard and/or higher cost fabrication processes as well as high reverse bias potential, the presented receiver in this paper employs a 2×2 on-chip Nwell/Psub photodiodes (PD) array fabricated in a low cost CMOS-compatible process. To extract high data rate performance out of the proposed CMOS low speed PD array, a 2nd-order LCR equalization is used to compensate for the stringent bandwidth limitation of the PD, measured around 20 MHz and push the speed up to 150 Mbps/channel. With a red light-emitting-diode (LED) array at 650 nm, the 4-channels MIMO setup DC power consumption is 1.38 W, which represents to our knowledge an energy-per-bit record performance for OOK VLC systems of 2.3 nJ/bit.
A switching architecture for exponential function generators in submicron CMOS technology is prop... more A switching architecture for exponential function generators in submicron CMOS technology is proposed. The architecture is based on second-order rational approximation of exponential functions and can be realised using MOS transistors in the saturation regime. An implementation eliminating complex squarer/multiplier circuits is presented in 0.13 μm CMOS technology. Simulation results show a dB-linear range of 46 dB with less than ± 0.5 dB linear error while dissipating a maximum of 0.45 mW from a 1.2 V power supply.
European Physical Journal-applied Physics, Nov 1, 2016
Design, manufacturing and measurements results for silicon plasma wave transistors based wireless... more Design, manufacturing and measurements results for silicon plasma wave transistors based wireless communication wideband receivers operating at 300 GHz carrier frequency are presented. We show the possibility of Si-CMOS based integrated circuits, in which by: (i) specific physics based plasma wave transistor design allowing impedance matching to the antenna and the amplifier, (ii) engineering the shape of the patch antenna through a stacked resonator approach and (iii) applying bandwidth enhancement strategies to the design of integrated broadband amplifier, we achieve an integrated circuit of the 300 GHz carrier frequency receiver for wireless wideband operation up to/over 10 GHz. This is, to the best of our knowledge, the first demonstration of low cost 130 nm Si-CMOS technology, plasma wave transistors based fast/wideband integrated receiver operating at 300 GHz atmospheric window. These results pave the way towards future large scale (cost effective) silicon technology based terahertz wireless communication receivers.
IEEE Transactions on Circuits and Systems I-regular Papers, Sep 1, 2016
A novel encryption scheme based on complex chaotic networks is proposed in this paper. Compared w... more A novel encryption scheme based on complex chaotic networks is proposed in this paper. Compared with a single chaotic system, a network of chaotic systems possesses complex dynamic characteristics, which can be used in encryption to enhance security. We adopt the drive-response synchronization method to synchronize two identical chaotic networks at the transmitter and receiver. Analysis on encryption security shows that key space is enlarged exponentially with respect to the number of nodes in the drive network, and also shows that the encryption system is highly sensitive to parameter mismatch. The proposed scheme is competent in carrying out encryption tasks of large data. Both theoretical and numerical results demonstrate that the proposed scheme is feasible for implementation in image and data encryption.
This work presents an inductorless, 10Gbps automatic gain control (AGC) circuit including a speed... more This work presents an inductorless, 10Gbps automatic gain control (AGC) circuit including a speed enhanced variable gain amplifier (VGA), a power detector, a comparator and a novel exponential function generator for extended dBlinear performance. Third order interleaved feedback technique is utilized in the current steering VGA stage to achieve 10Gb/s operation without using on-chip inductors. A stagger-tuned switching architecture for CMOS exponential function generation is proposed to achieve a dB-linear gain control range of ∼40dB with better than ±1 dB gain error. The relationship between tuning range and approximation error is analyzed and a novel current ratio generator circuit is proposed to implement the approximation functions in the current domain. The AGC circuit achieves a highest data rate of 10 Gb/s for 2 31-1 PRBS input, maintaining 360mV p-p constant differential output with a BER < 10-12 for an input dynamic range of ∼24 dB (15mV p-p to 240mV p-p). Fabricated in IBM 0.13-µm CMOS technology, the chip draws 50 mW from a 1.2 V power supply (excluding the output buffer) and occupies an active area of 0.4 mm 2. Index Terms-Automatic gain control (AGC), dB-linear gain control, exponential function generator, third-order interleaved feedback, variable gain amplifier (VGA).
This paper reports on an electrostatic MEMS vibration energy harvester with gapclosing interdigit... more This paper reports on an electrostatic MEMS vibration energy harvester with gapclosing interdigitated electrodes, designed for and tested on HVAC air ducts. The device is fabricated on SOI wafers using a custom microfabrication process. A dual-level physical stopper system is implemented in order to control the minimum gap between the electrodes and maximize the power output. It utilizes cantilever beams to absorb a portion of the impact energy as the electrodes approach the impact point, and a film of parylene with nanometer thickness deposited on the electrode sidewalls, which defines the absolute minimum gap and provides electrical insulation. The fabricated device was first tested on a vibration shaker to characterize its resonant behavior. The device exhibits spring hardening behavior due to impacts with the stoppers and spring softening behavior with increasing voltage bias. Testing was carried out on HVAC air duct vibrating with an RMS acceleration of 155 mg RMS and a primary frequency of 60 Hz with a PSD of 7.1510-2 g 2 /Hz. The peak power measured is 12nW (0.6 nW RMS) with a PSD of 6.910-11 W/Hz at 240 Hz (four times of the primary frequency of 60 Hz), which is the highest output reported for similar vibration conditions and biasing voltages.
An inductorless 10 Gb/s optical receiver including a novel transimpedance amplifier (TIA) with du... more An inductorless 10 Gb/s optical receiver including a novel transimpedance amplifier (TIA) with dual feedback loop and a limiting amplifier (LA) with third-order nested feedback is presented. The current-buffer based TIA employs an active Cherry-Hooper (CH) stage in the auxiliary amplifier and reuses the tail current source to achieve 10 Gbps operation in the presence of a 1pF photodiode input capacitance. The use of nested feedback in the four stage limiting amplifier enables a gain-bandwidth-product (GBP)>1THz without the use of area-consuming inductors. Implemented in IBM 130nm CMOS technology, the optical receiver achieves a BER<;10-12 at 10 Gbps for an input current of 30 μA, delivering 600 mV p-p at the output of the 50 Ω buffer. Optical testing confirmed a -13.8 dBm sensitivity for a data rate of 7.5 Gbps, mainly limited by the 850nm source used for measurement. The receiver dissipates 108mW from a 1.2V supply, while occupying a core area of only 0.08 mm2.
An inductorless, broadband amplifier architecture with enhanced stability and suppressed peaking ... more An inductorless, broadband amplifier architecture with enhanced stability and suppressed peaking is introduced. The architecture utilizes third order nested feedback technique to achieve high speed operation while maintaining robust stability compared to conventional architectures. The analysis and design considerations of the proposed architecture are presented and a prototype limiting amplifier is designed in 0.13-μm CMOS technology. The limiting amplifier achieves a voltage gain of 52 dB with a −3 dB bandwidth of 9 GHz while dissipating 75 mW from a 1.2 V power supply. An optical receiver front-end including the proposed amplifier is also implemented in the same technology. Measurement results with PRBS 231 −1 input confirm the functionality of the architecture for data rates up to 7Gb/s, limited mostly by the on-chip capacitance that emulates a photodiode. The entire chip dissipates 90 mW (without the 50Q output buffer) from a 1.2V supply and occupies an active area of only 0.074 mm2, including the offset cancellation network.
This paper presents an adaptive equalizer based on dual-loop balancing technique and a third orde... more This paper presents an adaptive equalizer based on dual-loop balancing technique and a third order nested feedback equalizing filter to achieve data rate up to 10Gb/s without using inductors. A spectral balancing circuit adjusts the equalizer boost, while a second servo loop automatically tracks the data rate using self-calibration and re-tunes the filters for optimal equalization. Third order nested feedback is introduced in the equalizing filters to compensate for ~15dB channel loss for a highest data rate of 10Gb/s. Implemented in IBM 0.13-μm CMOS technology, the equalizer maintains an eye opening of 0.26, 0.44 and 0.5UI with BER<;10-12 for 5 Gb/s, 8.5Gb/s and 10Gb/s PRBS31 inputs, respectively. The chip dissipates 130 mW from a 1.2V power supply, while occupying an active area of 0.34 mm2.
This paper presents an inductorless, 10Gbps automatic gain control (AGC) circuit including a spee... more This paper presents an inductorless, 10Gbps automatic gain control (AGC) circuit including a speed enhanced variable gain amplifier (VGA), a power detector, a comparator and a switching exponential function generator for extended dB-linear performance. Third order interleaved feedback technique is utilized to enhance the speed of the current steering VGA stage. A stagger-tuned switching architecture for CMOS exponential function generation is utilized to achieve a dB-linear gain control range of 45dB with better than ±0.5 dB gain error. The AGC circuit achieves a maximum data rate of 10 Gbps for 231-1 PRBS input, maintaining 360mVp-p constant differential output with a BER <; 10-12 for an input dynamic range of ~24 dB (15mVp-p to 240mVp-p). Fabricated in IBM 0.13-μm CMOS technology, the chip draws 50 mW from a 1.2 V power supply (excluding output buffer) and occupies an active area of 0.4 mm2.
A fully integrated 0.3 THz antenna-coupled plasma-wave detector with 10 GHz (measured) bandwidth ... more A fully integrated 0.3 THz antenna-coupled plasma-wave detector with 10 GHz (measured) bandwidth is presented. Fabricated in 130nm CMOS technology, the chip is formed of an E-shaped patch antenna, plasmonic based Field Effect Transistor (FET) detector and a wide bandwidth amplifier employing inductive shunt peaking. The open drain mode of operation of the detector achieves an absolute responsivity of 10 V/W with a minimum signal to noise ratio (SNR) of 40 dB over the entire bandwidth. With a drain current of 0.24 mA, the responsivity increases by 10X with a decrease in bandwidth to 3 GHz. The detector is also characterized without the on chip amplifier for imaging applications and shows a measured absolute responsivity of 150 V/W for a drain current of 5 μA at 0.3 THz.
This letter presents an On-Off-Keying (OOK) visible-light-communication (VLC) link realized over ... more This letter presents an On-Off-Keying (OOK) visible-light-communication (VLC) link realized over 6 meters distance. The transmitter is implemented with a commercially available red LED source at 650 nm. While most of the reported high-performance VLC links are using P-Insulator-N (PIN) photodetectors, this receiver employs a simple CMOS-compatible PN photo-detector. A 150 Mb/s optical wireless transmission is measured with a bit-error-rate (BER) of 1.3×10-6 , which falls below the forward error correction (FEC) limit of 3.8×10-3. Second-order L-C-R equalization is used in both the transmitter and the receiver circuits to achieve maximum bandwidth extension. The VLC link is realized with a low illuminance of 250 lux. This power is below the common indoor illumination levels which enables advanced lighting-compatible VLC applications. The receiver and the source circuits consume around 240 mW and 105 mW, respectively, which represents to our knowledge a record energy-per-bit level of 2.3 nJ/bit.
2016 41st International Conference on Infrared, Millimeter, and Terahertz waves (IRMMW-THz), 2016
This paper presents a high responsivity THz detector formed of two depletion mode pseudomorphic h... more This paper presents a high responsivity THz detector formed of two depletion mode pseudomorphic high electron mobility transistors (D-pHEMT) coupled to an on-chip bowtie antenna in GaAs 130 nm technology. The measured absolute responsivity of the integrated detector is 10 V/W at 250 GHz at a gate bias voltage of -0.3 V. A silicon lens attached to the GaAs substrate improves the responsivity of the detector by 20X while showing a noise equivalent power (NEP) of 25 pW/√Hz.
This paper studies the effect of non-ideal decoupling structures on the performance of single-end... more This paper studies the effect of non-ideal decoupling structures on the performance of single-ended circuits operating in the millimeter wave frequency range. Based on a first order approximation, an upper limit on the impedance of decoupling structures is derived given a pre-specified accepted degradation in insertion loss. To verify the analysis, a 110 GHz singleended amplifier with a compact decoupling structure based on distributed inter-digitized metal-oxide-metal capacitor (MOM-Cap) is implemented. The full wave electromagnetic simulations of the decoupling structure show an input impedance of (0.47-j0.12) Ω at 110 GHz, and the magnitude is less than 1 Ω from 82 GHz to 144 GHz. The degradation in the insertion loss of the matching networks is simulated to be less than 0.5 dB compared to the use of ideal decoupling capacitors at 110 GHz. The area of the decoupling structure is 18×100 µm 2 when implemented in 65 nm digital CMOS process.
A bandwidth enhanced patch antenna based on stacked resonators is proposed. Simulation results sh... more A bandwidth enhanced patch antenna based on stacked resonators is proposed. Simulation results show a bandwidth of 18.9 GHz with a center frequency of 295.65 GHz, while the antenna gain and radiation efficiency are 1.2 dB and 44.6% respectively. Compared to a regular patch antenna, the proposed design has 3x larger bandwidth. The antenna is realized in 0.13 μm CMOS technology and connected to a THz plasmonic detector at the gate terminal. The measured frequency response of the fabricated detector shows a 3 dB bandwidth of 17 GHz with a peak responsivity of 570 V/W at 300 GHz.
Journal of Micromechanics and Microengineering, Nov 18, 2016
This paper reports on electrostatic MEMS vibration energy harvesters with gapclosing interdigitat... more This paper reports on electrostatic MEMS vibration energy harvesters with gapclosing interdigitated electrodes, designed for and tested on HVAC air ducts. The harvesters were fabricated on SOI wafers with 200 m device layer using a custom microfabrication process. Designs with aspects ratio (electrodes' gap versus depth) of 10 and 20 were implemented, while the overall footprint was approximately 1 cm x 1 cm in both cases. In order to enhance the power output, a dual-level physical stopper system was designed to control the minimum gap between the electrodes, which is a key parameter in the conversion process. The dual-level stopper utilizes cantilever beams to absorb a portion of the impact energy as the electrodes approach the impact point, and a film of parylene with nanometer thickness deposited on the electrode sidewalls. The parylene layer defines the absolute minimum gap and provides electrical insulation. The fabricated devices were first tested on a vibration shaker to characterize the resonant behavior. Devices with aspect ratio 10 were found to exhibit frequency up-conversion, which enhances the amount of converted power. Devices with both aspect ratios were found to exhibits spring hardening due to impact with the stoppers and spring softening behavior at increasing voltage bias. The highest power measured on shaker table for sinusoidal vibrations was 3.13 W (includes enhancement due to frequency up-conversion driven by impact) for aspect ratio 10, and 0.166 W for aspect ratio 20. The corresponding dimensional figure-of-merit, defined as the power output normalized to vibration acceleration and frequency, squared voltage and device mass, was in the range of 1010-8 m/V 2 for both devices, about an order of magnitude higher than state-of-the-art. Testing was carried out on HVAC air duct vibrating with an RMS acceleration of 155 mg RMS , a primary frequency of 60 Hz and a PSD of 7.1510-2 g 2 /Hz. The peak power measured was 118nW with a PSD of 1.91x10-9 W/Hz at 120 Hz (four times of the primary frequency of 60 Hz), some of the highest values reported to date.
This paper presents a free-space 4-channels imaging multiple-input multiple-output (MIMO) system ... more This paper presents a free-space 4-channels imaging multiple-input multiple-output (MIMO) system for On-Off-Keying (OOK) Visible-Light-Communication (VLC) links. An aggregate data-rate of 600 Mb/s is measured over 6 meters link distance with a bit-error-rate (BER) below 10−3 with the 4-channels simultaneously modulated. While the majority of published VLC works to date use components-off-the-shelf (COTS) PIN or Avalanche PDs that require both non-standard and/or higher cost fabrication processes as well as high reverse bias potential, the presented receiver in this paper employs a 2×2 on-chip Nwell/Psub photodiodes (PD) array fabricated in a low cost CMOS-compatible process. To extract high data rate performance out of the proposed CMOS low speed PD array, a 2nd-order LCR equalization is used to compensate for the stringent bandwidth limitation of the PD, measured around 20 MHz and push the speed up to 150 Mbps/channel. With a red light-emitting-diode (LED) array at 650 nm, the 4-channels MIMO setup DC power consumption is 1.38 W, which represents to our knowledge an energy-per-bit record performance for OOK VLC systems of 2.3 nJ/bit.
A switching architecture for exponential function generators in submicron CMOS technology is prop... more A switching architecture for exponential function generators in submicron CMOS technology is proposed. The architecture is based on second-order rational approximation of exponential functions and can be realised using MOS transistors in the saturation regime. An implementation eliminating complex squarer/multiplier circuits is presented in 0.13 μm CMOS technology. Simulation results show a dB-linear range of 46 dB with less than ± 0.5 dB linear error while dissipating a maximum of 0.45 mW from a 1.2 V power supply.
European Physical Journal-applied Physics, Nov 1, 2016
Design, manufacturing and measurements results for silicon plasma wave transistors based wireless... more Design, manufacturing and measurements results for silicon plasma wave transistors based wireless communication wideband receivers operating at 300 GHz carrier frequency are presented. We show the possibility of Si-CMOS based integrated circuits, in which by: (i) specific physics based plasma wave transistor design allowing impedance matching to the antenna and the amplifier, (ii) engineering the shape of the patch antenna through a stacked resonator approach and (iii) applying bandwidth enhancement strategies to the design of integrated broadband amplifier, we achieve an integrated circuit of the 300 GHz carrier frequency receiver for wireless wideband operation up to/over 10 GHz. This is, to the best of our knowledge, the first demonstration of low cost 130 nm Si-CMOS technology, plasma wave transistors based fast/wideband integrated receiver operating at 300 GHz atmospheric window. These results pave the way towards future large scale (cost effective) silicon technology based terahertz wireless communication receivers.
IEEE Transactions on Circuits and Systems I-regular Papers, Sep 1, 2016
A novel encryption scheme based on complex chaotic networks is proposed in this paper. Compared w... more A novel encryption scheme based on complex chaotic networks is proposed in this paper. Compared with a single chaotic system, a network of chaotic systems possesses complex dynamic characteristics, which can be used in encryption to enhance security. We adopt the drive-response synchronization method to synchronize two identical chaotic networks at the transmitter and receiver. Analysis on encryption security shows that key space is enlarged exponentially with respect to the number of nodes in the drive network, and also shows that the encryption system is highly sensitive to parameter mismatch. The proposed scheme is competent in carrying out encryption tasks of large data. Both theoretical and numerical results demonstrate that the proposed scheme is feasible for implementation in image and data encryption.
This work presents an inductorless, 10Gbps automatic gain control (AGC) circuit including a speed... more This work presents an inductorless, 10Gbps automatic gain control (AGC) circuit including a speed enhanced variable gain amplifier (VGA), a power detector, a comparator and a novel exponential function generator for extended dBlinear performance. Third order interleaved feedback technique is utilized in the current steering VGA stage to achieve 10Gb/s operation without using on-chip inductors. A stagger-tuned switching architecture for CMOS exponential function generation is proposed to achieve a dB-linear gain control range of ∼40dB with better than ±1 dB gain error. The relationship between tuning range and approximation error is analyzed and a novel current ratio generator circuit is proposed to implement the approximation functions in the current domain. The AGC circuit achieves a highest data rate of 10 Gb/s for 2 31-1 PRBS input, maintaining 360mV p-p constant differential output with a BER < 10-12 for an input dynamic range of ∼24 dB (15mV p-p to 240mV p-p). Fabricated in IBM 0.13-µm CMOS technology, the chip draws 50 mW from a 1.2 V power supply (excluding the output buffer) and occupies an active area of 0.4 mm 2. Index Terms-Automatic gain control (AGC), dB-linear gain control, exponential function generator, third-order interleaved feedback, variable gain amplifier (VGA).
This paper reports on an electrostatic MEMS vibration energy harvester with gapclosing interdigit... more This paper reports on an electrostatic MEMS vibration energy harvester with gapclosing interdigitated electrodes, designed for and tested on HVAC air ducts. The device is fabricated on SOI wafers using a custom microfabrication process. A dual-level physical stopper system is implemented in order to control the minimum gap between the electrodes and maximize the power output. It utilizes cantilever beams to absorb a portion of the impact energy as the electrodes approach the impact point, and a film of parylene with nanometer thickness deposited on the electrode sidewalls, which defines the absolute minimum gap and provides electrical insulation. The fabricated device was first tested on a vibration shaker to characterize its resonant behavior. The device exhibits spring hardening behavior due to impacts with the stoppers and spring softening behavior with increasing voltage bias. Testing was carried out on HVAC air duct vibrating with an RMS acceleration of 155 mg RMS and a primary frequency of 60 Hz with a PSD of 7.1510-2 g 2 /Hz. The peak power measured is 12nW (0.6 nW RMS) with a PSD of 6.910-11 W/Hz at 240 Hz (four times of the primary frequency of 60 Hz), which is the highest output reported for similar vibration conditions and biasing voltages.
An inductorless 10 Gb/s optical receiver including a novel transimpedance amplifier (TIA) with du... more An inductorless 10 Gb/s optical receiver including a novel transimpedance amplifier (TIA) with dual feedback loop and a limiting amplifier (LA) with third-order nested feedback is presented. The current-buffer based TIA employs an active Cherry-Hooper (CH) stage in the auxiliary amplifier and reuses the tail current source to achieve 10 Gbps operation in the presence of a 1pF photodiode input capacitance. The use of nested feedback in the four stage limiting amplifier enables a gain-bandwidth-product (GBP)>1THz without the use of area-consuming inductors. Implemented in IBM 130nm CMOS technology, the optical receiver achieves a BER<;10-12 at 10 Gbps for an input current of 30 μA, delivering 600 mV p-p at the output of the 50 Ω buffer. Optical testing confirmed a -13.8 dBm sensitivity for a data rate of 7.5 Gbps, mainly limited by the 850nm source used for measurement. The receiver dissipates 108mW from a 1.2V supply, while occupying a core area of only 0.08 mm2.
An inductorless, broadband amplifier architecture with enhanced stability and suppressed peaking ... more An inductorless, broadband amplifier architecture with enhanced stability and suppressed peaking is introduced. The architecture utilizes third order nested feedback technique to achieve high speed operation while maintaining robust stability compared to conventional architectures. The analysis and design considerations of the proposed architecture are presented and a prototype limiting amplifier is designed in 0.13-μm CMOS technology. The limiting amplifier achieves a voltage gain of 52 dB with a −3 dB bandwidth of 9 GHz while dissipating 75 mW from a 1.2 V power supply. An optical receiver front-end including the proposed amplifier is also implemented in the same technology. Measurement results with PRBS 231 −1 input confirm the functionality of the architecture for data rates up to 7Gb/s, limited mostly by the on-chip capacitance that emulates a photodiode. The entire chip dissipates 90 mW (without the 50Q output buffer) from a 1.2V supply and occupies an active area of only 0.074 mm2, including the offset cancellation network.
This paper presents an adaptive equalizer based on dual-loop balancing technique and a third orde... more This paper presents an adaptive equalizer based on dual-loop balancing technique and a third order nested feedback equalizing filter to achieve data rate up to 10Gb/s without using inductors. A spectral balancing circuit adjusts the equalizer boost, while a second servo loop automatically tracks the data rate using self-calibration and re-tunes the filters for optimal equalization. Third order nested feedback is introduced in the equalizing filters to compensate for ~15dB channel loss for a highest data rate of 10Gb/s. Implemented in IBM 0.13-μm CMOS technology, the equalizer maintains an eye opening of 0.26, 0.44 and 0.5UI with BER<;10-12 for 5 Gb/s, 8.5Gb/s and 10Gb/s PRBS31 inputs, respectively. The chip dissipates 130 mW from a 1.2V power supply, while occupying an active area of 0.34 mm2.
This paper presents an inductorless, 10Gbps automatic gain control (AGC) circuit including a spee... more This paper presents an inductorless, 10Gbps automatic gain control (AGC) circuit including a speed enhanced variable gain amplifier (VGA), a power detector, a comparator and a switching exponential function generator for extended dB-linear performance. Third order interleaved feedback technique is utilized to enhance the speed of the current steering VGA stage. A stagger-tuned switching architecture for CMOS exponential function generation is utilized to achieve a dB-linear gain control range of 45dB with better than ±0.5 dB gain error. The AGC circuit achieves a maximum data rate of 10 Gbps for 231-1 PRBS input, maintaining 360mVp-p constant differential output with a BER <; 10-12 for an input dynamic range of ~24 dB (15mVp-p to 240mVp-p). Fabricated in IBM 0.13-μm CMOS technology, the chip draws 50 mW from a 1.2 V power supply (excluding output buffer) and occupies an active area of 0.4 mm2.
A fully integrated 0.3 THz antenna-coupled plasma-wave detector with 10 GHz (measured) bandwidth ... more A fully integrated 0.3 THz antenna-coupled plasma-wave detector with 10 GHz (measured) bandwidth is presented. Fabricated in 130nm CMOS technology, the chip is formed of an E-shaped patch antenna, plasmonic based Field Effect Transistor (FET) detector and a wide bandwidth amplifier employing inductive shunt peaking. The open drain mode of operation of the detector achieves an absolute responsivity of 10 V/W with a minimum signal to noise ratio (SNR) of 40 dB over the entire bandwidth. With a drain current of 0.24 mA, the responsivity increases by 10X with a decrease in bandwidth to 3 GHz. The detector is also characterized without the on chip amplifier for imaging applications and shows a measured absolute responsivity of 150 V/W for a drain current of 5 μA at 0.3 THz.
This letter presents an On-Off-Keying (OOK) visible-light-communication (VLC) link realized over ... more This letter presents an On-Off-Keying (OOK) visible-light-communication (VLC) link realized over 6 meters distance. The transmitter is implemented with a commercially available red LED source at 650 nm. While most of the reported high-performance VLC links are using P-Insulator-N (PIN) photodetectors, this receiver employs a simple CMOS-compatible PN photo-detector. A 150 Mb/s optical wireless transmission is measured with a bit-error-rate (BER) of 1.3×10-6 , which falls below the forward error correction (FEC) limit of 3.8×10-3. Second-order L-C-R equalization is used in both the transmitter and the receiver circuits to achieve maximum bandwidth extension. The VLC link is realized with a low illuminance of 250 lux. This power is below the common indoor illumination levels which enables advanced lighting-compatible VLC applications. The receiver and the source circuits consume around 240 mW and 105 mW, respectively, which represents to our knowledge a record energy-per-bit level of 2.3 nJ/bit.
2016 41st International Conference on Infrared, Millimeter, and Terahertz waves (IRMMW-THz), 2016
This paper presents a high responsivity THz detector formed of two depletion mode pseudomorphic h... more This paper presents a high responsivity THz detector formed of two depletion mode pseudomorphic high electron mobility transistors (D-pHEMT) coupled to an on-chip bowtie antenna in GaAs 130 nm technology. The measured absolute responsivity of the integrated detector is 10 V/W at 250 GHz at a gate bias voltage of -0.3 V. A silicon lens attached to the GaAs substrate improves the responsivity of the detector by 20X while showing a noise equivalent power (NEP) of 25 pW/√Hz.
This paper studies the effect of non-ideal decoupling structures on the performance of single-end... more This paper studies the effect of non-ideal decoupling structures on the performance of single-ended circuits operating in the millimeter wave frequency range. Based on a first order approximation, an upper limit on the impedance of decoupling structures is derived given a pre-specified accepted degradation in insertion loss. To verify the analysis, a 110 GHz singleended amplifier with a compact decoupling structure based on distributed inter-digitized metal-oxide-metal capacitor (MOM-Cap) is implemented. The full wave electromagnetic simulations of the decoupling structure show an input impedance of (0.47-j0.12) Ω at 110 GHz, and the magnitude is less than 1 Ω from 82 GHz to 144 GHz. The degradation in the insertion loss of the matching networks is simulated to be less than 0.5 dB compared to the use of ideal decoupling capacitors at 110 GHz. The area of the decoupling structure is 18×100 µm 2 when implemented in 65 nm digital CMOS process.
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Papers by Mona Hella