MOSCap Tool Primer

November 17, 2012 19:14 World Scientific Review Volume - 9in x 6in MOSCap
Chapter 1
MOSCap Tool on nanoHUB.org: A Primer
Abdussamad Muntahi and Shaikh Ahmed

Department of Electrical and Computer Engineering,
Southern Illinois University at Carbondale,
1230 Lincoln Drive, Carbondale, IL 62901, USA.
Phone: (618) 453 7630, Fax: (618) 453 7972, E-mail: [email protected]
The primary reason to study MOS (metal-oxide-semiconductor) capaci-

tors is to understand the principle of operation as well as become famil-
iar with some of the routinely used characterization techniques for MOS
field effect transistors (MOSFETs). The MOSCap tool on nanoHUB.org
simulates the one-dimensional electrostatics in single and dual-gate MOS
device structures along the growth direction as a function of device di-
mension, oxide charge, temperature, doping concentration, and AC fre-
quency. Among the quantities simulated, the low and high-frequency
capacitance-voltage (CV ) characteristics and various spatial profiles (en-
ergy band, electric field intensity, charge densities, and surface potential)
are of special importance. In this chapter, we will describe: 1) Structure
and basic operational principle of an MOS capacitor; 2) User interface
of the MOSCap simulator; 3) How to prepare an input deck and sample
simulations (examples); 4) Outputs and the major technologically im-
portant information that can be extracted from the simulation results;
and 5) Limitations of the MOSCap tool. The chapter is expected to
increase comprehension of the operation and applications of both con-
ventional and novel MOS capacitors from a semi-classical viewpoint. For
a quantum-mechanical description of capacitance in a MOS structure,
please see the Chapter on the Schred tool.
1. Introduction
1.1. What is an MOS Capacitor?

A capacitor is a device used to store electric charge. In its simplest form,
it consists of a pair of conductors separated by an insulator (dielectric
material). The MOS capacitor consists of a metal-oxide-semiconductor
1
2 Abdussamad Muntahi and Shaikh Ahmed
structure as shown in Fig. 1 below. The top layer is a metal or heavily

doped (on the order of 1020 cm−3 ) poly-silicon layer (which acts as a metal).
A thin oxide (here, SiO2) layer is sandwiched between the top conducting
layer and a bulk semiconductor (here, silicon) substrate that sits below the
insulator. The substrate, which is tied to the ground in normal mode of
operation, could be doped either p-type or n-type.
Fig. 1. A simple MOS capacitor.
1.2. Terminologies
Before we describe the operating principle of the device, we need to famil-

iarize ourselves with some terminologies. Below is a list:
Vacuum Level: It is the energy level where the electrons are free.
Electron Affinity (χ): Energy required for an electron to break loose from
atom and go to the vacuum level.
Fermi Level (Ef ): It is the energy level where the probability of finding an
electron is 12 . Fermi level provides useful information on how the electrons
are distributed in the energy space.
Work Function (qΦ): The energy difference between the vacuum level and
the Fermi level of any material. It is generally unique for a given material.
Band Gap (Eg ): The energy difference between the conduction band, Ec ,
and the valence band, Ev , of a semiconductor.
Intrinsic Level (Ei ): The energy level that lies at the center of the band
gap such that Ei = (Ec − Ev )/2.
MOSCap Tool on nanoHUB.org: A Primer 3
2. The Ideal MOS Capacitor
Let us consider an ideal p-substrate MOS capacitor (for a useful review see
Ref [1]). To accurately characterize MOS devices, we need to understand
the energy band diagrams. The energy band diagram of an ideal MOScap in
equilibrium (unbiased) condition is shown in Fig. 2. For an ideal MOSCap,
the metal workfunction (qΦm ) and the semiconducting workfunction (qΦs )
are equal. Hence, the Fermi levels (Ef m , Ef s ) line up throughout the struc-
ture and all the energy levels remain flat (that is, no built-in fields within
the structure). The quantity qφf in Fig. 2 measures the position of the
Fermi level with respect to the intrinsic level of the semiconductor and,
therefore, is a strong function of the substrate doping concentration. At
room temperature (T = 300 ◦K) the bandgap of the SiO2 is ∼ 8.9 eV and
that of silicon is ∼ 1.12 eV. The substrate is grounded.
Fig. 2. Energy band diagram of an ideal MOS capacitor in equilibrium.
2.1. Operation
The simple band diagram as depicted above is modified when a voltage,

Vg , is applied on the gate contact. Part of Vg is dropped across the oxide,
Vox , and part across the semiconductor, known as the surface potential, φs .
Depending on the polarity and magnitude of the applied gate voltage, the
surface condition changes, and the MOSCap goes through three distinct
operating regions as shown in Fig. 3. A negative gate voltage increases
the positive charge density (holes in this case) on the substrate (accumu-
lation mode); whereas a positive gate voltage creates a space-charge region
at the oxide/semiconductor interface (depletion mode) and the thermally
generated electrons start to populate the conduction band. As the posi-
tive gate voltage is further increased, the intrinsic level at first crosses the
Fermi level (weak inversion) and eventually drops far below the Fermi level
and the conduction band approaches the Fermi level. The density of elec-
trons increases significantly and when the magnitude of the band bending
(that is the surface potential) is equal to 2 × qφF , we say that a complete
(strong) inversion has occurred and a negatively charged electronic channel
is formed. Note that, even when a nonzero gate voltage is applied (that
is, the device is biased), since there is no current through the oxide insula-
tor, the Fermi level remains flat across the structure. However, depending
on the applied gate voltage and the surface condition, the direction of the
electric field changes from negative to positive (as indicated in Fig. 3 with
notation ξ). Also, note that Φm and χ are constants, and irrespective of
the bias arrangements, the device always remains charge neutral.
Fig. 3. Energy band diagram of an ideal MOS capacitor under applied bias. From left
to right: accumulation, depletion, and inversion regimes.
2.2. Analytical Calculation of Capacitance

dQ
We know that capacitance is given by, C = dV , where Q is the charge
and V is the potential. For an MOS capacitor, since Vg = Vox + φs , this
equation can be written as:
dQ 1 1
C= = dVox dφs
= 1 1 (1)
d(Vox + φs ) dQ + dQ Cox + Csem
Where, Cox is the oxide capacitance and Csem is the semiconductor capac-
itance originating from the response of the induced charge to the variation
of the surface potential. In other words, we see that the total (net) capac-
itance of an ideal MOS capacitor comes from a series combination of Cox
and Csem . To calculate the capacitance of an MOS device, therefore, we
need to establish a relationship between the applied voltage and the induced
charge in the semiconductor substrate. We can do this either analytically
or through a numerical approach. The numerical approach involves the so-
lution of the Poisson equation (most accurate in three dimensions), which
is discussed in detail in the Chapter on PN Junction Lab. Here, we present
the relevant equations for the semiconductor charge and the surface poten-
tial.
Charge in semiconductor substrate is given by[1 ]
kT
Qs = ±Ks εo F (Us , UF ) (2)
qLDi
(+ve for positive gate voltage and -ve for negative gate voltage.)
Here,
Ks is semiconductor dielectric constant (11.7 for silicon),
ǫo is permittivity of free space,
k is the Boltzmann constant,
T is the temperature in Kelvin,q
Intrinsic Debye length, LDi = kT2qK2 ns εi o ,
UF = φkTF ,
φs
Us = kT ,
φF = kT ln NnAi ,
ni is the intrinsic
p doping density and
F (U, UF ) = eUF (U + e−U − 1) − e−UF (U − eU − 1).
Eq. 2 gives us the total charge as a function of applied potential.
The gate voltage is given by:

Vg = ± K s Tox kT
Kox qLDi F (Us , UF ) + φs
Where,
Tox is the oxide thickness,
Kox is the oxide dielectric constant, and
φs is the potential drop across semiconductor (surface potential).
Below we provide a MATLAB code that uses the above equations and
plots (in Fig. 4) the Qs − Vg , φs − Vg and the C − Vg characteristics (which
seems to be noisy because of the discretization error) for an n-MOSCap
structure.
%%% MOS capacitor electrostatics: p-substrate
%%% Clear workspace:

clc
clear
%%% Inputs:
Tox = 2e-9;
Na = 1e23;
q = 1.6e-19;
Ks = 11.7;
Kox = 3.95;
k = 1.38e-23; %% J/K
T = 300;
eps0 = 8.85e-12;
Nc = 2e25;
Nv = 1e25;
Eg = 1.1; %% in eV
Eg = 1.1*q %% in Joules (J)
%%% Calculation:
ni = sqrt(Nc*Nv)*exp(-Eg/(2*k*T)) %% Eg and kT are both
phiF = (k*T)*log(Na/ni) %% in J in Joules
Ldi = sqrt((k*T*Ks*eps0)/(2*q*q*ni)) %% Joule based
%% calculation
ii = 1;
%% -ve gate voltage
for Vg = -2:0.01:0 %% Vg is potential (Volts) here

xaxis(ii) = Vg;
for V = 1.2:-0.00001:-1.2
%% V is a numeric (iterative) variable
%% for calculating Vs in Volts
lhs = Vg; %% LHS of the K.V.L.
u = V*q; %% u is in Joules
Fs = sqrt(exp(phiF/k/T)*(u/k/T + exp(-u/k/T) - 1)
- exp(-phiF/k/T)*(u/k/T - exp(u/k/T) + 1));
rhs = -(Ks*Tox)/Kox * (k*T)/q * 1/Ldi * Fs + V;
%% RHS of the K.V.L. (-ve for -ve Gate voltage)
if(lhs/rhs>= 0.99 && lhs/rhs<= 1.01)
Vs = V;
%% Vs (surface potential) is in Volts
Fss = Fs;
end
end
Qs(ii) = (Ks*eps0)*(k*T)/q*1/Ldi*Fss/q; %% #/cm2;
yaxis(ii) = Vs;
%%yaxis is surface potential (volts)
ii = ii + 1;
end
%% +ve gate voltage

for Vg = 0:0.01:2 %% Vg is potential (Volts) here
xaxis(ii) = Vg;
for V = -1.2:0.00001:1.2
%% V is a numeric (iterative) variable for
%% calculating Vs in Volts
lhs = Vg; %% LHS of the K.V.L.
u = V*q; %% u is in Joules
Fs = sqrt(exp(phiF/k/T)*(u/k/T + exp(-u/k/T) - 1)
- exp(-phiF/k/T)*(u/k/T - exp(u/k/T) + 1));
rhs = (Ks*Tox)/Kox * (k*T)/q * 1/Ldi * Fs + V;
%% RHS of the K.V.L.(+ve for +ve Gate voltage)
if(lhs/rhs>= 0.99 && lhs/rhs<= 1.01)
Vs = V;
%% Vs (surface potential) is in Volts
Fss = Fs;
end
end
Qs(ii) = -(Ks*eps0)*(k*T)/q*1/Ldi*Fss/q; %% #/cm2
yaxis(ii) = Vs;
%% yaxis is surface potential (volts)
ii = ii + 1;
end
%%% Capacitance:
for n = 2:1:ii-2
Vgate(n) = xaxis(n);
cap(n) = -(Qs(n)-Qs(n-1))*q/(Vgate(n)-Vgate(n-1));
if(cap(n)<1e-10)
cap(n) = cap(n-1);
end
end
%%%% Figure Plotting

figure(’Color’,’White’);
h1=plot(xaxis,abs(Qs),’r’);
%% Plotting the absolute charge as a
%% function of gate voltage
% Line options
set(h1,’linestyle’,’-’);
set(h1,’linewidth’,2)
% Figure options
set(gcf,’Colormap’,pink);
% Axis options
axis tight;
set(gca,’color’,[1 1 1]*1.0);
set(gca,’fontsize’,12);
set(gca,’layer’,’top’);
set(gca,’linewidth’,2);
xlabel(’Gate Voltage, V_G_S [V]’,’Fontsize’,16);
ylabel(’|Q_S|, [#/m^2]’,’Fontsize’,16);
% save
saveas(h1,’pMOScap-Qs-Vgs.fig’);
print pMOScap-Qs-Vgs.eps-deps;

h1=plot(xaxis,yaxis,’r’);
% Line options
% Figure options
% Axis options
axis tight;
set(gca,’color’,[1 1 1]*1.0);
ylabel(’Surface potential, [V]’,’Fontsize’,16);
% save
saveas(h1,’pMOScap-phiS-Vgs.fig’);
print pMOScap-phiS-Vgs.eps-deps;

h1=plot(Vgate,cap,’r’);
%% Plotting the absolute charge
% Line options
% Figure options
% Axis options
axis tight;
set(gca,’color’,[1 1 1]*1.0);
ylabel(’Capacitance, [F/m^2]’,’Fontsize’,16);
% save
saveas(h1,’pMOScap-Cap-Vgs.fig’);
print pMOScap-Cap-Vgs.eps-deps;
Fig. 4. Qs −Vg , φs −Vg , and the C−Vg characteristics for an p-substrate MOS structure.
3. MOSCap Tool Description
The MOSCap simulator is available at (http://nanohub.org/resources/

moscap). MOScap simulates the one-dimensional electrostatics in typical
single and dual-gate MOS device structures along the growth direction as
a function of device dimension, oxide charge, temperature, doping concen-
tration, and applied frequency. Among the quantities simulated, the low
and high-frequency capacitance-voltage (CV ) characteristics and various
spatial profiles (e.g., energy band, vertical electric field, charge densities
etc.) are of special importance. MOSCap also has an option for plotting
the semiconductor surface potential as a function of applied gate potential.
In the following, we describe the input parameters, the output quantities,
and important information that can be extracted from these outputs using
the MOScap tool.
3.1. Input Parameters
To simulate a device, we need to consider several structural and other

parameters in MOSCap. The input deck has four phases/tabs: Device
(contains structural information), Parameters, Environment and Surface
Potential.
3.1.1. Device:
Model: used to select Single or Double gate capacitor
Gate insulator thickness: Physical thickness of the oxide layer in µm (range:
0.001 - 10)
Gate insulator layer node: Number of finite calculation point in gate insu-
lator layer (range: 0 - 350)
Gate insulator dielectric constant: Relative permittivity of dielectric mate-
rial (ǫr )
Semiconductor thickness: Physical thickness of bulk semiconductor in µm
Semiconductor layer node: Number of finite calculation point (range: 2 -
1000)
Semiconductor doping type: Semiconductor doping type
Semiconductor doping characteristic: Only uniform doping is available at
this time
Gate electrode: Gate electrode type. Options are: aluminum, poly-silicon,
tungsten, or any specific material (for which, one needs to specify the work-
function from below)
Gate workfunction: Specify workfunction for any arbitrary gate contact
material.
3.1.2. Parameter:
Fixed charge density in gate insulator: Fixed bulk charge density divided
by q (that is number density) in gate insulator
Interface trap charge density in gate insulator: Interface trap charge density
divided by q in gate insulator
3.1.3. Environment:
Ambient temperature: Temperature around the device in K (range: 77 -
500)
Initial voltage: Initial value for the voltage sweep in V (range: -20 - 20)
Final voltage: Final value for the voltage sweep in V (range: -20 - 20)
Number of voltage steps: Integer number (range: 1 - 200)
High frequency value for AC Analysis: For C-V Characteristics (order of
106 ), in Hz (value > 1 Hz)
Low frequency value for AC Analysis: For C-V Characteristics (order of 10
Hz), in Hz (value > 0.01 Hz)
Minority carrier lifetime for electrons in ns: Smaller value gives better low-
Fig. 5. Input deck: Device.
Fig. 6. Input deck: Parameters.

frequency CV curve.
Minority carrier lifetime for holes in ns: Smaller value gives better low-
frequency CV curve.
Fig. 7. Input deck: Environment.
3.1.4. Surface Potential:

Check the box to plot surface potential. Note that this is a standalone
section in the simulator and uses the analytical models to compute surface
potential as a function of applied gate voltage (which we have already cov-
ered in Section 2).
Temperature: Temperature around the device in K (range: 4 - 500)
Acceptor dopant density: For a p-type substrate, in /cm3 (range: 0 /cm3 −
1022 /cm3 )
Donor dopant density: For a n-type substrate, in /cm3 (range: 0 /cm3 −
1022 /cm3 )
Intrinsic carrier density: in /cm3 (range: 0 /cm3 − 1022 /cm3 )
Oxide thickness: in µm (range: 0 - 10)
Gate voltage range minimum, Vg min: in V (range: -20 - 20)
Gate voltage range maximum, Vg max: in V (range: -20 - 20)
** In double gate device, input deck provides multiple options for left gate
and right gate options for all gate related parameters.
Fig. 8. Input deck: Surface Potential.
3.2. Output Analysis
Below is a list of of technologically important parameters, values of which

can be extracted from the CV characteristic of a MOS structure.
3.2.1. Extraction of device parameters from CV measurements
(1) Capacitance:
An equivalent circuit model for capacitances of an MOS structure is
shown in (Fig. 9). Here, capacitance depends on the frequency of ap-
plied signal (Fig. 10). At high frequency, electron concentration remains
fixed at an average value and electron layer does not respond to Vg . So,
the channel capacitance, Cch = 0 and the semiconductor capacitance
depends on the capacitance of the depletion region only (C < Cox).
For low frequency, electrons can be generated by thermal excita-
tion fast enough to be in phase with the applied signal and can re-
spond to Vg . Since channel is very thin (tch ≈ 0), channel capacitance,
ε
Cch ≈ tch ≈ ∞. Hence, capacitance of substrate and channel in paral-
lel becomes infinity, (Cs + Cch = ∞).
The net capacitance leads to
Fig. 9. Equivalent circuit for MOS capacitances.
Fig. 10. Typical CV characteristic for a p-substrate MOS capacitor.
1
C
1
= C1ox + Cs +C ch
= C1ox + 0 = C1ox .
So, the capacitance tends to go back to the Cox level (C ≈ Cox ).
In the following, we will use the low-frequency CV characteristic to
define and extract some other parameters.
(2) Oxide thickness:
Calculating oxide thickness is fairly simple and is given by,
ε0 εox
Tox = (3)
Cox
Where,
Tox is the oxide thickness (cm),

Cox is the oxide capacitance (Farad, F),
ǫo is the free space permittivity and
ǫox is the permittivity of oxide (F/cm).
(3) Flatband capacitance:
To have capacitance, we need applied voltage and charges available to
respond to the voltage. At zero temperature (T = 0K), there are no
charges to respond, so we do not have any capacitance. But at room
temperature (T = 300K), we have intrinsic charges in the device and
thermal potential (V0 = kT q ). At Vg = 0, as there would not be any
depletion layer, ideally all capacitance for flat-band (Cf b ) should come
from oxide capacitance (Cox ). But in reality, we see a slight drop in
the capacitance because of debye length due to thermal potential.
s
2εsi kT
LD ∼ (4)
q 2 NA
Where,
LD is the Debye length (cm),
ǫsi is the permittivity of silicon (F/cm),
kT is the thermal energy at room temperature, (300K)(4.046×10−21 J),
q is the electron charge (1.60219 ×1019C),
NA is the acceptor doping density (cm−3 ).
So, at Vg = 0, the flatband semiconductor capacitance is, Cs,f b = εL0D
εs
.
So, the flatband capacitance of the device is,
1
Cf b = 1 1 (5)
Cox + Cs,f b
(4) Threshold voltage:

In the CV curve, the threshold voltage is the point where surface po-
tential (φs ) is twice the Fermi potential (φF ). This point in the curve
corresponds to strong inversion. The threshold voltage is calculated as
follows:
√
4qNA εsi φF
VT = Vf b + 2φF + (6)
Cox
Where,
VT is the threshold voltage (V),
φF is the Fermi potential (V),
Fig. 11. Effect of thermal potential (and Debye length) on MOS flat-band capacitance.
kT NA
φs = 2φF = 2 ln (7)
q ni
and Vf b is the flatband voltage (V).

In a practical MOS Capacitor, poly-silicon is used instead of metal as
gate contact. Therefore, due to the variation in work function at the
gate/oxide interface, MOSCap operation deviates from the ideal case.
Also, work function of semiconductor φs varies as a function of doping
density. The metal-semiconductor work function difference is given by
(Φms = Φm − Φs ). As a result of this, the flat-band potential becomes,
Vf b = Φms − CQoxi , where Qi is the interface charge.
(5) Substrate doping concentration:
Doping concentration of the semiconductor sustrate can be extracted
from the slope of the CV characteristic, which at the depletion-layer
edge is given by[1 ]
2
Na (W ) = d( C12 )
(8)
qǫsi dV
3.2.2. Sample Simulations
During the course of building our first device, we will learn how to use the
MOSCap tool and plot and extract the output quantities conveniently.
Fig. 12. Substrate density can be extracted from the slope of the CV characteristic.
Device Description: Design and simulate a single-gate MOS Capacitor

with the following specification.
Structural Specifications
Substrate: p-Type
Substrate Thickness: 5 µm
Substrate Doping Density: 1e+15 /cm3 ; Uniform
Gate material: n-type poly-silicon
Insulator: SiO2; Thickness = 0.8 µm; Dielectric Constant, ǫox = 3.9
External Environment:
Temperature: 300 K
Initial Voltage: -10 V
Final Voltage: 10 V
Low frequency value: 1 Hz
The rest, for the time being, we can keep what we get as default in the
tool. Snapshots of the Input Decks/Phases for this simulation are shown
in Figs. 5 - 8:
Outputs: A typical Output Deck is shown in Fig. 13. All of the plots
that available from this simulator are, as of now, one-dimensional. Access
to simulation parameters used is available from the bottom panel/tab on
the deck.
A range of outputs are available in the drop-down menu shown in Fig. 14.
The user can download and save the outputs (as data or image) by clicking
the download button available at the top right corner (Fig. 15). Different
Fig. 13. The output deck.
Fig. 14. Output drop down menu.
formatting options are also available for the image Type, Axis, Legend, and
Layout (Fig. 16).
Fig. 15. Download data or image
Fig. 16. Downloading and saving options.
Description and Analysis of Outputs:
(1) CV Characteristic: The CV characteristics of the MOS structure show

both the normalized (by Cox ) and net capacitance as a function of

the gate voltage. This is probably the most important curve the user
would look for. As explained in an earlier Section, several different
parameters can be extracted from the CV characteristic. Please note
that the simulator does not, by default, calculate and provide these
values.
Fig. 17. CV Characteristic of the MOS structure.
(2) Energy Band Diagram: Conduction band, Valence Band, and the Fermi
level are available for equilibrium (Vg = 0) and biased (for last applied
bias) conditions.
In Fig. 18(a), because of the work function difference, a small band
bending is observed at the oxide/semiconductor interface even when
the device is unbiased. As expected, in the biased case (Fig. 18(b)),
the band bending is steeper which leads to the creation/induction of
the channel region populated by minority electrons.
(3) Electron Density: Electron density plots in the semiconductor substrate

are available for equilibrium (Vg = 0) and biased (last bias point) con-
ditions (Fig. 19(a) and Fig. 19(b)).
(a) At V g = 0 (b) At applied voltage
Fig. 18. Potential energy vs. Distance along the substrate depth.
(a) At Vg = 0 (b) At applied voltage
Fig. 19. Electron Density vs. Distance along the substrate depth.
(4) Hole Density: As electron density, hole density plots in the semicon-
ductor substrate are also available for equilibrium (Vg = 0) and biased
(last bias point) conditions (Fig. 20(a) and Fig. 20(b)). However, the
hole density plots depict an oppositive trend as a function of the gate
voltgae.
(5) Net Charge Density: Net charge density is defined as ρ = q(NA − ND +

n − p) and shown in Fig. 21(a) and Fig. 21(b).
Fig. 20. Hole Density vs. Distance along the substrate depth.
Fig. 21. Net charge density vs. Distance along the substrate depth.
(6) Electrostatic Potential: The potential is defined as V = const − q × Ec

and hence has an opposite trend with regard to the band diagram.
The equilibrium potential distribution (Fig. 22(a)) originates from the
gate/semiconductor workfunction difference. Fig. 22(b) shows the same
at biased condition. Also, due to absence of charges, potential varies
linearly with distance in the oxide region.
Fig. 22. Electrostatic potential vs. Distance along the substrate depth.
(7) Electric Field: Electric field is defined as ξ = −∇V and shown

in Fig. 23(a) and Fig. 23(b) for equilibrium and biased conditions.
Noticeable is the sharp transition of the electric field at the ox-
ide/semiconductor interface, which arises from the discontinuity (in-
homogeniety) of the dielectric constants (3.9 for oxide and 11.7 for
silicon) therein.
Fig. 23. Electric field intensity vs. Distance along the substrate depth.
Comparison of Outputs: Simulation tools on nanoHUB.org, in gen-

eral, allow users to run multiple sets of simulations (by varying one or a
group of parameters) and compare the results on a single plot. To illustrate
this, here, simulaiton results are presented and compared for two different
values for the substrate doping concentration of a MOS capacitor (Fig. 24).
As expected, by comparing the two CV curves, the user can immediately
see that the use of a higher substrate doping density leads to an increased
threshold voltage.
Fig. 24. CV characteristics of two MOS samples for NA1 = 10 15 cm −3 and

NA2 = 2 × 10 15 cm −3
4. Conclusion
The MOSCap tool on nanoHUB.org numerically describes the CV char-

acteristics of single-gate and dual-gate silicon MOS structures. The user
can extract an array of important device parameters from the CV char-
acteristic (such as threshold voltage, semiconductor doping density, typr
of gate contact, gate insulator thickness), which not only provide a better
understanding of the underlying physics, but help design improved MOS-
FETs using such MOS building blocks. MOSCap is based on the Padre
simulation tool developed by Mark Pinto, R. Kent Smith, and Ashraful
Alam at Bell Labs. The tool has three noteworthy limitations: 1) There is
no models available for the study of quantum mechanical effects; 2) Users
are not allowed to perform the AC analysis for a range of frequencies; and
3) MOSCap does not have sequence plots, that is, users cannot see what
happens in the intermediate steps between Vg = 0 and the last applied bias.
The MOSCap tool was published on nanoHUB on April 06, 2006. As of
November 16, 2012, the tool has served 3,296 users worldwide, who have
run a total of 32,189 simulation runs.
References
1. Y. Taur and T. H. Ning Fundamentals of Modern VLSI Devices 2009: Cam-

bridge University Press.

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November 17, 2012 19:14 World Scientific Review Volume - 9in x 6in MOSCap

MOSCap Tool on nanoHUB.org: A Primer

Abdussamad Muntahi and Shaikh Ahmed

The primary reason to study MOS (metal-oxide-semiconductor) capaci-

1.1. What is an MOS Capacitor?

2 Abdussamad Muntahi and Shaikh Ahmed

structure as shown in Fig. 1 below. The top layer is a metal or heavily

Fig. 1. A simple MOS capacitor.

Before we describe the operating principle of the device, we need to famil-

MOSCap Tool on nanoHUB.org: A Primer 3

2. The Ideal MOS Capacitor

Fig. 2. Energy band diagram of an ideal MOS capacitor in equilibrium.

The simple band diagram as depicted above is modified when a voltage,

4 Abdussamad Muntahi and Shaikh Ahmed

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2.2. Analytical Calculation of Capacitance

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The gate voltage is given by:

%%% MOS capacitor electrostatics: p-substrate

%%% Clear workspace:

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for Vg = -2:0.01:0 %% Vg is potential (Volts) here

%% +ve gate voltage

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%%%% Figure Plotting

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%%%% Figure Plotting

%%%% Figure Plotting

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3. MOSCap Tool Description

The MOSCap simulator is available at (http://nanohub.org/resources/

3.1. Input Parameters

To simulate a device, we need to consider several structural and other

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Fig. 5. Input deck: Device.

Fig. 6. Input deck: Parameters.

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Fig. 7. Input deck: Environment.

3.1.4. Surface Potential:

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and right gate options for all gate related parameters.

Fig. 8. Input deck: Surface Potential.

3.2. Output Analysis

Below is a list of of technologically important parameters, values of which

3.2.1. Extraction of device parameters from CV measurements

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Fig. 9. Equivalent circuit for MOS capacitances.

Fig. 10. Typical CV characteristic for a p-substrate MOS capacitor.

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Tox is the oxide thickness (cm),

(4) Threshold voltage:

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and Vf b is the flatband voltage (V).

3.2.2. Sample Simulations

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Device Description: Design and simulate a single-gate MOS Capacitor

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Fig. 13. The output deck.