Material Science

Paper No. : 09 Semiconductor Materials and Devices

Module: 2.2 MOS capacitors

Development Team
Prof. Vinay Gupta ,Department of Physics and Astrophysics,
Principal Investigator University of Delhi, Delhi

Dr. Monika Tomar ,Physics Department ,Miranda House

Paper Coordinator
University of Delhi, Delhi

Dr. Monika Tomar, Department of Physics, Miranda House University of Delhi, Delhi
Content Writer
Dr. Ayushi Paliwal, Department of Physics, Deshbandhu College, University of Delhi, Delhi

Prof. Vinay Gupta ,Department of Physics and Astrophysics,

Content Reviewer
University of Delhi, Delhi

Semiconductor Materials and Devices

Material Science
MOS capacitors
 Description of Module
Subject Name Material Science
Paper Name Semiconductor Materials and Devices
Module Name/Title Basics of BJT and JFET
Module Id 2.2

Semiconductor Materials and Devices

Material Science
MOS capacitors
 Contents of this Unit
1. Introduction
2. Ideal MOS device
3. Biasing conditions of an ideal MOS diode
4. Detailed analysis of surface space-charge region
5. C-V characteristics of Ideal MOS capacitor
6. Frequency dependence of CV curve of MOS capacitor
7. Practical MOS (SiO2-Si MOS diode)
8. Summary

Learning Objectives:
From this module students may get to know about the following:

• Schematic of MOS capacitors and the energy band diagram of ideal MOS diode.

• Energy band diagrams of ideal MOS diode under accumulation, depletion and inversion
conditions depending upon the applied bias voltage.

• Detailed analysis of space charge region

• C-V characteristics of ideal MOS capacitors under three biasing conditions

• Practical MOS diode along with some interface traps and charges in oxides

Semiconductor Materials and Devices

Material Science
MOS capacitors
 1. Introduction
Metal–oxide–semiconductor (MOS) capacitors exhibit sophisticated characteristics when compared to
the ordinary metal–dielectric–metal capacitors. It is the replacement of one metal electrode by a
semiconductor that leads to some unique effects. The dielectric in the MOS capacitor has almost always
been the silicon dioxide, or oxide, for short, so the standard term is MOS (metal–oxide–
semiconductor).The MOS capacitor can be seen as a structure consisting of two heterojunctions: (1)
metal–dielectric and (2) dielectric– semiconductor, where the dielectric is the silicon dioxide. It is the
high quality of oxide–semiconductor interface that enables practical applications of this device structure.
For decades, a device-quality oxide–semiconductor interface has been limited to one semiconductor
only—silicon. It is this fact that makes silicon by far the dominant semiconductor, in spite of the fact
that many other semiconductors have better bulk properties. Recently, device-quality oxide–
semiconductor interfaces have been developed on silicon carbide—a wide-energy-gap semiconductor
with excellent bulk properties. The problems with the interface are due to the dangling atomic bonds at
the semiconductor surface that have to be electronically passivated to enable existence of mobile chargeat
the semiconductor surface. There are no special effects at the metal–oxide interface. In fact, heavily
doped polysilicon has been typically used in the place of metal electrode, the reason being an important
technological effect that relates to the MOSFET structure.
MOS capacitors have been used in linear circuits and as the storage elements in random-access memories
(RAMs) and charge-coupled devices (CCDs). The real importance of this structure, however, is that it is
the central part of the most used device in electronics—the metal–oxide–semiconductor field-effect
transistor (MOSFET).The metal (or heavily doped polysilicon) electrode of the MOS capacitor in a
MOSFET is called the gate. Accordingly, the metal/polysilicon electrode of the MOS capacitor will be
referred to as the gate, and the oxide will frequently be referred to as the gate oxide to distinguish it from
oxide layers that play other roles in integrated circuits.
MOS diode is useful in the study of semiconductor surfaces, and is the core of the most important devices for
VLSI-MOSFET. The schematic of the MOS diode is as follows:

Figure 1: Schematic of an MOS diode

where, V is positive when metal is at positive bias w.r.t. ohmic contact.

Semiconductor Materials and Devices

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MOS capacitors
 2. Ideal MOS device:

Ideal MOS diode is defined as:

1. At zero applied bias, the energy difference between metal work function qm and semiconductor work
function qs is zero.
2. Oxide is perfect insulator devoid of any charges

The energy band diagram of an ideal MOS diode under zero applied bias is shown in figure 2 below:

Figure 2: Energy band diagram of an ideal MOS diode at V = 0

When applied bias is zero to an ideal MOS diode, then energy difference between the metal work function 𝑞𝜙𝑚
and the semiconductor wave function 𝑞𝜙𝑠 is zero i.e. the work function difference 𝑞𝜙𝑚𝑠 is zero. Thus, the work
function difference for p-type semiconductor can be expressed as
𝐸𝑔
𝑞𝜙𝑚𝑝 = 𝑞(𝜙𝑚 − 𝜙𝑝 ) = 𝑞𝜙𝑚 − [𝑞𝜒𝑝 + + 𝑞𝜓𝐵𝑝 ] = 0 (1)
2
where, q semiconductor electron affinity
Also, q𝜓𝐵 = Ei - EF
where, Ei corresponds to intrinsic Fermi level
EF corresponds to Fermi level
Consider, qBm be the metal to oxide barrier energy which is equal to the difference between lower edge of oxide
conduction band and metal fermi level.
𝐸𝑔
𝑞𝜙𝑚𝑛 = 𝑞𝜙𝑚 − [𝑞𝜒𝑛 + − 𝑞𝜓𝐵𝑛 ] = 0 (2)
2
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MOS capacitors
 𝑑𝐸𝐹𝑝
( = 0)
𝑑𝑥

For Si-SiO2 system, qm < qBm

The energy band is flat when V = 0 (Flat band condition):
The only charges that exist in diode under any biasing conditions are those in semiconductors and those with
equal but opposite sign on metal surface (adjacent to oxide). No carrier transport through the oxide under dc-
biasing conditions, or resistivity of oxide is infinite.
When ideal MOS diode is biased (positive or negative), there are three cases arises at semiconductor surface.
Thus, three biasing conditions for an ideal MOS diode are as follows.
3. Biasing conditions of an ideal MOS diode:

Case I: For a small and negative applied voltage V < 0, fermi level on metal side is raised by an amount qV than
on metal side. The schematic under this biasing condition is shown in figure 3(a) and the energy band diagram is
shown in figure 3(b).

Figure 3: (a) Schematic of an ideal MOS diode when V < 0, (b) Energy band diagram of an ideal MOS diode
when V < 0

Since, m &  remains unaffected by applied V, vacuum level on metal side also rise by qV. Bands near
semiconductor surface are bent upward (Ev, Ei, Ec). No current flows in MOS irrespective of V; the Fermi level in
semiconductor will remain constant. The vacuum level must bend up gradually to accommodate applied V (from
semiconductor side). Since, oxide is assumed to be charge free, the lower edge of the oxide conduction band will
bend linearly.

Semiconductor Materials and Devices

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MOS capacitors
 The negative applied bias voltage (-V) on the gate implies that negative charge on gate producing equal and
opposite charges in the semiconductor by attracting holes near the oxide-semiconductor interface. Therefore, there
is an enhanced concentration of holes occurs near semiconductor surface with a consequent upward bending of
energy levels. [Surface accumulation condition].
We know that carrier density in the semiconductor is
𝑝𝑝 = 𝑛𝑖 𝑒 (𝐸𝑖 −𝐸𝐹 )/𝐾𝑇 (3)
The upward bending of energy band causes the increase in (Ei - EF) implying enhanced concentration of holes
near oxide-semiconductor interface which is called as Accumulation condition.
Case II: For a small positive applied voltage V > 0, holes are pushed away from oxide interface. Therefore, there
is a formation of depletion region in semiconductor near interface, having mainly negative charged acceptor (Na)
ions. [Depletion Condition]. The schematic under this biasing condition is shown in figure 4(a) and the energy
band diagram is shown in figure 4(b).

Figure 4: (a) Schematic of an ideal MOS diode when V > 0, (b) Energy band diagram of an ideal MOS diode
when V > 0
Since hole concentration in depletion region is very much less than the concentration of holes in neutral region of
semiconductor, separation between EF and Ev is increased at interface causing a downward bending of energy
levels Ec , Ev and Ei..

The space charge per unit area in the semiconductor is [charge in depletion region which is W]

𝑄𝑆𝐶 = −𝑞𝑁𝐴 𝑊 (4)

where W represents the width of surface depletion region, and Na is the concentration of acceptor ions in the
semiconductor.

Semiconductor Materials and Devices

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MOS capacitors
 Case III: For a large positive applied voltage V >> 0, there is a downward bending of bands occurs and when Ei
touches EF at surface, then semiconductor surface becomes intrinsic (np = ni). For large V, Ei crosses EF and
conduction band comes closer to EF instead of valence band i.e. minority carriers (electrons) are attracted to
interface, semiconductor surface contains more electrons than holes. [Surface gets inverted from p-type to the n-
type]. The thin region (xi) where electrons concentration exceeds the hole concentration is called the inversion
layer. The schematic under this biasing condition is shown in figure 5(a) and the energy band diagram is shown
in figure 5(b).

Figure 5: (a) Schematic of an ideal MOS diode when V >> 0, (b) Energy band diagram of an ideal MOS diode
when V >> 0

In this biasing condition, minority carriers (ns) becomes more than majority charge carriers.

The electron concentration in p-type material is

𝑛𝑝 = 𝑛𝑖 𝑒 (𝐸𝐹 −𝐸𝑖 )/𝐾𝑇 (5)

Since, Ei - EF > 0 (in inversion) i.e. when Ei crosses EF at large V.

=> np ] at surface > ni
and pp ] at surface < ni (from 2, EF – Ei > 0)

Therefore, surface of p-type is inverted. [Inversion condition].

Once, inversion occurs at the surface: Further increase in V will induce practically all additional negative
charges in the incversion layer.
Therefore, electron concentration in surface space-charge region increases rapidly with applied V in narrow region
0 < x < x1, and depletion region width reaches a maximum (Wm). [Because when bands bend downward far enough
for strong inversion to occur, a very small increase in band bending (corresponding to a very small increase in W)
results in a large increase in Qn in the inversion layer]. Thus, under a strong inversion condition, the charge per
unit area in semiconductor is
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MOS capacitors
 𝑄𝑠 = 𝑄𝑛 + 𝑄𝑠𝑐 (6)
where, 𝑄𝑠𝑐 = −𝑞𝑁𝐴 𝑊𝑚 (𝑐ℎ𝑎𝑟𝑔𝑒 𝑤𝑖𝑡ℎ𝑖𝑛 𝑊𝑚) (7)
Wm is the width of surface depletion region.
Qn is the inversion layer charge per unit area and is negative.
Here, xi << Wm.
Here, n- and p- regions are separated by depletion region [like in pn junction], howeverjunction is obtained by
applying field normal to surface and thus field induced junction.
4. Detailed analysis of surface space-charge region:

The electrostatic potential p, defined as zero in the bulk of semiconductor. At surface, p = sp which is surface
potential.
𝐸𝑖 −𝐸𝐹𝑝 = 𝑞𝜓𝐵𝑝 𝑓𝑜𝑟 𝜒≥𝑊 𝑏𝑢𝑙𝑘
} (8)
𝑎𝑛𝑑 𝐸𝑖 −𝐸𝐹 = 𝑞(𝜓𝐵 −𝜓) 𝑓𝑜𝑟 𝜒<𝑊 𝑏𝑢𝑙𝑘

Figure 6: Energy bands of p-type semiconductor surface in the MOS

Therefore, hole concentration (po) in the neutral semiconductor bulk, away from the surface is
𝑝𝑜 = 𝑁𝐴 = 𝑛𝑖 𝑒 𝑞𝜓𝐵 /𝑘𝑇 (9)
(from 2 and 7 and assuming all NA are ionized)
=>Electrostatic potential at the Fermi level w.r.t. Ei in neutral semiconductor region is

Semiconductor Materials and Devices

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MOS capacitors
 𝑘𝑇 𝑁𝐴
𝜓𝐵𝑝 = 𝑙𝑛 (10)
𝑞 𝑛𝑖

Similarly, the hole concentration in the semiconductor as a function of  is

𝑝𝑝 = 𝑛𝑖 𝑒 𝑞(𝜓𝐵 −𝜓)/𝑘𝑇 (11)

and electron concentration in semiconductor as a function of  is

𝑛𝑝 = 𝑛𝑖 𝑒 𝑞(𝜓−𝜓𝐵 )/𝑘𝑇 (12)

where  > 0 where band is bend downwards.

Also, at the surface, densities are [ = s]:

𝑛𝑠 = 𝑛𝑖 𝑒 𝑞(𝜓𝑠 −𝜓𝐵 )/𝑘𝑇 (13) (from 11)
and 𝑝𝑠 = 𝑛𝑖 𝑒 𝑞(𝜓𝐵 −𝜓𝑠 )/𝑘𝑇 (14) (from 10)
= 𝑁𝐴 𝑒 −𝑞𝜓𝑠 /𝑘𝑇 (15) (from 8)

We can infer that if the surface potential of p-type semiconductor in MOS device is
sp < 0 : ps>> ni and ns << ni Accumulation of holes (bands bends upward) (at V < 0)
sp = 0 : Flat-band condition (no bending of bands) Equilibrium condition (at V = 0)
Bp > sp > 0 : ps << ni Depletion of holes (bands bend downward) (at V > 0)
sp = Bp : ns = pi = ni Intrinsic surface (midgap)
sp > Bp : ns >> ni and ps << ni Inversion layer of electrons (bands bend downward) (at V >> 0)
e.g:
1. When hole accumulation occurs (ps > NA) implies s < 0 (from 14).
=> Ei (in bulk) is lower than Ei (surface) => Energy band bend upward.
2. When hole depleted: (ps < NA) => s > 0 (from 14) ; => energy band bend downwards

INVERSION CONDITION: Surface becomes intrinsic when s = B. Therefore, onset of inversion for p-type
semiconductor is given by s > B. Strong inversion occurs when minority carrier concentration at surface (ns)
equals majority carrier concentration in bulk (po = NA). For p-type => ns = no and surface potential for this condition
is s (strong inversion) = 2B (15)
(from 8 and 12) i.e. when Ei at surface comes below EF as much as it is above EF in bulk.

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 5. C-V characteristics of Ideal MOS capacitor:

MOS can be said as parallel plate capacitor with SiO2 dielectric surface charge layer in semiconductor under
metal gate is modified by V.
In the absence of any work function differences, the applied voltage (V) will appear partly across oxide and
partly across semiconductor.
Thus, total applied voltage is 𝑉 = 𝑉𝑜 + 𝜓𝑠 (17)
where, 𝑉𝑜 is the voltage across oxide
𝜓𝑠 in semiconductor
Where potential across oxide is given by
−|𝑄𝑠 | −|𝑄𝑠 |𝜒𝑜
𝑉𝑜 = 𝜉𝑜 𝜒𝑜 = = (18)
𝐶𝑜 𝜖𝑜𝑥
𝜖𝑜𝑥
where o is field in oxide of thickness d, Qs is charge per unit area in semiconductor, 𝐶𝑜 = is oxide
𝜒𝑜
capacitance per unit area. 𝜖𝑜𝑥 is permittivity of oxide layer.
Therefore, from (16) and (17), we have
−|𝑄𝑠 |
𝑉= + 𝜓𝑠 (19)
𝐶𝑜

Differentiate equation 18 w.r.t. to V

1 𝑑𝑄𝑠 𝑑𝜓𝑠 𝑑𝑄𝑠
1=− .( )+ .( )
𝐶𝑜 𝑑𝑉 𝑑𝑄𝑠 𝑑𝑉

1 1 𝑑𝜓𝑠
= −
−(|𝑑𝑄𝑠 /𝑑𝑉|) 𝐶𝑜 𝑑𝑄𝑠

Small signal capacitance C of MOS capacitor is

𝑑𝑄𝑚 −𝑑𝑄𝑠
𝐶= = 𝑤ℎ𝑒𝑟𝑒 𝑄𝑚 = −𝑄𝑠 , 𝑎𝑛𝑑 𝑄𝑚 𝑖𝑠 𝑐ℎ𝑎𝑟𝑔𝑒 𝑜𝑛 𝑚𝑒𝑡𝑎𝑙 𝑠𝑖𝑑𝑒
𝑑𝑉 𝑑𝑉
1 1 1
Therefore, = + (20)
𝐶 𝐶𝑜 𝐶𝑗

𝑑𝑄𝑠 𝜖𝑠
where, 𝐶𝑗 = − = is semiconductor space-charge layer capacitance, 𝜖𝑠 is the permittivity of
𝑑𝜓𝑠 𝑊
semiconductor, and W is the depletion width.
𝐶 1
=> = 𝐶 (21)
𝐶𝑜 1+ 𝑜
𝐶𝑗

For a given oxide thickness (d), Co is constant and independent of applied voltage (V). => if voltage dependent
Cj is known, ratio C/Co can be plotted with V.

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 Figure 7: Variation of charge distribution, field distribution, potential distribution as a function of distance x
5.1 Depletion condition:
The potential  as a function of distance (x) in the space-charge region can be obtained from the solution of 1D
Poisson equation:
𝑑2 𝜓 −𝜌(𝑥)
= (22)
𝑑𝑥 2 𝜖𝑠

where  (x) is total space charge density. Here, we shall use the depletion region approximation (used in p-n
junction under reversed- biased). When semiconductor is depleted
𝜌𝑠 = −𝑞𝑁𝐴
𝑑2 𝜓 𝑞𝑁𝐴
Therefore, =
𝑑𝑥 2 𝜖𝑠

𝑑𝜓
Integrate with boundary conditions, = 0 and 𝜓 = 0 at x = w, we have
𝑑𝑥

𝑑𝜓 𝑞𝑁𝐴
= (𝑥 − 𝑊)
𝑑𝑥 𝜖𝑠
𝑥
𝜓(𝑥) = 𝜓𝑠 (1 − )2 (23)
𝑊

𝑞𝑁𝐴 𝑊 2
where surface potential 𝜓𝑠 = (24)
2𝜖𝑠

The criterion for onset of strong inversion is

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 𝜓𝑠 (𝑖𝑛𝑣. ) = 2𝜓𝐵 (25)
Here, surface depletion layer width reaches a maximum (Wm) given as
2𝜖 𝜓 (𝑖𝑛𝑣.)
𝑊𝑚 =√ 𝑠 𝑠
𝑞𝑁𝐴
} (26) (from 24 and 25)
4𝜖𝑠 𝜓𝐵𝑝
=√
𝑞𝑁𝐴

4𝜖𝑠 𝑘𝑇 𝑁𝐴
𝑊𝑚 = √ ln ( ) (27) (from 26)
𝑞2 𝑁 𝐴 𝑛𝑖

In depletion region in inversion, the total charge per unit area:

𝑄𝑠𝑐 = −𝑞𝑁𝐴 𝑊𝑚 ≈ √2𝑞𝜖𝑠 𝑁𝐴 (2𝜓𝐵 ) (27) (from 25)

For V > 0, depletion region: equation (18) for 𝑄𝑠𝑐 = −𝑞𝑁𝐴 𝑊 becomes
𝑞𝑁𝐴 𝑊
𝑉= + 𝜓𝑠 (28)
𝐶0
𝑞𝑁𝐴 𝑊 𝑞𝑁𝐴 𝑊 2
𝑉 = + (29)
𝐶0 2𝜖𝑠
𝜖𝑠 𝜖𝑠
But space charge layer capacitance is 𝐶𝑗 = , put value o 𝑊 = f in
𝑊 𝐶𝑗

𝑞𝑁𝐴 𝑊 𝑞𝑁𝐴 𝑊 2
𝑉 = +
𝐶0 2𝜖𝑠
we get,
𝑞𝜀𝑠 𝑁𝐴 𝑞𝜀𝑠 𝑁𝐴
𝑉= +
𝐶𝑜 𝐶𝑗 2𝐶𝑗 2
𝑉 1 1
= +
𝑞𝜀𝑠 𝑁𝐴 𝐶𝑜 𝐶𝑗 2𝐶𝑗 2
2𝑉𝐶𝑜 2 2𝐶𝑜 𝐶𝑜 2
=> = + [multiply both sides by 2𝐶𝑜 2 ]
𝑞𝜀𝑠 𝑁𝐴 𝐶𝑗 𝐶𝑗 2

2
2𝑉𝐶𝑜 2 𝐶𝑜
=>1 + = (1 + )
𝑞𝜀𝑠 𝑁𝐴 𝐶𝑗

1 1 1
2𝑉𝐶𝑜 2 𝐶𝑜− 𝐶 2 𝐵𝑒𝑐𝑎𝑢𝑠𝑒 = + 𝑒𝑞𝑢𝑎𝑡𝑖𝑜𝑛 19
𝐶 𝐶𝑗 𝐶𝑜
1+ = [1 + 𝐶𝑜 ( )] [ 1 1 1 𝐶 −𝐶
]
𝑞𝜀𝑠 𝑁𝐴 𝐶𝐶𝑜 => = − = 𝑜
𝐶𝑗 𝐶 𝐶𝑜 𝐶𝐶𝑜

𝐶𝑜 2
=( )
𝐶

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 𝐶 1
= (30)
𝐶𝑜
2𝑉𝐶𝑜 2
√1+
𝑞𝜀𝑠 𝑁𝐴

𝐶𝐶𝑜
𝐶𝑗 =
𝐶𝑜 − 𝐶
Total capacitance (C) decreases with increase in voltage while surface is being depleted.
5.2 CV curve of an ideal MOS capacitor
CV curve is measured by superimposing a small ac signal ( 5 mV) on dc bias. Figure 8 shows the CV curve of
an ideal MOS capacitor.

Figure 8: CV curve of an ideal MOS capacitor

When V < 0, no depletion region => accumulation of holes at semiconductor surface.
=>Total capacitance
𝜀𝑜𝑥
𝐶 ≈ 𝐶𝑜 =
𝜒𝑜

𝜖
Here, Cj increases [ 𝑠 ] and 𝐶 ≈ 𝐶𝑜
𝐿𝐷
𝜖𝑠
When V > 0, W increases, 𝐶𝑗 = decreases
𝑊

 C decreases

When V >> 0 ( VT), W  Wm. No change in W with V. Therefore, at

V = VT, s  s (inv.)
The threshold voltage at on-set of strong inversion.
𝑞𝑁𝐴 𝑊𝑚
𝑉𝑇 = + 𝜓𝑠 (𝑖𝑛𝑣)
𝐶𝑜
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 √2𝜖𝑠 𝑞𝑁𝐴 (2𝜓𝐵 )
= + 2𝜓𝑠 (31) (from equation
𝐶0
28 and 27)
𝑄𝑠
=− + 𝜓𝑠 (𝑖𝑛𝑣)
𝐶𝑜
𝜖𝑠 𝜀𝑜 𝑥
At strong inversion: 𝐶𝑗 = and 𝐶𝑜 =
𝑊 𝜒𝑜

Minimum capacitance is
𝜀 𝜀 𝑥
𝐶𝑜 𝐶𝑗 ( 𝑠 )( 𝑜 ) 𝜀𝑜 𝑥
𝑤𝑚 𝑑
𝐶𝑚𝑖𝑛 = = 𝜀 𝜀 𝑥 = 𝜀 𝑥 (32)
𝐶𝑜 +𝐶𝑗 𝑠
+ 𝑜
𝑑 + ( 𝑜 ) 𝑤𝑚
𝑤𝑚 𝑑 𝑑
In depletion or accumulation regimes, change in charge in response to applied signal requires the flow of majority
carriers (holes in p-type) i.e. moves in or out of space space-charge region.
The relaxation time, c, (time constant for charge transport)  10-12 sec for signal frequency. When
where c << 1, thus C-V curve (accumulation of depletion) is frequency independent.
However, in INVERSION regime: charge flow in response to applied signal may also occur by movement of
minority carriers between inversion layer and the neutral semiconductor, and MOS shows strong frequency
dependence.
If frequency is low so that generation-recombination rates in surface depletion region are equal or faster than
gate.
Voltage variation, then minority carriers (electrons) can follow the applied signal and lead to charge exchange
with inversion layer in step with signal. If e-h pairs generated in Wm before VG goes to zero, the generated holes
will fill hole vacancy in Wm, while generated electron will move into inversion layer. Wm decreases, therefore Cj
= s/Wm start increasing, and total capacitance C will be equal to Co at low frequency (< 100 Hz). All these
considerations are also valid for n-type substrate with proper change in signs and symbols. C-V curve will be of
identical shape (mirror images of each other), and threshold voltage (V T) is a negative quantity for an ideal MOS
diode on an n-type substrate.
5.3 Frequency dependence of CV curve of MOS capacitor
 In low frequency (curve (a)), the generation-recombination rates in depletion region are equal or faster
than variation in applied voltage (V) implying that minority carriers follows the applied signal and lead
to charge exchange with inversion layer in step with signal. (Here, W = Wm, and electron goes to
inversion layer).

Since, Cinv >> CD (because Wm >>> LD) Cinv is the inversion layer capacitance and CD is the depletion
layer capacitance
C  Co (because Cinv >> Co)

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  At higher frequency: For small ac signal, thermal generation cannot create minority carriers fast enough
to support a variation of charge in inversion layer with applied V implying that CV in inversion part is
different. The variation in V (V) results in variation in depletion charge and depth i.e. Wmax  W,
where W is small modulation in W due to applied small ac gate bias (V)

 C is series combination of Co and CD = s / Wm and CD is almost constant and hence giving low and
constant value of C ( because Wm is large and CD is low)

6. Practical MOS (SiO2-Si MOS diode)

In practical MOS,

 difference in the work function of metal and semiconductor is not zero (ms = ms -ms  0 at VG =
0)

 interface traps and charges are present in the oxide layer.

Figure 9: Band diagram at thermal equlibrium

6.1 Interface traps and charges in oxides
The average distance between the oxygen atoms in the oxide is larger than the distance between the silicon
atoms in the silicon. This means that some of the interface atoms from the silicon cannot create Si–O bonds
because they are missing oxygen atoms. The atoms from the silicon that remain bonded only to three silicon
atoms with the fourth bond unsaturated (trivalent interfacial silicon atoms) represent interface defects. The
energy levels associated with the fourth unsaturated bond of the trivalent silicon atoms do not appear in the
conduction or the valence band, but rather in the silicon energy gap. It is believed that every trivalent silicon
atom introduces a pair of energy levels; one can be occupied by an electron (acceptor type), and the other can
be occupied by a hole (donor type). Electrons and holes that appear on these levels cannot move freely because

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 there is a relatively large distance between the neighboring interfacial trivalent silicon atoms (these levels are
localized and isolated from each other). Because these levels can effectively trap mobile electrons and holes,
they are called interface traps. Impurity atoms and groups (such as H, OH, and N) can be bonded to the
unsaturated bonds of the interfacial trivalent silicon atoms, which results in a shift of the corresponding energy
levels into the conduction and the valence bands. Although this process effectively neutralizes the interface
traps, it is not possible to enforce such a saturation of all the interfacial trivalent silicon atoms, which means
that the density of the interface traps can never be reduced to zero. The interface trap density will be denoted
by Qit to express the number of interface trap per unit area (in m−2), or by qQit to express the associated charge
per unit area (in C m−2). Trivalent silicon atoms can also appear in the oxide; these are silicon atoms bonded
to three neighboring oxygen atoms with the fourth bond unsaturated. There are also a number of other possible
defects in the oxide: non bridging oxygen, oxygen vacancy, interstitial silicon, silicon vacancy, and interstitial
oxygen.
The oxide defects introduce energy levels in the oxide energy gap, which can trap electrons and holes. The
charge due to the trapped electrons and holes onto the oxide defects is referred to as the oxide charge. Although
the oxide traps do not continuously exchange electrons and holes with the silicon, the oxide charge does affect
the electrons and holes in the silicon by its electric field. In general the oxide charge is usually positive and is
mostly located close to the oxide–silicon interface.

7. Summary
 The two conditions for an ideal MOS diode and its energy band diagram at zero applied
bias voltage were discussed.
 The negative applied bias voltage (-V) on the gate produces equal and opposite charges in
the semiconductor by attracting holes near the oxide-semiconductor interface and thus there
is an enhanced concentration of holes known as Surface accumulation condition.
 For a small positive applied voltage, holes are pushed away from oxide interface and there
is a formation of depletion region in semiconductor near interface, having mainly negative
charged acceptor (Na) ions known as Depletion Condition.
 For a large positive applied voltage, the conduction band comes closer to EF instead of
valence band i.e. minority carriers (electrons) are attracted to interface, semiconductor
surface contains more electrons than holes. Surface gets inverted from p-type to the n-type
and this is known as inversion condition.
 CV curve of an ideal MOS capacitor is discussed under three conditions accumulation,
depletion and inversion. In inversion regime, the CV curve shows the frequency
dependence of the applied signal.
 SiO2-Si MOS diode i.e. practical MOS along with the interface traps and charges in oxides
were discussed.

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