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The fundamental physics of the Metal-Oxide-Semiconductor FieldEffect Transistor (MOSFET) is developed in this chapter. The MOSFET is used extensively in digital circuit applications where, because of its relatively small size, thousands of devices can be fabricated in a single integrated circuit. The MOS designation is used for the metal-silicon dioxide (SiO2)silicon system. The heart of the MOSFET is a MOS capacitor. The energy band bending near the oxide-semiconductor interface is a function of the voltage applied across the MOS capacitor. Thus the material can be inverted from n-type to p-type (and vice versa) by applying the proper voltage.

Chapter 11
Fundamental of the Metal-Oxide-Semiconductor Field-Effect Transistor

Section 11.1 The Two-Terminal MOS Structure The figure shows a metal-oxide semiconductor capacitor. The metal may be aluminum or some other metal, although in many cases, it is actually a high conductivity polycrystalline silicon deposited on the oxide.

Section 11.1.1 Energy-Band Diagrams

The physics of the MOS structure can be more easily explained by the comparison to the simple parallel-plate capacitor.

Oxide thickness tox

An insulator (dielectric) separates the two plates. A dielectric material is a substance that is a poor conductor of electricity, but an efficient supporter of electrostatic fields. If the flow of current between opposite electric charge poles is kept to a minimum while the electrostatic lines of flux are not impeded or interrupted, an electrostatic field can store energy.

Energy-Band Diagrams

Energy-Band Diagrams

The magnitude of the charge per unit area on either plate is

E= V d

With the bias voltage as shown, a negative charge exists on the top plate, a positive charge exists on the bottom plate, and an electric field is induced between the two plates.

The capacitance per unit area is

C' =

Permittivity of the dielectric separation of the two plates

In the above MOS capacitor, an accumulation layer of holes in the oxide-semiconductor junction corresponds to the positive charge on the bottom plate.

The magnitude of the charge per unit area on either plate is

Q ' = C 'V

Energy-Band Diagrams

Energy-Band Diagrams

Now the polarity of the applied voltage is reversed. A positive charge now exists on the top metal plate and the induced electric field is in the opposite direction. The exposed ionized acceptor ions will now have a negative charge near the metal-semiconductor junction. There will be an induced depletion region.

The energy-band diagram shows that for the case of negative voltage applied to the top metal plate, the valence-band edge is closer to the Fermi level at the oxide-semiconductor interface than in the bulk material.

This implies an accumulation of holes.

Energy-Band Diagrams

Energy-Band Diagrams

When the positive voltage is applied, the conduction and valence band edges bend. This is similar to the depletion in a pn junction.

If a still larger positive voltage is applied to the top metal gate. We would expect the induced electric field to increase in magnitude and the separated charge to increase.

The induced depletion layer width is xd.

The intrinsic Fermi level at the oxide-semiconductor junction is now below the Fermi level. The conduction band is now closer to the Fermi level than the valence band is. Thus the surface of the junction is now n-type. The voltage created an inversion layer of electrons at the oxidesemiconductor interface.

Energy-Band Diagrams

Section 11.1.2 Depletion Layer Thickness The figure below shows the depletion region adjacent to the oxidesemiconductor interface.

There is a complementary effect if the bulk region is n-type. Read pages 453-455 for the discussion of n-type MOS.

The potential fp is the difference (in volts) between EFi and EF.
fp = Vt ln
Na ni

The potential s is called the surface potential; it is the difference (in volts) between EFi measured in the bulk semiconductor and EFi measured at the surface at the metal-semiconductor junction.

Depletion Layer Thickness s is the potential difference across the depletion region. Thus the depletion region width is
xd = 2 ss eN a

Figure 11.9

The last equation assumes the abrupt depletion approximation is valid. In the next figure, we see the case for the Fermi level at the surface is as far above the intrinsic level as the Fermi level is below the intrinsic level in the bulk semiconductor. We

The Fermi level at the surface is as far above the intrinsic level as the Fermi level is below the intrinsic level in the bulk semiconductor.

Depletion Layer Thickness For this case, the electron concentration at the surface is the same as the hole concentration in the bulk material. This condition is known as the threshold inversion point. The applied gate voltage creating this condition is known as the threshold voltage. While the conduction band may bend slightly with further increase in the gate voltage, beyond threshold the change in both the band bending and the depletion region width is very small. However the electron concentration is an exponential function of the surface potential with will increase by many orders of magnitude as the gate voltage increases from threshold.

Depletion Layer Thickness The maximum depletion region width xdT, at this inversion transistion point is 2 s (2 fp ) 4 s fp
xdT = eN a = eN a

This condition is known as the threshold inversion point.

The applied gate voltage creating this condition is known as the threshold voltage.

Exercise 11.1 on page 458

Oxide to p-type silicon junction at T = 300 K. Na = 3 x 1016 cm-3 Calculate the maximum depletion region width in the silicon.
N 3 1016 cm 3 fp = Vt ln a = (0.0259V ) ln = 0.376V 10 3 1.5 10 cm ni

Depletion Layer Thickness The same maximum induced depletion region width also occurs in an n-type substrate. Thus
fn = Vt ln
Nd ni

xdT =

4 s fp eN a

F 4(11.7)(8.85 1014 cm )(0.376V ) 19 (1.602 10 C )(3 1016 cm 3 )

xdT =

4 s fn eN d

= 1.8 105
5

FVcm 2 C

= 1.8 105 cm

CV V C

Figure 11.10 shows this case.

= 1.8 10 cm = 0.18 m

Figure 11.10

Figure 11.11

Section 11.1.3 Work Function Differences

Work Function Differences This figure is the energy band diagram of the entire metaloxide-semiconductor structure with zero gate voltage. m is a modified metal work function the potential required to inject an electron from the metal into the conduction band of the oxide. In the semiconductor we also modify to which the difference in energy between the bottom of the semiconductor conduction band to the vacuum level of the oxide.

The metal work function is m. The electron affinity is which in this case is the energy from the bottom on the conduction band to the vacuum level. (see chemistry for its electron affinity definition) The text defines the oxides electron affinity as i. For silicon dioxide i =0.9 V.

Work Function Differences The voltage Vox0 is potential drop across the oxide for zero applied gate voltage. It is not necessarily zero due to the difference between m and . The potential s0 is a the surface potential for this case. The sum of the energies from the Fermi level on the metal side to the Fermi level on the semiconductor, we have e ' + e + eV = e + e + Eg e and e = e '+ e i m i ox 0 fp s0
thus e + e i + eVox 0
' m

Work Function Differences

Eg ' es 0 em + eVox 0 = e fp + e '+ 2
' m + Vox 0 = fp + '+

Eg s 0 2e

The last equation now in terms of voltage rather than energy.

' Vox 0 + s 0 = m + '+

Eg 2e

+ fp

We can define a potential as the metal-semiconductor work function.

' ms = m '+

Eg = e fp + e '+ e i + es 0 2

Eg 2e

+ fp

Example 11.2 on page 459 Aluminum-silicon dioxide junction at T = 300 K. m = 3.2 V = 3.25 V Eg = 1.11 eV The silicon is p-type with doping Na = 1014 cm-3. Calculate the metal-semiconductor work function.

Work Function Differences Degenerately doped polysilicon deposited on the oxide is often used as the metal gate. For the n+ polysilicon gate, the metal-semiconductor work function difference is
ms = ' '+
Eg 2e Eg + fp = + fp 2e

fp = Vt ln

Na 1014 cm 3 = 0.228V = (0.0259V ) ln 10 3 1.5 10 cm ni

For the p+ polysilicon gate, the metal-semiconductor work function difference is

ms = '+

With all the variables above, we can now sum for the solution.

1.11 ' + 0.228 = 0.833V + fp = 3.2 3.25 + ms = m '+ 2 2e

Eg

Eg Eg Eg fp + fp = '+ 2e e 2e

The value of ms will become more negative as the doping of the p-type substrate increases.

Figure 11.13

Figure 11.14

n + polysilicon gate

Energy band diagram for n-type substrate.

p-type substrate

p + polysilicon gate

n-type substrate

Figure 11.15

Section 11.1.4 Flat-Band Voltage

Metal-semiconductor work function difference versus doping for aluminum, gold, and n+ and p+ polysilicon gates.

The flat-band voltage is defined as the applied gate voltage such that there is no band bending in the semiconductor.

There is no net space charge in this region.

Because of the work function difference and also from the possible trapped charge in the oxide, the voltage across the oxide for this case is not necessarily zero. In the work so far, we have assumed that there is zero note hcarge density in the oxide material. A net fixed charge density, usually positive, may exist in the insulator. This is due to broken and dangling covalent bonds near the oxide-semiconductor surface.

Section 11.1.4 Flat-Band Voltage

Figure 11.17

Silicon dioxide will form naturally, but it is the annealing of the semiconductor that leaves a consistent volume of oxide. Annealing is classically a process of heat in an oxidizing atmosphere. Not all of the covalent bonds will find mates in the annealing process. Thus the net charge is rarely zero. The net charge appears to be located fairly close to the oxidesemiconductor interface. We will define this charge in the oxide as Qss. Since there is a zero net charge in the semiconductor, for charge neutrality there must be an equivalent opposite charge in the metal.
' ' Qm + Qss = 0

Section 11.1.4 Flat-Band Voltage

Exercise 11.6 on page 465

MOS structure on p-type substrate Na = 3 x 1016 cm-3 SiO2 insulator thickness tox = 200 and ox = 3.9 from table B.6 Let Qss = 8 x1010 charges/cm2. ms = -0.981 from exercise 11.3 Calculate the flat-band voltage. First we need the capacitance of the oxide, C = A/d or, in terms of unit area, it is
Cox =

We can relate Qss to the voltage across the oxide from

Vox = Q Cox
' m

Where Cox is the oxide capacitance per unit area. '

Qss Vox = Cox

ox
tox

In the flat-band condition, the surface potential s = 0.

VGate = Vox + s + ms VG = VFB = ms
' Qss Cox

F 3.9(8.85 1014 cm ) = 1.73 107 200 108 cm

F cm2

VFB = ms

VFB is called the flat-band voltage.

' Qss (1.602 1019 C )(8 1010 / cm2 ) = 0.981 F Cox 1.73 107 cm2

= 0.981 0.074 = 1.06V

Section 11.1.5 Threshold Voltage

Threshold Voltage

The threshold voltage was defined as the applied gate voltage required to achieve the threshold inversion point. The threshold inversion point was in turn defined for when the surface potential voltage s = 2 fp for the p-type material and s = 2 fn for the n-type. In this section the threshold voltage will be derived in terms of the electrical and geometrical properties of the MOS capacitor.

The charge distribution through the MOS device at the threshold inversion point for a p-type semiconductor substrate is shown below. The depletion region width has reached its maximum value.
' ' ' ' QmT + Qss = QSD (max) where QSD (max) = eN a xdT

The energy-band diagram of the MOS system with an applied positive gate voltage. The applied gate voltage will change the voltage across the oxide and will change the surface potential.

Threshold Voltage

Threshold Voltage

VG = Vox + s = Vox + s + ms

At threshold we define VG = VTN where VTN is the threshold voltage that creates the electron inversion layer charge.
VTN = VoxT + 2 fp + ms

The last equation can be express in terms of the flat-band voltage.

t ' ' VTN = QSD (max) Qss ox + 2 fp + ms ox

Where VoxT is the voltage across the oxide at this threshold inversion point and can related to the charge on the metal and to the oxide ' capacitance by Q' Q ' (max) Qss VoxT = mT = SD Cox Cox
VTN =
' ' QSD (max) Qss t ' ' + 2 fp + ms = ( QSD (max) Qss ) ox Cox ox

' QSD (max) ' t + ms Qss ox + 2 fp ox Cox Q ' (max) = SD + VFB + 2 fp Cox

+ 2 fp + ms

For a given semiconductor material, oxide material, and gate metal, the threshold voltage is a function of semiconductor doping, oxide charge Qss, and oxide thickness.

Example 11.4 on page 467 n+ polysilicon gate and a p-type silicon substrate at T = 300 K. Na = 3 x 1016 cm-3 ox = 3.9 from table B.6 Qss = 1011 cm-2. From figure 11.15 ms = -1.13 V (or about so!) Determine the oxide thickness so that VTN = +0.65V.

Example 11.4 on page 467 The oxide thickness can be determined from the threshold voltage equation.
' ' VTN = QSD (max) Qss

) t
(

ox ox

+ ms + 2 fp
11 1 cm 2

0.65 = 8.64 10 0.65 =

C cm 2

10

) x (1.6 10

19

tox C (3.9)(8.85 1014

F cm

1.13 + 2(0.376)

fp = Vt ln
xdT =

Na 3 1016 = (0.0259V )(14.51) = 0.3758V = (0.0259V ) ln 10 1.5 10 ni

=
F C 4(11.7)(8.85 1014 cm )(0.376V ) 1.56 1012 cm = = 0.180 104 cm C (1.6 1019 C )(3 1016 cm 3 ) 4.8 103 cm3

7.04 108 3.45 1013

C cm2 F cm

tox 1.13 + 0.752

V 0.65 = 204, 058 cm tox 1.13 + 0.752

4 s fp eN a

tox =

1.028V V 204, 058 cm

= 5.04 106 cm = 504 A

8 ' QSD (max) = eN a xdT = (1.6 1019 C )(3 1016 cm 3 )(0.18 104 cm) = 8.64 10

C cm2

Example 11.5 on page 468 Aluminum gate and a p-type silicon substrate at T = 300 K. ox = 3.9 from table B.6 for SiO2 Na = 1014 cm-3 Qss = 1010 cm-2. From figure 11.15 ms = - 0.83 V tox = 500 Calculate the threshold voltage.

Example 11.5 on page 468 The threshold voltage is

' ' VTN = QSD (max) Qss

) t
(

ox ox
10

+ ms + 2 fp
1 cm2

= 3.89 109
14

C cm2

10

) x (1.6 10
8

19

500 108 cm C (3.9)(8.85 1014

F cm

0.83 + 2(0.228)

fp = Vt ln
xdT =

Na 3 10 = (0.0259V )(8.8) = (0.0259V ) ln 10 1.5 10 ni =

= 0.228V
= 2.43 104 cm

( 2.29 10

9 C cm2

) ( 500 10
13 F cm

cm

4 s fp eN a

3.45 10

) 0.374

F C 4(11.7)(8.85 1014 cm )(0.228V ) 9.44 1013 cm = C (1.6 1019 C )(1014 cm 3 ) 1.6 105 cm3

= 0.0332 0.374
= 0.341 Volts

9 ' QSD (max) = eN a xdT = (1.6 1019 C )(3 1016 cm 3 )(2.43 104 cm) = 3.89 10

C cm2

Threshold Voltage

Threshold Voltage for n-type substrate

A negative threshold voltage for a p-type substrate implies a depletion mode device. A negative charge must be applied to the gate in order to make the inversion layer charge equal to zero.

The equations for the n-type substrate but now a negative gate is used to induce an inversion layer of holes at the oxide-semiconductor interface.
' ' VTP = QSD (max) Qss

) t

ox ox

+ ms 2 fn

This figure shows the threshold voltage VTN as a function of acceptor doping for various oxide charge values.

' ms = m ' +

Eg 2e

fn

' QSD (max) = eN d xdT

xdT =

4 s fn eN d

N and fn = Vt ln d ni

Threshold Voltage for n-type substrate

Section 11.1.6 Charge Distribution The electron concentration in the inversion layer (p-type substrate) at the oxide interface is given by

This plot shows the donor doping for values of oxide charge. As the Qss charge increase, the threshold voltage becomes more negative, which means that it takes a larger applied gate voltage to create the inversion layer of holes in the oxide-semiconductor interface.

ns =

ni2 exp s Na Vt

The electron concentration at the surface increases rapidly with very small changes in surface potential. This implies that the depletion region width has essentially reached its maximum value.

Section 11.1.6 Charge Distribution The total charge density the surface potential. (C/cm2) in silicon is shown as a function of

Exercise 11.10 on page 474 MOS Device with p+ polysilicon gate and a n-type silicon substrate at T = 300 K. ox = 3.9 from table B.6 Nd = 1015 cm-3 Qss = 8 x 1010 cm-2. From figure 11.15 ms = +0.97 V tox = 220 Determine the threshold voltage VTP.

At flat-band, the total charge is zero. For 0 s fp, The device is operating in the depletion mode since the inversion charge has not yet been formed. For fp s 2 fp, The Fermi energy at the surface is in the upper half of the band diagram (implies n-type material now) but not at threshold inversion point yet. For s > 2 fp, the device is in strong inversion.

fn = Vt ln
xdT =

Nd 1015 = (0.0259V )(11.11) = 0.288V = (0.0259V ) ln 10 ni 1.5 10

4 s fn eN d

C F 4(11.7)(8.85 1014 cm )(0.288V ) 1.193 1012 cm = = 86.3 106 cm C 1.6 104 cm3 (1.6 1019 C )(1015 cm 3 )

' QSD (max) = eN d xdT

= (1.6 1019 C )(1015 cm 3 )(86.3 106 cm)

C cm 2

= 1.38 108

C cm 2

' Qss = (8 1010 cm 2 )(1.6 1019 C ) = 1.28 108

Exercise 11.10 on page 474 The threshold voltage is

VTP = Q (max) Q
' SD

Section 11.2 Capacitance-Voltage Characteristics The capacitance of a device is defined as

' ss

tox
ox

+ ms 2 fn
C cm 2

C=
8 F cm

= 1.38 108

C cm 2

1.28 108
8

220 10 cm (3.9)(8.85 1014

dQ dV

+ 0.97 2(0.288)

( 2.66 10

8 C cm2

) ( 220 10

cm

F 3.45 1013 cm

) + 0.394

Where dQ is the magnitude of the differential change in charge on one plate as a function of the differential change in voltage dV across the capacitor. The capacitance is a small-signal or ac parameter and is measured by superimposing a small ac voltage on an applied dc gate voltage. The capacitance, then, is measured as a function of the applied dc gate voltage.

= 0.170 + 0.394
= +0.224 Volts

Section 11.2.1 Ideal C-V Characteristics First, we will find the ideal C-V characteristics of the MOS capacitor and the in later sections discuss some of the deviations from the ideal. We will initially assume that there is zero charge trapped in the oxide and also that there is no charge trapped at the oxide-semiconductor interface. There are three operating conditions of interest in the MOS capacitor. Accumulation Depletion Inversion The next three figures will show the energy band diagrams for a MOS structure with a p-type substrate.

Figure 11.24 Accumulation Mode

A negative voltage is applied to the gate.

C ' (acc) = Cox =

ox
tox

An accumulation layer of holes in the semiconductor is induced by this negative voltage. The differential changes in charge occur at the edges of the oxide (just as in a parallel plate capacitor).

Figure 11.25 Depletion Mode

Depletion Mode

A small positive voltage is applied to the gate.

The total capacitance of the series combination is

1 1 1 = + ' C ' (depl ) Cox CSD

C ' (depl ) =

' Cox CSD ' Cox + CSD

' where CSD is the capacitance of the depletion region.

Cox =

ox
tox

' and CSD =

s
xd

C ' ( depl ) =

1+

The oxide capacitance and the capacitance of the depletion region are in series. A small differential change in voltage will cause a differential change is the depletion region width.

Cox t = ox ox Cox ' CSD 1 + tox

s
xd

ox

tox +

ox ox xd s

As the space charge region width increases, the total capacitance C(depl) decreases.

Depletion Mode

Figure 11.26 Inversion Mode

A positive voltage is applied to the gate.

C ' (inv) = Cox =

ox
tox

The threshold inversion point is the condition when the maximum depletion width is reached, but there is as yet essentially zero inversion charge density. This condition will yield a minimum capacitance Cmin.
' Cmin =

ox tox + ox xdT s
A small incremental change in the voltage across the MOS capacitor will cause a differential change in the inversion layer charge density. The depletion width does not change.

Figure 11.27

Exercise 11.12 on page 478

MOS Device with aluminum gate and a p-type silicon substrate at T = 300 K. Na = 3 x 1016 cm-3 ox = 3.9 from table B.6 Qss = 1011 cm-2. From figure 11.15 ms = +0.97 V tox = 250

Find Cmin/Cox.
fp = Vt ln
xdT = Na 3 1016 = (0.0259V )(14.51) = 0.376V = (0.0259V ) ln 10 1.5 10 ni =
F C 4(11.7)(8.85 1014 cm )(0.376V ) 1.558 1012 cm = = 18.0 106 cm C (1.6 1019 C )(3 1016 cm 3 ) 4.8 103 cm3

4 s fp eN a

The capacitance at flat band is

' CFB =

ox tox + ox Vt s s eN a

' Cmin Cox

ox tox + ox xdT s = ox
tox

tox + ox xdT s

tox

x 1 + ox dT s tox

Exercise 11.12 on page 478

' Cmin 1 1 = = F 1 Cox 1 + ox xdT (3.9)(8.85 1014 cm ) 18 106 cm 1+ F s tox (11.7)(8.85 1014 cm ) 250 108 cm

Exercise 11.12 on page 478

' CFB = Cox

1 1+

ox 1 V s s tox t eN a
1

= 1+

1
F (11.7)(8.85 1014 cm ) 3.9 1 (0.0259) 1 11.7 250 108 cm (1.6 1019 C )(3 1016 cm3 )

1 = 0.294 1 + (0.333)(7.2)

1 1 + 133,333.3 cm 5.587 1012 cm 2

= 0.760

Now find CFB/Cox.

tox +

' CFB = Cox

ox ox Vt s eN a s ox
tox

There is an error in the texts answer for this calculation.

=
1

1 1 + ox V s s tox t eN a

Total Oxide Capacitance

Figure 11.28

Typical values of channel length and width are Length = 2 m and width = 20 m. The total gate oxide capacitance for example 11.7 is then
8 ' Cox (total ) = Cox ( Area ) = (6.28 10 F cm 2

MOS capacitor with n-type substrate

)(2 104 cm)(20 104 cm)

= 2.511014 F = 0.025 pF The total oxide capacitance in a typical MOS device is quite small.

The accumulation condition is obtained for a positive gate bias. The inversion condition is obtained for a negative gate bias.

Section 11.2.2 Frequency Effects There are two sources of electrons that can change the charge density of the inversion layer. The first source is by diffusion of minority carrier electrons from the ptype substrate across the depletion region. This diffusion process is the same as that in a reverse-biased pn junction that generates the ideal reverse saturation current. The second source of electrons is by thermal generation of EHPs within the depletion region. Again the process is the same as that in a reverse-biased pn junction generating the reverse-biased generation current. Both of these processes generate electrons at a particular rate. Thus the electron concentration in the inversion layer cannot change instantaneously.

Frequency Effects If an ac voltage across the MOS capacitor changes rapidly, the change in the inversion layer charge will not be able to respond. The C-V characteristics will then be a function of the frequency of the ac signal used to measure the capacitance. In the limit of a very high frequency, the inversion layer charge will not respond to a differential change in capacitor voltage. The capacitance of the MOS capacitor is then Cmin.
Low frequency is around 5 to 100 Hz for measurement purposes.

High frequency is above 1 MHz for measurement purposes.

Section 11.2.3 Fixed Oxide and Interface Charge Effects In the discussion so far, we have assumed an ideal oxide in which there are no fixed oxide or oxide-semiconductor interface charges (such as dangling bonds, embedded impurities, defect sites, surface interface effects) In the presence of such fixed charge, the flat-band shifts to more negative voltages for net positive fixed oxide charges. Since the oxide charge is not a function of gate voltage, but is a material property, the C-V curves show a parallel shift with the shape of the curve remaining as before.

Figure 11.31

High frequency capacitance versus gate voltage (p-type substrate).

More fixed charge.

Less fixed charge.

Interface Charge Effects In the metal to semiconductor interface, there is an abrupt termination of the periodic nature of the semiconductor. These allowed energy states are referred to as interface states. Charge can flow between the semiconductor and the interface states. The net charge in these interface states is a function of the position of the Fermi level in the bandgap.

Interface Charge Effects In the metal to semiconductor interface, there is an abrupt termination of the periodic nature of the semiconductor. These allowed energy states are referred to as interface states. Charge can flow between the semiconductor and the interface states. The net charge in these interface states is a function of the position of the Fermi level in the bandgap.

Section 11.3 The Basic MOSFET Operation The current in an MOS field-effect transistor is due to the flow of charge in the inversion layer or channel region adjacent to the oxidesemiconductor interface. Previous sections have discussed the creation of the inversion layer charge in enhancement-type MOS capacitors. We may also have depletion-type devices in which a channel already exists at zero gate voltage.

Section 11.3.1 MOSFET Structures There are four basic MOSFET devices types. n-channel enhancement mode MOSFET n-channel depletion mode MOSFET p-channel enhancement mode MOSFET p-channel depletion mode MOSFET

n-channel enhancement mode MOSFET

Figure 11.35 n-channel enhancement-mode MOSFET

In the n-channel enhancement mode, the semiconductor substrate is not inverted directly under the oxide with zero gate voltage. A positive gate voltage induces the electron inversion layer, which then connects the n-type source and the n-type drain regions. The source terminal is the source of carriers that flow through the channel to the drain terminal. In this case, it is electrons that flow, so the conventional current will enter the drain and leave the source (and thus account for the negative charge of the charge carrier).

n-channel depletion mode MOSFET

Figure 11.36 n-channel depletion-mode MOSFET

In the n-channel depletion mode, an n-channel region exists under the oxide with zero volts applied to the gate.

Thus an electron inversion layer already exists even with zero gate voltage applied.

p-channel enhancement mode MOSFET

Figure 11.37 p-channel enhancement-mode MOSFET

In the p-channel enhancement mode device, an negative gate voltage must be applied to create an inversion layer of holes that will conect the p-type source and drain regions. Holes flow from the source to the drain so the conventional current will enter the source and leave the drain.

Figure 11.37 p-channel depletion-mode MOSFET

Section 11.3.2 Current-Voltage Relationship - Concepts The figure shows an n-channel enhancement mode MOSFET with a gate-to-source voltage that is less than the threshold voltage and with only a very small drain-to-source voltage. Source and substrate are held at ground potential. With this bias configuration, there is no electron inversion layer. The drain-to-substrate pn junction is reverse biased. The drain current is zero.

In the p-channel depletion mode, a p-channel region already exists under the oxide even with zero gate voltage.

Current-Voltage Relationship - Concepts Now the same MOSFET has an applied gate voltage VGS > VT. An electron inversion layer has been created. When a small drain voltage is applied, the electrons in the inversion layer will flow from the source to the positive drain terminal. Again, the conventional current is into the drain terminal and out the source terminal. In this ideal case, there is no current through the oxide to the gate terminal.

Current-Voltage Relationship - Concepts For small VDS values, the channel region has the characteristics of a resistor.

I D = g dVDS
Where gd is the channel conductance in the limit as VDS 0.
gd = W n Qn' L

The inversion layer charge is a function of the gate voltage; thus the basic MOS transistor action is the modulation of the channel conductance by the gate voltage. The conductance determines the drain current.

Current-Voltage Relationship - Concepts For small VDS values, the figure shows current ID versus VDS.

Figure 11.40 (a)

I D = g dVDS
When VGS < VT, the drain current = zero. When VGS > VT, the channel inversion charge density increases which increases the channel conductance. R = 1/g. There is a small channel inversion which is essentially constant along the entire channel length.

Figure 11.40 (b)

Figure 11.40 (c)

Now VDS increases. As the drain voltage increases, the voltage drop across the oxide near the drain terminal decreases. The induced inversion charge density near the drain also decreases. The incremental conductance of the channel at the drain decreases.

When VDS increases to the point where the potential drop across the oxide at the drain terminal is equal to VT, the induced inversion charge density = zero at the drain terminal. This is called pinch-off. At this point the incremental conductance at the drain is zero.

VDS ( sat ) = VGS VT

Figure 11.40 (d)

Figure 11.41

When VDS increases beyond VDS(sat), the channel width shrinks towards the source terminal. Electrons that enter at the source travel through the channel toward the drain, then at the point where the charge density goes to zero, the electron are injected in the depletion region near the drain. There to be immediately drifted by the E field to the drain contact.

The previous figures assume VGS remained constant. Here in this figure is the effect of also changing VGS. This is called the family of curves for the transistor.

Current-Voltage Relationship - Concepts

Exercise 11.13 on page 495 n-channel MOSFET n-channel MOSFET n = 650 cm2/V-s tox = 200 W/L = 50 VT = 0.40 V Transistor is biased in the saturation region.

In the nonsaturation region, the drain current is given by

ID =

W n Cox 2 2(VGS VT )VDS VDS 2L W n Cox (VGS VT ) 2 ID = 2L

Find the drain current for VGS = 1 V.

Cox =

ox
tox

(3.9)(8.85 1014 200 108 cm

F cm

) = 1.726 107

F cm 2

In the saturation region, the drain current is given by

ID =

W n Cox 50 F (VGS VT ) 2 = (650 cm )(1.73 107 cm )(1 0.40)2 Vs 2 2L

2 2

F C = (2.81 103 Vs )(0.60V ) 2 = 1.01103 V

V2 Vs

= 1.01 103 mA

The operation of a p-channel device is the same as that of the n-channel device. The charge carrier is the hole and the conventional current direction and voltage polarities are reversed.

For VGS = 2V ID = 7.19 mA For VGS = 3V ID = 19 mA

Exercise 11.15 on page 498 p-channel MOSFET p-channel MOSFET p = 310 cm2/V-s tox = 220 W/L = 60 VT = -0.40 V Transistor is biased in the saturation region. Find the drain current for VSG = 1 V.

Section 11.3.4 Transconductance The MOSFET transconductance is defined as the change in drain current with respect to the corresponding change in gate voltage.

gm =
F cm

I D VGS

The transconductance is sometimes referred to as the transistor gain.

Cox =

ox
tox

(3.9)(8.85 1014 220 108 cm

) = 1.569 107

F cm 2

For an n-channel MOSFET operating in the nonsaturation region, the transconductance increases linearly with VDS but is independent of VGS.

ID =

W p Cox 2L

(VSG + VT ) 2 =

60 2 (310 cm )(1.57 107 Vs 2

F cm2

)(1 0.40) 2

gm =

I D VGS

W nCox VDS L

F = (1.46 103 Vs )(0.60V ) 2 = 0.526 103 mA

For an n-channel MOSFET operating in the saturation region, the transconductance is a linear function of VGS but is independent of VDS.

For VSG = 1.5 V ID = 1.77 mA For VSG = 2 V ID = 3.74 mA

gm =

I D ( sat ) VGS

W nCox (VGS VT ) L

Section 11.3.5 Substrate Bias Effects In the analysis so far, the substrate has been connected to the source and held at ground potential. In MOSFET circuits, the source and body may not be at the same potential.

Figure 11.51 If VSB = 0, threshold is defined as the condition when s = 2 fp. If VSB > 0, the surface will still try to invert when s = 2 fp. However, these electrons are at a higher potential energy than are the electrons in the source. The newly created electrons will move laterally and flow out of the source terminal. When s = 2 fp.+ VSB, the surface reaches equilibrium inversion condition as shown to the right.

The source-to-substrate pn junction must always be zero or reverse biased. Thus VSB 0.

Section 11.3.5 Substrate Bias Effects The depletion region width under the oxide increases from the original xdT value when a reverse-biased source-substrate junction voltage is applied.

Example 11.10 on page 500 n-channel MOSFET at T = 300 K. Substrate doped to Na = 3 x 1016 cm-3. tox = 500 of SiO2 VSB = 1 V Calculate the change in threshold voltage to the applied source-body voltage.

fp = Vt ln

Na 3 1016 = (0.0259V )(14.51) = 0.376V = (0.0259V ) ln 10 1.5 10 ni

Cox =
Thus to reach the threshold condition, the applied gate voltage must be increased. The change in threshold voltage is
VT = 2e s N a Cox 2 fp + VSB 2 fp And is always positive. (for an n-channel) VT =

ox
tox
2e s N a Cox

(3.9)(8.85 1014 500 108 cm

F cm

= 6.9 108

F cm 2

2 fp + VSB 2 fp

2(1.6 1019 )(11.7)(8.85 1014 )(3 1016 ) 2(0.376) + 1 2(0.376) 6.9 108

Example 11.10 on page 500 n-channel MOSFET at T = 300 K. Substrate doped to Na = 3 x 1016 cm-3. tox = 500 of SiO2 VSB = 1 V
VT = 2e s N a 2 fp + VSB 2 fp Cox

Section 11.4 Frequency Limitations

In many applications, the MOSFET is used in a linear amplifier circuit. In order to analyze the circuit, a small-signal model for the MOSFET is needed.

= 1.445 [1.324 0.867 ] = 0.66 V

The equivalent circuit contains capacitances and resistances that introduce frequency effects. A transistor cutoff frequency will then be defined.

Square root drain current versus various values of VSB.

Section 11.4.1 Small-Signal Equivalent Circuit The small-signal equivalent circuit of the MOSFET is constructed from the basic geometry.

Small-Signal Equivalent Circuit

Cgs and Cgd represent the interaction between the gate and the channel charge near the source and drain terminals. Cgsp and Cgdp are the parasitic (or overlap) capacitances. In real devices, the gate oxide will overlap the source and drain contacts because of fabrication tolerances. Cds is the drain to substrate pn junction capacitance. rs and rd are the series resistances associated with the source and drain terminals. The equivalent circuit derivation will assume the source and substrate are both tied to ground potential. The small-signal channel current is controlled by the internal gate-to-source voltage through the transconductance.

Figure 11.54 Small-Signal Equivalent Circuit

Figure 11.56 Simplified Low Frequency Small-Signal Equivalent Circuit

The voltage Vgs is the internal gate-to-source voltage that controls the channel current. The drain current is given by
gm ' Id = Vgs = g mVgs 1 + g m rs

CgsT and CgdT are the total gate-to-source and gate-to-drain capacitances. rds is the slope of ID versus VDS. In the ideal MOSFET biased in saturation, ID is independent of VDS (and would not be needed in the model). It is included here for both short channel and other real world effects.

Section 11.4.2 Frequency Limitation Factors and Cutoff Frequency The are two basic frequency limitation factors in the MOSFET. The first factor is the channel transit time. If we assume that carriers are traveling at their saturation drift velocity vsat, the the transit time is

Frequency Limitation Factors The second limiting factor is the gate or capacitance charging time. The input impedance of the device is not infinite and several of the capacitances are wrapped up in a parameter called the Miller capacitance. The serious effect of the drain overlap capacitance now becomes apparent. This parasitic capacitance is multiplied by the gain of the transistor and can become a significant factor in the input impedance.

t =

L vsat

L is the channel length.

For example, if vsat = 107 cm/s and L = 1 m, then t = 10 ps which translates to a maximum frequency of 100 GHz. This high frequency is rarely approached by actual devices. Thus the transit time of carriers through the channel is usually not the limiting factor in the frequency responses of MOSFETs.

CM = CgdT (1 + g m RL )

Cutoff Frequency The cutoff frequency fT is defined to be the frequency at which the magnitude of the current gain of the devices is unity. This is the point where the input current equals the load current.

Cutoff Frequency Solving for f and calling that frequency fT we have

I i = j (C gsT + CM )Vgs
The ideal load current is

fT =

gm gm = 2 CG 2 (C gsT + CM )

Where CG is the equivalent input gate capacitance.

I d = g mVgs
Thus the magnitude of the current gain (ratio) is For the ideal MOSFET, the cutoff frequency is

Id gm = Ii 2 f (C gsT + CM )
At cutoff this current gain = 1.

fT =

gm 2 CG

W nCox (VGS VT ) L 2 (CoxWL)

n (VGS VT ) 2 L2

1=

gm 2 f (C gsT + CM )

Exercise 11.19 on page 506 n-channel MOSFET at T = 300 K. n = 400 cm2/V-s tox = 200 W/L = 20 VT = 0.4 V VGS = 2.5 V Load is RL = 100 k Calculate the ratio of the Miller capacitance CM to gate-to-drain capacitance CgdT.

Exercise 11.20 on page 507 n-channel MOSFET at T = 300 K. n = 400 cm2/V-s W/L = 20 VGS = 2.5 V Determine the cutoff frequency.
2

Now let channel length L = 0.5m tox = 200 VT = 0.4 V Load is RL = 100 k

Cox =

ox
tox

(3.9)(8.85 10 200 108 cm

14 F cm

) = 1.73 107

F cm 2

fT =

(400 cm )(2.5 0.4) n (VGS VT ) Vs = 2 L2 2 (0.5 104 cm) 2

840 cm s 2 (0.5 104 cm) 2

W g m = n Cox (VGS VT ) = (20)(400)(1.73 107 )(2.5 0.4) = 2.91 mA V L

= 53.48 109 Hz = 53.5 GHz

CgdT (1 + g m RL ) CM A = 1 + g m RL = 1 + (2.91103 V )(100 103 ) = CgdT CgdT

= 292

Section 11.5 The CMOS Technology

Figure 11.59

FOX = field oxide

n well in p-type substrate

We have considered the physics of both n-channel and p-channel enhancement mode MOSFETs. Both devices are used in a complementary MOS (CMOS) inverter which is the basis of CMOS digital logic circuits. The power dissipation in a digital circuit can be reduced to very low levels by using the complementary channel pairs. The next figure will show examples, but the essential detail is that a substrate is doped appropriately to build a well in the substrate of the appropriate n-type or p-type. These wells are separated by a relatively thick field oxide.

p well in n-type substrate

twin wells formed in either an n or p-type substrate

Figure 11.60 CMOS Inverter circuit

End of Chapter 11