Physics of Power Dissipation in CMOS

This chapter begins with a study of the physics of small geometry MOSFET
devices. Many phenomena that are absent in larger geometry devices occur in
submicrometer devices and greatly affect performance and power consump-
tion. These phenomena and \vays of combatL.t'lg their undesirable effects are
described. We begin with the metal-insulator-semiconductor (MIS) struc-
ture in Section 2.2.1. Analytical expressions for the threshold voltage of a
MIS diode, the depth of the depletion region, the quanta of charges in the
inversion layer, and the thickness of the inversion layer are derived. Section
2.2.2 considers the long-channel MOSFET. Impact of the body effect on the
threshold voltage is analyzed. A model of the subthreshold behavior of
MOSFETs is presented and used to estimate the subthreshold current. The
important device characteristic called the subthreshold swing is introduced.
Many phenomena, which are absent in larger geometry devices, occur in
sub-micron devices and greatly affect several aspects of their performance
including their power consumption. These phenomena and ways of combat-
ing their undesirable effects are described in this section. In Section 2.2.3, a
model of the submicrometer MOSFETs based on drain-induced barrier lower-
ing is used to study the shift in the threshold voltage due to the short-channel
effect. Other submicrometer phenomena-na"ow-gate-width effects, substrate
bias dependence, and the reverse short-channel effects-are studied in follow-
ing sections..Section 2.2.3.2 discusses the subsurface punchthrough and ways
of preventing it.
7
This study of the physics of MOSFET devices prepares us for the second
section, which examines various components of overall power consumption in
CMOS very large scale integrated (ruI) circuit The final of
the chapter derives limits on how far we may be able to lower the power
consumption and discusses ways of approaching those limits.
2.2 PHYSICS OF POWER DISSIPATION IN MOSFET DEVICES
2.2.1 The MIS Structure
The stability and reliability of all semiconductor devices are intimately
related to their surface conditions. Semiconductor surface conditions heavily
influence even the basic working of some devices (e.g., the MOSFET).
MIS structure, besides being a device (a voltage variable capacitor and a
diode), is an excellent tool for the study of semiconductor surfaces. In this
section the ideal MIS diode will be discussed. Nonideal characteristics will be
briefly introduced at the end of the section.
Figure 2.1 shows the MIS structure. A layer of thickness d of insulating
material is sandwiched between a metal plate and the semiconductor sub-
strate. For the present discussion, let the semiconductor be of p-type. A
voltage V is applied between the metal plate and the substrate. Let us first
consider the case when V = O. As we are considering an ideal MIS diode, the
energy difference tPms between the metal work function! tPm and the semi-
IThe work function is defined as the minimum energy necessary for a metal electron in a
metal-vacuum system to escape into the vacuum from an initial energy at the Fermi level. In a
metal-semiconductor system, the metal work function may still be used but only with the
free-space permittivity eo replaced by the permittivity e, of the semiconductor medium.
PHYSICS OF POWER DISSIPATION IN MOSFET DEVICES 9
10 PHYSICS OF PO\rAJER DISSIPATION IN CMOS FET DEVICES
Metal
Figure 2.3 Energy bands when a negative bias is applied.
Semiconductor
-- E
c
I I
Insulator Metal
Vacuum level
t----i'---+_ EC
E
8
/2 E.
________________ r
777Z'77;ry;'77I 'I.'I!.L EF
, " " ""
fdi'///////////// E,
Insulator Semiconductor
Figure 2.2 Energy bands in an unbiased MIS diode.
2The electron affinity of a semiconductor is the difference in potential between an electron at
the vacuum level and an electron at the bottom of the conduction band.
3The barrier height is simply the difference between the metal work function and the electron
affinity of the semiconductor.
where X is the semiconductor electron affinity,z E
g
the band gap, cPB the
potential barrier
3
between the metal and the insulator, and I/JB the potential
difference between the Fermi level E
F
and the intrinsic Fermi level E
j

Furthermore, in an ideal MIS diode the insulator has infinite resistance and
does not have either mobile charge carriers or charge centers. As a result, the
Fermi level in the metal lines up with the Fermi level in the semiconductor.
The Fermi level in the metal itself is same throughout (consequence of the
assumption of uniform doping). This is called the flat-band condition as in
the energy band diagram, the energy levels E
e
, E
v
' and E
i
appear as straight
lines (Figure 2.2).
When the voltage V is negative, the holes in the p-type semiconductor are
attracted to and accumulate at the semiconductor surface in contact with the
insulator layer. Therefore this condition is called accumulation. In the
absence of a current flow, the carriers in the semiconductor are in a state o ~
equilibrium and the Fermi level appears as a straight line. The
Maxwell-Boltzmann statistics relates the equilibrium hole concentration to
the intrinsic Fermi level:
._-----Ec
E.
~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ F
Metal Insulator Semiconductor
Figure 2.4 Energy bands when a small positive bias is applied.
So the intrinsic Fermi level has a higher value at the surface than at a point
deep in the substrate and the energy levels E
e
, E
iJ
, and E
i
bend upward near
the surface (Figure 2.3). The Fermi level E
F
in the semiconductor is now
-qV below the Fermi level in the metal gate.
When the applied voltage V is positive but small, the holes in the p-type
semiconductor are repelled away from the surface and leave negatively
charged acceptor ions behind. A depletion region, extending from the surface
into the semiconductor, is created. This is the depletion condition. Besides
repelling the holes, the positive voltage on the gate attracts electrons in the
semiconductor to the surface. The surface is said to have begun to get
inverted from the original p-type to n-type. While V is small, the concentra-
tion of holes is still larger than the concentration of electrons. This is the
weak-inversion condition and is important to the study of power dissipation in
MOSFET circuits. The bands at this stage bend downward near the surface
(Figure 2.4).
If the appiied voltage is increased sut1icientiy, the bands bend far enough
that level E
i
at the surface crosses over to the other side of level EF' This is
(2.1)
(2.2)
cPm, == cPm - ( X + ~ g + l/JJ = 0
." .. \. l,q - /
conductor work function is zero, that is,
12 PHYSICS OF POWER DISSIPATION IN CMOS FET DEVICES
Insulator Semiconductor
------------Ec
_-----Ec
E.
I
E
F / _- ..

777777771 r
Metal Insulator Semiconductor
Figure 2.5 Energy bands in strong inversion.
.............................................. E;

r---
x
Figure 2.6 Energy bands at the insulator-semiconductor surface.
2.2.1.1 Surface Space Charge Region i!'nd the Threshold Voltage
where D, the electric displacement vector, is equal to esE under low-frequency
or static conditions; e
s
is the permittivity of Si; E the electric field vector;
and p(x, y, z) the total electric charge density. In a MIS diode the electric
In this section we will build a mathematical model of the MIS diode. This
model is known as the charge-sheet model [1, 2]. Unlike the simpler model [3]
based on the depletion approximation that is accurate only in the strong-
inversion and beyond regions of operation, the charge-sheet model remains
valid in the weak-inversion and preceding regions of operation. The latter
regions are important when power dissipated in submicrometer MOSFETs
is considered.
We begin with the Poisson equation
(2.5)
(2.6)
(2.4)
pp(x) = ni e
q
(u(x)-4>p)/kT
n
p
( x) = n
i
e
Q
(4)(xl-4>pJ/kT
The Fermi potential epF corresponds to the Fermi energy level E
F
( = -qepF)'
Electrostatic potential is a relative quantity. In the following discussion we
measure electrostatic potential relative to the potential which corresponds to
the intrinsic Fermi energy level in the bulk Ei(x = (0), that is, the absolute
value of ep(x) = ep(x) + ep(oo). We will denote the equilibrium hole and
electron densities in the bulk by ppo( =pp(oo) = n
i
exp q[ epF - ep(oo)}jkT) and
npo, respectively. Simplifying the right-hand sides of (2.5) and (2.6), substitut-
ing in (2.4), mUltiplying both sides of the resulting equation by 2depjdx,
Noting that p(x) = q X [p(x) - n(x) + ND(x) - NA(x)], (2.3) is trans-
formed to
aep aep
E =-. =E =-=0
Y ay Z az
where N
D
is the concentration of donor impurities, N
A
the concentration of
acceptor impurities, n
p
the mobile electron density, and Pp the mobile hole
density. The subscript p is to emphasize that p-type semiconductor is being
considered.. The rNO carrier densities at a point x are related to the intrinsic
carrier density n
i
, Fermi potential epF' and the electrostatic potential ep(x)
according to Boltzmann statistics:
field due to the applied voltage is normal to the insulator (Si0
2
). If the
fringing fields at the edges are neglected, the variation of the electrostatic
potential ep can be considered to be only along the x axis (Figure 2.6), that is,
(2.3) V D = p(x,y,z)
brought about by the tendency of carriers to occupy states with the lowest
total energy. The kinetic energy of electrons is zero when they occupy a state
at the bottom edge of the conduction band. In the present condition of
inversion the level E
i
bends to be closer to level E
e
and electrons outnumber
holes at the surface. The electron density at the surface is still smaller than
the hole density deep inside the semiconductor. When V is increased to the
extent that the electron density at the surface ns becomes greater than the
hole density (z N
A
, the concentration of acceptor impurities) in the bulk,
onset of strong inversion is said to have occurred. This condition is depicted
in Figure 2.5. As we will see in the following section, E
i
at the surface now is
below E
F
by an amount of energy equal to 2lfrB' where lfrB is the potential
difference between the Fermi level E
F
and the intrinsic Fermi level E
i
in the
bulk. The value of V necessary to reach the onset of strong inversion is called
the threshold voltage.
Since c/J(x = co) = 0, part of the applied voltage V appears across the
insulator and the remaining across the semiconductor, or
(Z.12)
(Z.13)
The assumptions made to facilitate the derivation of the expression for the
threshold voltage are never strictly true. In particular, the work function
difference 4>ms is never zero and there may be charges present in the
insulator or at the insulator-semiconductor boundary. The latter include
mobile ionic charges, fIXed oxide charges, interface trap charges, and oxide
trap charges. Let Q
T
be the effective net charge per unit area. The total
voltage needed to offset the effect of nonzero work function difference and
the presence of the charges is referred to as the flat-band voltage V
FB
Hence,
The voltage V that must be applied to reach the onset of strong inversion
must include the flat-band voltage as well. Therefore
The assumptions above and the fact that N
D
= 0 in p-type semiconductor
2.2.1.2 Depth oj Depieiion Region
The MIS structure is in the depletion condition when a small positive bias V
is applied between the metal plate and the semiconductor bulk. The inversion
condition exists when V is large enough as to attract enough minority carriers
(electrons) to the surface that their density exceeds the free-hole density in
the bulk. It is once again assumed that the semiconductor region is uniformly
doped. Two additional simplifying assumptions are invoked. The depletion
assumption allows us to regard the depletion region as being completely
devoid of mobile charges. In the inversion condition the attracted minority
carriers are all assumed to be in a very thin inversion layer near the
semiconductor surface. The one-sided abmpt-junction assumption aiiows us to
regard that the carrier concentrations abruptly change to their intrinsic
values at a distance W beneath the surface, where W is the depth of the
depletion region. The exponential relation (as we will see shortly) between
the total charge in the semiconductor Q
c
and d requires negligible increase
in d in order to balance the increased charge on the metal when V is
increased beyond the onset of strong inversion. Hence it is assumed that d
reaches a maximum value of W
m
and does not increase further. Similarly the
potential at the surface cPs does not increase beyond 24>0'
Once again we start with the Poisson equation
(2.11)
(2.10)
Qs(strong inversion) X d
V
T
= + 24JB
8;
,!2qeJvA .1
Qs = esE
s
= - V /3 ve-Pi/>, + /34J
s
- 1 + e-
2P
t/>B( e pt/>, - /34>s - 1)
(2.9)
rearranging, and integrating from a point deep in the bulk to an arbitrary
point x [4], we get
rX d4J d
2
4J _ rX d I d4J \ 2 _
leo
2
dx dx
2
dx = lee dx tdx J dx
d4> [2iiFi; Ve-Pt/> 1 (ePt/> 1 )
dx = -E(x) = -V -;;- T + 4>- /3 +e-
2p
t/>B {3 - 4>- /3
(2.8)
= l"'zi-(p 0 eqt/>(x)/kT - n eqt/>(x)/kT + N
D
- N
A
) d4J
o es P P
(2.7)
At relatively elevated temperatures, most of the donors and acceptors are
ionized. So Pt "" N
A
and npo "" N
D
= nt/NA' Assuming Boltzmann statistics,
npo = n
i
e-
P
B = Ppo e-
2P
t/>B, where /3 = kT/q. Then
The electric field at the surface E
s
can be obtained by substituting for 4> the
value of the potential at the surface 4>s. To determine the total charges in the
semiconductor Qs' we make use of Gauss's law and obtain
Or,
where C;, e
i
, and d are the capacitance, permittivity, and thickness of the
insulator. At the onset of strong inversion 4>s ... 24>B' and so
PHYSICS OF POWER DISSIPATION IN MOSFET DEVICES 15 16 PHYSICS OF POWER DISSIPATION IN CMOS FET DEVICES
allow us to simplify the above to dropped. Thus,
Integrating twice and applying boundary conditions ep(x = 0) = eps and
ep(x = W) = 0 yields
(2.19)
(2.21)
(2.20)
+ e {3(q,,-2q,B) )
, - ,ff;
f3
From (2.21) and (2.22),
Now the charge per unit area in the semiconductor Q
s
is the sum of the
charge per unit area in the inversion layer Qi and the charge per unit area in
the depletion region Qd' The charge in the depletion region is due to the
acceptor atoms using an extra electron to comolete their covalent bonds.
Therefore, - . -
(2.15)
(2.14)

O::;;x<d
cp( X) = CPs (1 _
2
d
2
cp _ [qN
A
-
ax- to-
Solving for W,
Therefore,

V = W
When W = W
m
, = 2cPB' Therefore,
(2.16)
We noted above that, in the desired range of values of partL"l1eters,
exp( - 1 < Then in weak inversion, where < f3cP
s
>
e{3(q,,-2q,B) and using the first two terms in the Taylor series expansion about
e P(q,,-2 q,o) = 0,
Y
J4BCS
W = --
m qN
A
(2.17)
(2.22)
2.2.1.3 Charge in the Inversion Layer
Substituting in (2.23),
In a nrevious section n _the total chaTire in the semiconductor. was seen to
--- -- c-------- ------- ---- ------0- --- ---- ---------------7 .'-- -------
depend on the parameters of the MIS structure according to the following
relation:
(2.23)
V2qs
s
N
A
,,;
Qs = = - f3 e -{3q" + f34>s -1 + e-
2
{3q,B(e
M
, - f3eps -1)
(2.18)
In this section we will determine the charge in the depletion region due to
the ionized atoms left behind when the holes are repelled away by the
positive potential on the metal and, in tum, the charge in the inversion layer.
The inversion of the semiconductor surface does not begin until 4>s
For the range of doping concentrations used in MOSFETs and for the range
of temperatures of interest, 9::;; f34>B ::;; 16, the other terms in (2.20) are
negligible in comparison with the second and the fourth terms and can be
2.2.1.4 Inversion Layer Thickness
As the next step, we will derive an approximation for the thickness of the
inversion layer. This is done by assuming that the charge density in the
inversion layer is much higher than the density of ionic charge in the bulk
and that the inversion layer is very thin. Thus aE
x
/ ax in the inversion layer
is much greater than in the bulk. Here, Ex!ax can be approximated by
considering the value of the electric field at the bottom edge of the inversion
layer to be zero (Figure 2.7).
The concentration of electrons at some point in the semiconductor is
exponentially dependent upon the potential, with the exponential constant
being f3 = kT/q. This implies that the majority of the charge is contained
within a distance from the surface over which ep drops by kT/q. To illustrate,
1Vertical

IL
tj W
m
x
Figure 2.7 Variation of the vertical electrical
field.
Hence, relative to the sOurce terminal
The V
T
value obtained from the above equation is greater than the one
obtained from Eq. (2.13). This increase in the V
y
when the bulk bias voltage
V
BS
is nonzero is termed the body effect.
2.2.2.2 Subthisshold CU;isnt
or
(2.29)
n; O.J.
n = -eP'Y'
P N
A
Because of the exponential dependence of the minority-carrier concentration
n
p
on the surface potential <P
s
' Bn/y)/By can be relatively large. Since
___.... '\: ..... _
Figure 2.8 "Variation of minority concentration in the channel of a MOSEFET
biased in weak inversion.
In n-channel MOSFETs, when the gate-to-source voltage Vas is less than the
threshold voltage V
y
, the condition identified as weak inversion in the
discussion of the MIS structure exists. The minority-carrier concentration in
the channel is small but not zero. Figure 2.8 shows the variation of minority-
carrier concentration along the length of the channel.
Let us consider that the source of an n-channel MOSFET is grounded,
Vas < V
T
, and the "drain-to-source voltage IV
Ds
l 0.1 V. In this condition
of weak inversion, V
DS
drops almost entirely across the reverse-biased
substrate-drain p-n junction. As a result, the variation along the channel
(the y axis) in the electrostatic potential <Ps at the semiconductor surface is
small. The y component E of the electric field vector E, being equal to
a<pj ay, is also small. With both the number of mobile carriers and the
longitudinal electric field small, the drift component of the subthreshold
drain-to-source current ID,sl" is negligible. In addition, the long channel
aiiows the gradient of the electric field along the channel to also be consid-
ered small and the gradual-channel approximation to be used.
Earlier we observed that if we measure potential relative to the potential
deep in the bulk,
(2.26)
(2.25)
(2.24)
Since in weak inversion <Ps < 2<PB' the expression (2.21) for Qs can be further
simplified by regarding e{3(<p
s
....
2
cfJ
B
) negligible in comparison to 134>s. Then
at the point where the potential drops kTj q below <Ps> the electron density
will have dropped to lie = 0.37 of its value at x = O. Then we can approxi-
mate t
i
by this distance. Furthermore, if the electric field in the inversion
layer is approximated by the ratio of the potential difference across this layer
(::::: i3) divided by its thickness ii'
2.2.2 Long-Channel MOSFET
2.2.2.1 Body Effect
The analysis in the previous section assumes the substrate or the bulk
electrode to be at zero potential and the voltages at the other terminals are
measured with respect to it. When MOSFETs are used in real circuits, the
terminal voltages are expressed with respect to the source terminal and the
bulk, relative to the source, 'may be at a nonzero voltage. Since V
GS
=
V
GB
- VBS' if the potential at the surface when the bulk is at zero potential,
is <P
s
' it becomes <P
s
+ JIBs relative to the source terminal. If the analysis of
the previous section is carried out with potentials measured relative to the
source terminal, the side of Eq. (2.13) is found to be
d
V
PB
+ -,J2qB
s
N
A
(2<PB + V
Bs
)(l - e-
2j3
4>r
V
Bs) + 2<po + V
ss
(2.27)
Bi
diffusion current is proportional to the carrier concentration gradient, carrier
diffusion can and does produce a significant ID,SI' The diffusion current is
given by
an(y) an(y) aQj(Y)
Idiffusion = AJdiffusion = AqD
n
---ay = ZtjqDn ---ay = ZDn ay (2.30)
where A is the cross-sectional area of the channel, D
n
the electron diffusion
coefficient, Z the width of the channel, t
j
the thickness of the inversion layer,
and Qj, the per-unit area charge in the inversion layer, is equal to tjqn(y).
The equilibrium electron concentration is given by
The charge in the inversion layer in the weak-inversion condition can then be
written as
(2.31)
If n; in the right-hand side of the above equation is replaced by its
approximate value expressed as Nl expe - 2qf34>B)' we see that the above
expression is the same as the one derived earlier for Qj:
n _ y2qesN
A
,,/3(</>,-2</>.)
- 2f3{f;" . -
One respect in which a MOSFET differs from a MIS diode is the presence of
a potential gradient along the y axis. With the source grounded (i.e.,
V
SB
= 0), the electron density at the source end of the channel is as given by
the expression above with 4>s(Y) replaced by 4>s(Y = 0). At the drain end of
the channel, however, V
DS
must be considered. Then,
At temperatures higher than room temperature, the exp( - V
DS
/ f3) term is
smaller than exp( - 4). Neglecting this term, the electron concentration gradi-
ent along the channel can be approximated as
Therefore,
qD"Z f3{B; n?
= __-;::=======__' "q/3</>,(Y=O)
L y2qN
A
4>s(Y = 0) N
A
-
It is seen that in long-channel MOSFETs, the subthreshold drain-source
current remains independent of the drain-source voltage. As (My = 0)
varies exponentially with the applied gate voltage [3], so does the drain-source
current. The independence of ID,sl from V
DS
ceases even in MOSFET with
L as large as 2 p,m when V
DS
is large enough that the source and drain
depletion regions merge. This short-channel effect is called punchthrough.
must be prevented as it causes ID,SI to become independent
of ... 11. ThIs normally means that the punchthrough current filust be kept
smaller than the long-channel I D st value. In Section 2.2.3.2, methods of
using implants to control the punchthrough current will be studied.
2.2.2.3 'Subthreshold Swing
The inverse of the slope of the log ID, sl versus V
G
S characteristic is called the
subthreshold swing. For uniformly doped MOSFETs,
where Cd is the capacitance of the gate depletion layer, C
j
the capacitance of
the insulator layer, B
s
the permittivity of the semiconductor, e
j
the permittiv-
ity of the insulator, d the thickness of the insulator, and W the thickness of
the depletion layer. The term SSI indicates how effectively the flow of the
drain current of a device can be stopped when Vas is decreased below V
T

As device dimensions and the supply voltage are being scaled down to
enhance performance, power efficiency, and reliability, this characteristic
becomes a limitation on how small a power supply voltage can be used.
The parameter SSI is measured in millivolts per decade. For the limiting
case of d -) 0 and at room temperature, Sst"'" 60 mV/decade. In practice,
the Sst of a typical submicrometer MOSFET is "'" 100 mV/decade. This is
due to the nonzero oxide thickness and other deviations from the ideal
condition. A SSI of 100 mV/decade reduces the ID,sl from a value of
1 pA/JLm at VGS = V
T
= 0.6 V to 1 pA/p,m at VGS = 0 V.
It can be noted from the above expression for SSI that it can be made
smaller by using a thinner oxide (insulator) layer to redllce d or a lower
substrate doping concentration (resulting in larger W). Changes in operating
conditions, namely lower temperature or a substrate bias, also causes Sst
to decrease.
2.2.3 Submicron MOSFET
Since the invention of integrated circuits (les), both the amount of circuitry
on a chip and the speed the circuitry operates at have continued to grow
exponentially. In order to accommodate larger amounts of circuitry, the
dimensions of the devices-L and Z-have been made progressively smaller.
Continuing to increase the speed of operation of the devices has also
required the dimensions Land d of the devices to be shrunk every genera-
tion. The latter is due to the need to increase I
D
st
, the drain current in the
saturation state of a device, sO that the parasitic capacitances can be charged
and discharged faster.
When ICs incorporating devices with gate length L s; 2 J,Lm were fabri-
cated, effects in the behaviors of the devices were observed that could not be
explained using the prevalent theories of long-channel devices. Of greater
immediate interest to us is the fact that the threshold voltage Vr and the
subthreshold current iD,st predicted by analyses in previous sections are not
in agreement with observed values for the cases of L s; 2 J,Lm. Here, Vr ,
expected to be independent of L, Z, and V
DS
' decreases when L is de-
creased, varies with Z, and decreases when the drain-source voltage VDS is
. increased. Also, V
r
is seen to increase less rapidly with VBS than in the case
of longer channel lengths. In case of devices with L > 2 ,t.tm, ID,sl is
independent of V
DS
and increases linearly as L decreases. Also, ID, st
increases with increasing V
DS
and increases more rapidly than linearly as L
decreases for cases of L s; 2 J,Lm.
In this section we will study the effects that are thought to cause these
differences in the behavior of MOSFETs with smaller dimensions. In most
cases it is not possible to establish an analytical relation between the device
characteristics and device parameters. Prevalent theories attempt to provide
a qualitative explanation or rely on numerical analysis.
2.2.3.1 Effects Influencing Threshold Voltage
The term V
r
, expected to be independent of L, Z, and VDS , decreases when
. L is decreased, varies with Z, and decreases when the drain-source voltage
V
DS
is increased. Also, V
r
is seen to increase less rapidly with Vos than in
the case of longer channel lengths. In this section the short-channel-length
effect, the narrow-gate-width effect, and the reverse short-channel-length
effects and their impacts on the threshold voltage will be examined.
Short-Channel-Length Effect The undesirability of the Vr decrease with
decreasing L and increasing V
DS
cannot be emphasized enough. The en-
hancement mode FETs in CMOS are designed to operate at 0.6 V S; Vr S; 0.8
V. Even a small decrease in Vr causes the leakage currents to become
excessive. Also V
r
values in the range from 0.6 to 0.8 V in MOSFETs with
lightly doped substrates can only be achieved by using Vradjust implants to
increase the doping concentration at the surface. In presence of short-
channel-length effects, an even higher doping concentration may be required
PHYSiCS OF POWEFl DiSSIPATION IN CMOS FET DEVICES
to compensate for the additional V
r
decrease. Higher doping concentration,
however, ?as an adverse effect on carrier mobility, subthreshold current, and
other deVIce characteristics. .
ThA T.I' u,..l... .Q.l" .............. J:_.... _ .L ,_: _ LW. -" ."
AU'" r T .a.u",,, UVUl UIC I1Il<Uy:;t::; III rne prevIous section ana
observed do not agree when L s; 2 J,Lm. The simplifying assumptions
t? facilItate the analyses included that the space charge under the gate
IS not mfluenced by V
DS
' When the channel is relatively long, the drain-
and substr?te-source depletion regions account for only a small
se:t!on of the total dIstance behveen the drain and the source regions.. ""hen
L IS of the same order of magnitude as the width of the drain-substrate or
the depletion region, the ionic charge present in these
regIOns. represents a reduction in the amount of charge the gate
?IaS to contnbute to the total space charge necessary to bring about
InverSIon; A-s a result; a sma!!er Vas appears to suffice to tum on the device..
The drain depletion region expands further into the substrate, making the
tum-on voltage even smaller when the reverse bias across the drain-
substrate junction is increased.
To. the effect of V
DS
on the space charge under the gate, the
two-dImensIonal form of the Poisson equation needs to be solved. Exact
solution of the two-dimensional Poisson equation can only be obtained
To analytically solve the Poisson equation, various simplifica-
tIons have been proposed, One of the first simplifications, the charge-sharing
model [5], the. charge in the channel to be shared among source,
gate, and dram. Assummg the chaf.l!:e controlled bv the gate lies within a
trapezoidal .region, the Poisson is reduced to a- one-dimensional
form solved to obtain the shift in the threshold voltage. This simple
model falls to give good quantitative agreement with observed values.
Drain-induced barrier lowering (DIBL) is the basis for a number of more
complex models of the threshold voltage shift. It refers to the decrease in
voltage due to the depletion region charges in the potential energy
bamer between the source and the channel at the semiconductor surface. In
one DIBL-based model, according to Hsu et aI. [6], the two-dimensional
is reduced to a one-dimensional form by essentially approx-
Imatmg the a 4>/ax
2
term as a constant. This and other DIBL-based models
are capable of achieving good agreement with measured data for L as small
as 0.8 J,Lm and V
DS
as large as 3 V.
A recent model, according to Liu et aI. predicts the short-channel thresh-
old voltage shift accurately even for devices with channel length below
0.5 JLm [7]. Liu et aI. adopt a quasi two-dimensional approach to solving the
Poisson equation. The electric field vector E is regarded as
havI?g a component and a vertical component Ex. The term
E
y
IS the dram field. The dram field has only a horizontal component.
Simil,arly, Ex is due to the charge on the gate and is the only component of
the field due to the charge on the gate. Here, E varies with y but not with
x; Ex assumes its maximum value at the source of the channel and then
24 PHYSICS OF POVaJER DfSS!PP.T!ON !N CMOS FET DEVICES
Invoking the depletion approximation again, the charge in the depletion
region is simply the ionic charge, that is, p(x, y) = qN
A
Substituting these in
the Poisson equation,
varies (decreases) with y to a minimum value at the drain end. Also, Ex(x, y)
has a value at the insulator-semiconductor surface given by Ex(O, y) and goes
to zero at the bottom edge of the depletion region, that is, Ex(W, y) = O.
__ _ t '\ 1
Most Imponanny, 11 IS assumea mat dl!"xl dX at eacn pOlllt \x, yJ can oe
replaced with the average of its value at (0, y) and at (W, y) given by
Furthermore,
(2.40)
1= _! esWmd
V 8;17
where V.L = Vas - V
r
, V
bi
is the built-in potential at the drain-substrate
and substrate-source p-n junctions, and I is the characteristic length
defined as
is now found by subtracting the long-channel value of rP
s
at V
r
from
the minimum of 4>.(y) given by E.q. (2.39). The minimum of 4>.(y) is found by
evaluating the right-hand side of Eq. (2.39) for a handful of values ofy,
o< y < L, plotting and fitting a curve to them. Figure 2.9 shows the
variation of the surface potential along the channel for channel lengths of
0.35 and 0.8 /Lm. For each channel length, surface potential has been plotted
for V
DS
= 0.05 V and V
DS
= 1.5 V.
The surface potential of the device with L = 0.8 /Lm is seen to remain
constant over a significant portion of the channel. This characteristic be-
comes more pronounced in cases of longer channel lengths. The surface
potential of the device with L = 0.35 /Lm, however, does not exhibit a region
where its value is unvarying. The minimum surface potential value for the
device with L = 0.35 /Lm is greater than that for the device with L = 0.8
/Lm. In fact, the minimum value of the surface. potential increases with
decreasing channel length and increasing V
DS
'
(2.33)
(2.34)
(2.35)
EAD,y)
W
E ( ) = Vr - VFB - 4>s(Y)
ox Y d
aE
x
EAO, y) - EAW, y)
-- "" --------
ox W
From the condition of continuity of the electric displacement vector,
where 17 is an empirical fitting parameter and W = W
m
at the onset of strong
inversion. Or,
Under boundary conditions 4>9(0) = V
bi
and 4>9(L) = V
bi
+ V
DS
' the solution
4>s(Y) to the above equation is
0.8 0.6 0.4 0.2
,
L =.8. Vos =1.5 V- II
L= .8. Vos = .05 V---
f L =.35. Vos =1.5 V i
/ L = .35. Vos = .05 V-- !
/ /
/ i
/ i
/ II
.,
/ / ./

.......... -'

3
2
5
o
4
-1 L- --.l ---L --'- -'- .....
o
Figure 2.9 Surface potential along the channel for two lengths.
(2.37)
(2.36)
(2.38)
(2.39)
aE aE p(x, y)
- + - = - ---'---
ax ay 8
9
sinh(YII)
4>s(Y) = V.L + (Vbi + VDS - V.L) sinh(LII)
sinh([L - y lit)
+(V
bi
- V.L) sinh(LII)
we get
and for n-channel MOSFETs with a p+ polysilicon gate [where, assuming
V
r
= 1.2 V, W
m
:= 4(s./ s;)d],
If the expression for the minimum value of tP.(y) is subtracted from the
right-hand side of Eq. (2.39), an expression for AV
r
.
sc
is obtained. The
general form of this expression is complex. When L > 51, the expression for
\V.. __ can be simplified to
- ",.;>y ..
1 = (I (1m Hul 13r1
.. v.vv...... " j U (2.48)
Equation (2.4i) can be further simpiified for smaii vaiues of V
DS
to obtain
The values of V
r
computed from the above two equations have been
compared \!lith measured values [7] and have been found to be in good
(2.49)
Dependence on Vas Equation (2.15), which gives the threshold voltage of a
long channel MOSFET, can be rewritten as
where the e-
2P
q,,-V
BS
term has been dropped as being negligibly small and
'Y = (d/ s)J2qs
s
N
A
For shorter channel lengths and higher drain biases, V
r
is less sensitive to VBS than specified by the above equation. Here, V
r
becomes altogether independent of VBS for all values of VBS when L = 0.7
;.;,m [9J and for large values of VBS in all cases.
(2.42)
(2.41)
avl',se:= [3(V
bi
- 2tP8) + VDS]e-LII
+ 2J(V
bi
- 2tPB)(V
bi
- 2tPB + VJ)S) e-
Lj21
It can be shown that for n-channel MOSFETs with an n+ polysilicon gate, to
maintain V
T
, given by
agreement.
The fitting parameter 11 in the expression [Eq. (Z.37)lforthe characteristic
length 1makes the expression unsuitable for determining the exact value of 1.
The exact value of 1 needs to be obtained from measurements of V
r
carried
out on fabricated devices_
To facilitate empirical determination of I, it can be expressed in an
alternative form by relating it to the minimum channel length L
min
a
MOSFET must have so that it exhibits long-channel characteristics. Brew
et a1. give an empirical expression for L
min
i8]:
(
2)113
L
min
= 0.41 UjdW
m
If it is assumed that L
min
is 4/, then
I = O.1(WjdW";f/3
at a certain value (e.g., 0.7 V), it is necessary that
d 4e
s
rPo 2s
s
W =- z-d
m 8j V
r
- V
FB
- 2r/JB e
j
(2.43)
(2.44)
(2.45)
(2.46)
Narrow-Gate-Width Effects In general, the three narrow-gate-width effects
discussed in this section have a smaller impact on V
T
than the short-channel
effects discussed earlier. The first two effects cause V
T
to increase and are
ex.ltibited in fabricated with either raised isolation
structures or semirecessed local oxidation (LOCOS) isolation structures. The
third effect causes V
r
to decrease and is exhibited in MOSFETs fabricated
with fully recessed LOCOS or trench isolation structures.
To understand the reason behind the first effect, the channel can be
viewed as a rectangle in a horizontal cross section. Two parallel edges border
the drain and the source and therefore, fall on depletion regions. The other
two edges do not have depletion region under them. The presence of charges
under the first two edges brings about a decrease in the amount of charge to
be contributed by the voltage on the gate, so the absence of a depletion
region under the other two edges implies a larger Vas is required to invert
the channel. The effect is an increase in V
T
[10].
The second effect arises from the higher channel doping along the edges
along the width dimension [11]. The higher doping is due to the channel stop
dopants [boron and intentional in case of n-type MOS transistors (NMOST)
and a result of oxidation of the piled-Up phosphorus in case of p-type MOS
transistors (PMOSTs)] encroaching under the gate. Due to the higher doping,
a higher voltage must be applied to the gate to completely invert the channel.
In MOSFETs with trench or fully recessed isolation, when the gate is
biased, the field lines from the region of the gate overlapping the channel are
focused by the edge geometry [12]. Thus an inversion layer is formed at the
edges at a lower voltage than that required for the center and gives rise to
the third effect.
From (2.44) and (2.46),
(2.47)
Reverse Short-Channel Effect Experimental measurements of V
r
with
decreasing channel lengths do not bear out the steady decrease expected
from the theories outlined in the previous two sections. Reverse short-channel
PHYSICS OF POWER D!SS!PAT!ON !N MOSFET DEVICES 27
28 PHYSiCS OF POWER DiSSiPATiON iN CMOS FET DEViCES
effect is the name given to the phenomenon whereby, as the channel length is
reduced from L -- 3 p.m, V
T
initially increases until L -- 0.7 p.m [13]. As L
is decreased below 0.7 p.m, V
T
decreases at a faster rate than predicted by
the theories. Researchers have sought and proposed new explanations [13-19},
and the effects continue to attract further research.
2.2.3.2 Subsurface Drain-Induced Barrier Lowering (Punchthrough)
The depletion regions at the drain-substrate and the substrate-source junc-
tions extend some distance into the channeL Were the doping to be kept
constant as L is decreased, the separation between the depletion region
boundaries decreases. Increase in the reverse bias across the junctions
also leads to the boundaries being pushed farther away from the junction and
nearer to each other. When the combination of the channel length and
junction reverse biases is such that the depletion regions merge, punchthroagh
is said to have occurred. In submicrometer MOSFETs a VT-adjust implant is
used to raise the doping at the surface of the semiconductor to a level above
that in the bulk of the semiconductor. This causes greater expansion in the
portion of the depletion regions below the surface (due to the smaller doping
L'lere) tha..TI at the surface. Thus punchthrough is first established bela'" the
surface.
Any increase in the drain voltage beyond that required to establish
punchthrough lowers the potential energy barrier for the majority carriers in
the source. A larger number of these carriers thus come to have enough
energy to cross over and enter the substrate. Some of these carriers are
collected by the drain. The net effect is an increase in the subthreshold
current ID,st. Furthermore if 10g(ID,s\) is plotted versus Vas' the slope of the
curve (Sst) becomes smaller (i.e., the curve becomes flatter) if subsurface
punchthrough has occurred [20].
While Sst> or rather an increase in its measured value, serves as an
indication of subsurface punchthrough, the device parameter most commonly
used to characterize punchthrough behavior is the punchthrough voltage VPT
defined as the value of V
DS
at which ID 5t reaches some specific magnitude
with Vos = O. The parameter VPT can roughly approximated as the value
of V
DS
for which the sum of the widths of the source and the drain depletion
regions becomes equal to L [21]:
(2.50)
where the bulk doping concentration is represented by N
B
to distinguish it
from the surface doping concentration N
A

The undesirability of subsurface punchthrough currents for low-power
devices cannot be emphasized enough. As these currents flow when the
device is off, even a tiny current represents an unproductive leakage. Several
techniques have been developed for eliminating subsurface punchthrough.
The obvious one is to suitably select N
B
and N
A
, on the one hand, to achieve
the V
T
adjustment, and, on the other hand, to increase the doping in the
substrate to reduce depletion region widths. The rule of thumb proposed by
r""l 'AT ""'" 1\, /1 n '1,...,,;10. ...... .:.t'O n __..._... J... l.. ...... A.. .e
.... llro..&uuu"""u L,w.wJ .." ..t"B r .J. "AI LV. 'f'" UU"" LJUi3 applUaCU Jlas t.Ue aUvanLage Oi.
requiring only one implant, it fails to satisfy the requirements when L < 1
p.m. Therefore, other approaches use additional implants, either to form a
layer of higher doping at a depth equal to that of the bottom of the junction
depletion regions [23] or to form a tip or halo at the leading edge of (toward
the drain for the source and vice-versa) the drain and the source regions
[24,25].
2.2.4 Gate-Induced Drain Leakage
A lame field exists in the oxide in the reaion where the n + of
MOSFET is underneath its gate and -;nd
ground potential, respectively (Figure 2.10).
In accordance with Gauss's law, a charge Q = e E is induced in the
s ox ox
dram electrode. The charge Qs is provided by a depletion layer in the drain.
Because the substrate is at a lower potential for the minority carriers. anv
minority carriers that may have accuniulated and formed an in;ersion layer ;t
the surface of the drain underneath the gate are swept laterally to the
substrate. For this reason the nonequilibrium surface region is called "incipi-
ent inversion layer" and the nonequilibrium depletion layer is called "deep
depletion layer."
If the field in the oxide, E
ox
' is large enough, the voltage drop across the
depletion layer suffices to enable tunneling in the drain via a near-surface
trap. Several tunnelings are thought to be possible [26]. What-
ever the mechanism, the minority carriers emitted to the incipient inversion
layer are laterally removed to the substrate, completing a path for a gate-
induced drain leakage (GIDL) current. In CMOS circuits this leakage cur-
rent contributes to standby power. 'ne GIDL can be controlled by increasing
, p-Substrate
edge
-',
,
,
,
,
,
,
I
I
.
Figure 2.10 Gate-induced drain leakage
in MOSFET.
POWER DISSIPATION IN CMOS 29
30 PHYSICS OF POWER DISSIPATION IN CMOS FEr DEVICES
the oxide thickness (reducing the field for a given voltage), increasing the
doping in the drain (to limit the depletion width and the tunneling volume),
or eliminating traps (assuming voltages and fields low enough that trap-free
band-to-band tunneling is not possible).
2.3 POWER DISSIPATION IN.CMOS
The first ICs ever fabricated used a PMOS process. This was due to the
simplicit'f of fabrication of a p-channel enhancement mode !vIOS field..-effect
transistor (PMOST) with threshold voltage V
r
< O. But soon thereafter the
PMOS was replaced by the NMOS as the process of choice for fabricating
ICs. The drain-source current in a PMOST results from flow of positively
charged holes and in an NMOST from the flow of negatively charged
electrons. Since the electron mobiIitv II. ;l:. 1IIWlIVl:. 11Irup.r thlln hnlp mnhiHtv
'"'J rn _ _" --"0-- _ - _ J
f.L
p
and the switching time for an inverter is inversely proportional to the
carrier (hole or electron) mobility, an NMOS inverter has a p.. I p.. = 2.5
times faster transient response than a PMOS inverter. This fact the
move to the NMOS process. Today NMOS is no longer the dominant
process, CMOS is. This chanQ:e has been brouQ:ht about bv the verY consider-
ation central to us, that of dissipation. " "
The NMOS inverter dissipates significant amount of power even when its
input is not changing (for this reason this component of power dissipation is
called static power dissipation). Static power dissipation in CMOS is due to
leakage currents and is small in comparison to other components. This
advantage of CMOS over NMOS has proven to be important etiough that the
shortcomings of CMOS are overlooked. The CMOS process is more complex
than the NMOS,. the CMOS requires use of guard-rings to get around the
latch-up problem, and CMOS circuits require more transistors than the
equivalent NMOS circuits.
Figure 2.11 shows a CMOS inverter. When = 0, the NMOST is in
cutoff and when = the PMOS is in cutoff. Hence with the input
stable at either 0 or no current flows from rtdd to ground. A very small
amount of power dissipation, though, does take place. This is due to the
currents. With Vin = 0, the PMOST is conducting and the NMOST is
III cutoff. The output capacitor is charged up to As is increased
beyond V
r
_, the NMOST starts to come out of cutoff and enters the
saturation 'region. The output capacitor starts to discharge through the
NMOST and v"ut decreases. At this time, a conducting path exists for current
to flow directly from V
dd
to ground. When the gate-to-source voltage V and
h d
. p
t e ram-to-source voltage J:'ds of the PMOST s?tisfy < IVdsl - IV
r
) the
PMOST also enters saturatIOn. Here, v"UI begms to drop steeply until the
increasing makes the gate-to-source voltage of the NMOST V
r
greater
than its V
ds
' Then the NMOST becomes nonsaturated. Finally when V has
increased to the point that V
dd
- < IV
r
I, the PMOST goes into
and the flow of current from V
dd
to ground ceases. Hence we saw that the
current flow consisted of two components, one due to the output capacitor
discharging through the NMOST and the second straight from V
dd
to ground.
Changing Vin from 0 to V
dd
elicits a similar behavior. The current flow
consists of a component and an output capacitor
component. In either cases the two components of the current flow give rise
dissipation, referred to as dynamic power dissipation, as it occurs
when the gate output is changing. The component of power dissipation due
t?e of current from V
dd
direct to ground is called short-circuit power
dISSIpatIOn. The power dissipated in charging and discharging the load
capacitances is called switching power.
At this point, two facts about the dynamic component of power dissipation
are of interest: It is by far the dominant component and it is proportional to
the product of load capacitance C
L
and the square of the supply voltage
Hence reduction of dynamic power voltages V
r
and V
r
become critical
parameters. The threshold voltages place a limit on the
P
minimum supply
voltage that can be used without incurring unreasonable delay penalties. As
low as possible values of threshold voltages are desirable. Unfortunately, if
the threshold voltage is too low, the static component of the power due to
subthreshold currents becomes significant. Detailed analysis of subthreshold
leakage is given in Chapter 5. Thus design of devices and selection of supply
and threshold voltage requires trade-offs.
Figure 2.11 A CMOS inverter.
2.3.1 Short-Circuit Dissipation
In static CMOS circuits, while V
r
< < V
DD
- IV
r
I, where is the
voltage ata changing, say the ith, input and the voltage at remaining inputs
are steady, both the NMOST subnetwork and the PMOST subnetwork
conduct and a short-circuit path exists for direct current flow from V
DD
to
the ground terminal. The mean short-circuit power dissipation is then given
by I
mean
V
DD
Analysis of any static CMOS gate using a circuit analysis
program shows that the short-circuit dissipation of the gate varies with the
output load and the input signal slope [27]. The short-circuit dissipation
decreases in both absolute terms and as a fraction of total dissipation as the
POWER DISSIPATION IN CMOS 31 32 PHYSICS OF POWER DISSIPATION IN CMOS FET DEVICES
Figure 2.12 An inverter.
Solving = 0, = V
DD
, and = 0, we obtain
V
T
T
t
l
= --T and t
2
= -
V
DD
2
Substituting (2.51), (2.53), and (2.54) into (2.52), we get
2
1
"/2 13 ( V
T
)2
[ = 2- - -t - V dt
mean T 2 T
(VT/VOO}r T
(2.54)
(2.55)
i
l
i
z
i)
Figure 2.13 Short-circuit current.
T
(2.56)
(2.57)
(2.58)
Let 0 =(Vy/T)t - V
T
; then
1 = 213 j(VT/VOO}r0 dO
mean T ,,/2
Therefore, the short-circuit power dissipation of an unloaded inverter is
p 3
T
PSC = 12 (VDD - VT ) T
Solving,
V
ln ..It---+.'t'R.:
YDD _-....
I
Mu

(2.52)
output load is increased. Exact analysis of the short-circuit dissipation for a
loaded inverter [28] is complex. The following analysis, while simplified,
offers insights into the short-circuit dissipation and gives an upper bound.
For simplicity a symmetrical inverter (i.e., f3N = f3p and V
T
= - V
T
;
Figure 2.12) and a symmetrical input signal (i.e., rise time T
R
,,: fall tin{e
TF = T; Figure 2.13) are considered. The input signal is also periodic with
period equal to T. During the interval from t
1
to t
2
, the short-circuit current
increases from 0 to I
max
As, for the NMOST, V
DS
> Vas - V
T
, it will be in
saturation. The simple square-law formula then gives the drain"current:
[= - V
T
)2 for 0 ;S; [ :;;; [max (2.51)
Due to the assumption of the symmetry of the inverter, this current will reach
its peak: when = V
DD
I2 and its waveform will be symmetric about the
vertical axis t = t
2
The mean current is given by dividing by T the result of integrating the

instantaneous current from t = 0 to t = T:
liT 2
112
13
2
I
mean
= - l(t) dt = 2-
T
- V
T
) dt
To 1
1
,2
Assuming the rising and falling portions of the input voltage waveform to be
linear ramps, V;
DD
= -t (2.53)
T
We see from Eq. (2.58) that Psc depends upon frequency (= liT), the
supply voltage, and the rise and fan times of the input signal.
The short-circuit power dissipation characteristic of an inverter with a load
capacitance C
L
can be studied using simulation [27]. It is seen that if the
input and the output signal have equal rise and fall times, the short-circuit
dissipation is small. However, if the inverter is lightly loaded, causing output
rise and fall times that are relatively shorter than the input rise and fall
times, the short-circuit dissipation increases to become comparable to dy-
namic dissipation. Therefore, to minimize dissipation, an inverter should be
designed in such a way so that the input rise and fall times are about equal to
the output rise and fall times.
2.3.2 Dynamic Dissipation
For an inverter, the average dynamic dissipation can be obtained by summing
the average dynamic dissipation in the NMOST and the PMOST (Figure
2.14). Assuming that the input is a square wave having a period T and
that the rise and fall times of the input are much less than the repetition
period, the dynamic dissipation is given by
(2.59)
Figure 2.15 Switching energy per transition: partial swing.
where V is the maximum voltage that the load capacitor charges to. Equation
(2.61) follows from the assumption that C
L
is independent of v" and does
not vary with time. When V = V
DD
, E
O
...
l
= CLVIiD' When energy stored in a
capacitor with capacitance C
L
and voitage V
DD
across its plates is C
L
VJ5DI2,
the rest of the energy, another C
L
VDI2, is converted into heat. This is
because of the finite source-drain channel resistance of the PMOSTs that
provide the path for the charging current. The remaining GLVD/2 energy
stored in the load capacitor is converted into heat when the gate output
makes a high-to-Iow transition and the capacitor discharges through the
on-resistance of the NMOSTs. During a high-to-Iow transition, no additional
energy is transferred out of the power-supply. Hence the Eo ... 1 in (2.61) is
the power dissipated during a pair of transitions, one low-to-high and one
high-to-low.
In many instances, a circuit node may not charge to full V
DD
- Nodes in
networks of pass transistors are such cases (Figure 2.15). In Figure 2.15
v" s; V
DD
- ~ . Hence, from (2.63), energy transferred during a low-to-high
transition of V
o
' Eo ... 1 = CLVDD(VDD - ~ .
In dynamic circuits, during the evaluate phase, redistribution of the net
charge stored on all the node capacitances occurs. Transient currents flow
from one floating circuit node to another through conducting MOSTs and
power is consumed. Consider the example circuit in Figure 2.16. During the
evaluate phase the node V
o
discharges from V
DD
to V
DD
- AV. During the
precharge phase, it is charged back from V
DD
- AV to V
DD
The discharge of
node V
o
occurs as a result of charge sharing with the node ~ n t via the
conducting MOST with input A. Both the nodes v., and ~ n t are floating due
to the absence of conducting paths to either the V
DD
or the ground terminal.
Assuming ~ n t s; V
DD
- V, (so that it is assured that the MOST with input
A is conducting), V
DD
- dV = ~ n t . Since at the start of the evaluate phase,
capacitor C
int
is completely discharged, at the end of the evaluate phase the
charge stored in G
int
is equal to the charge given up by CL
(2.63)
(2.60)
+
;-rVo
~
VDu
NMOS
L.-._-1 Network
. dY"
lDD(t) = G
L
dt (2.62)
Hence the energy transferred out of the power-supply during a low-to-high
transition at the gate output is given by
dE
pet) = --;jf = V
DD
x iDD(t) (2.61)
assuming that the input voltage is a step applied at t = 0 and that leakage
current is negligible,
2.3.2.1 Energy per Transition-Method 2
Since,
The important thing to note in the above expression for the dynamic power is
that it is proportional to switching frequency and the square of the supply
voltage but is independent of the device parameters. Since 21T is the
average number of transitions per second, CLV6D/2 is the energy transferred
per transition. In the following we will consider another method of comput-
ing the energy per transition.
(2.64)
Figure 2.14 Energy per transition.
Therefore,
(2.65)
POWER DISSIPATION IN CMOS 35 36 PHYSICS OF POWER DISSIPATION IN CMOS FET DEVICES
elk
.tV
DD
I

7\ =High I
TABLE 2.1 Average Gate Capacitance of a MOS Transistor in the Three Regions
of Operation
Operation Region

C
gd
Cutoff
r- un {\ {\
\..,..ox
rr
.LJ(!XX V u
Triode 0 C
ox
WL
exx
/2 C
ox
WL
exx
/2
Saturation 0 (2/3)CoxWLexx 0
The overall load capacitance is modeled as the parallel combination of
four capacitances-the gate capacitance C , the overlap capacitance C the
diffusion capacitance C
diff
, and the interccfnnect capacitance C
int
OV'
(2.67)
(2.68)
2.3.3.1 The Gate Capacitance
The gate capacitance is the largest of the four components. It is the
equivalent capacitance of three capacitors in parallel and is given by
where C
gb
is the sum of the gate-to-bulk capacitances of the two MOSTs in
the load inverter and the other two capacitances are the sum of the gate-to-
drain/source capacitances of the MOSTs in the load inverter. The value of
an individual component capacitance depends on the region of operation of
the respective MOST. The values are given in Table 2.l.
The W in Table 2.1 is the sum of the channel widths of the PMOST and
the NMOST of the load inverter, Cox = Boxltox and L
err
is the identical
channel width of the two MOSTs.
2.3.3.2 The Overlap Capacitance
The overlap capacitances arise from the unwanted lateral diffusion of the
drain and source impurities into the channel region under the gate (Figure
2.18). The gate-drain overlap capacitances of the driver inverter need to be
considered in addition to the load inverter. Because of the Miller effect, the
gate-drain overlap capacitances of the driver inverter appear to be larger
than a similar sized load inverter. The gate-drain overlap capacitances of the
MOSTs in the driver inverter are given by
whereas the gate-to-source/ drain capacitances or the MOSTs in the load
inverter are given by
Figure 2.16 Charge sharing in dynamic circuits.
Energy transferred during a complete cycle, E
101
' comprising of a precharge
and an evaluate phase, is given by
2.3.3 The Load Capacitance
It can be observed from (2.60) and (2.66) that the power dissipation of a
CMOS inverter is directly proportional to the load capacitance. Besides gates
that are in-chip output buffers and that drive chip output and input pins
through printed wiring board (PWB) interconnects, all gates in the interior of
a. chip only drive other gates through on-chip interconnects. The load
capacitance of such a gate comprises of a number of parasitic components
some of which are shown in Figure 2.17.
Figure 2.17 An inverter driving another and its model (on the right of the arrow)for
computing the parasitic load capacitance.
(2.69)
38 PHYSiCS OF PO\tVER DiSSiPATiON iN CMOS FEr DEViCES
L
Figure 2.18 Overlap capacitances of a MOS field-effect transistor.
C
jSWg
and C
jsw
, are the gate and the insulation side per unit gate-width
capacitances. C
jSW
, depends on the type of insulation and is high for LOCOS
and very low for shallow trench isolation (STI).
J1 JV
when - 1 and - 1
tax tax
- C - Bins WL
- p-p - -
tins
2.3.3.4 Interconnect Capacitance
As the feature size continues to shrink, there is a corresponding pressure to
reduce metal-widths and metal spacing. The small oxide thickness and metal
spacing make it necessary to consider, besides the parallel-plate capacitance
between the metal and substrate, the effect of fringing fields and of coupling
between neighboring wire. The combined parallel-plate and fringing-field
capacitance is given by
I
f W H 27T 1]
C;nl
p
= Box tax - 2t
ox
+ ( 2t
ox
( R)l xL
In 1+- 1+ 1+-
H tax
Drain
+
n
Lexx
tox
Source
+
n
Source
+
n
The total overlap capacitance is simply the sum of all the above:
w W
when - - 0 and - 0
H t
ox
(2.73)
C
bw
= KeqC
jo
= (V
H
_ _m) [( <Po - VH)l-m - (<Po - Vdl-m]CjO
(2.71)
2.3.3.3 Diffusion Capacitance
The overall diffusion capacitance is the sum of the diffusion capacitances of
the two !vl0STs in the driver inverter. Diffusion capacitlli'iCe for a
itself has two components, the bottomwall area capacitance and the sidewall
capacitance. The bottomwall capacitance is given by
where C
jO
is the junction capacitance per unit area under zero bias, <Po :::I 0.6
V is the built-in potential for silicon p-n junction, m :::I is the grading
coefficient, VB == V
DD
, and V
L
== O. Observe that C
jO
and hence C
bw
increase
as V
DD
decreases.
The sidewall capacitance has contributions from each of the four walls and
is given by
where W, H, and L are the width, length and height of the metal wire.
The mutual coupling between two wires and that between a wire and the
ground plane contribute to the interconnect capacitance. While the mutual-
coupling capacitance decreases with increasing design rule, both the
parallel-plate capacitance and the ground-coupling capacitance increase lin-
early. As a result the total interconnect capacitance first decreases with
increasing design rule and then increases [47].
2.4 LOW-POWER VLSI DESIGN: LIMITS
Since the fabrication of the first transistor in the late 1940s, microelectronics
has advanced at a breathtaking rate from one transistor per chip to nearly SO
million transistors per chip today. This growth has come about as a net effect
of a decline by a factor of 1/50 in the minimum feature size, a growth by a
factor of 170 in the die area, and an improvement in the number of devices
per minimum feature area by a factor of 100. In 1975 Gordon Moore of Intel
made the astute observation that, for the preceding two decades, the number
of transistors per chip had been doubling every year. This observation has
become known as Moore's law, and the exponential nature of growth implied (2.72)
(2.70)
LOW-POWER VLSI DESIGN: UMITS 39 40 PHYSICS OF POWER DISSIPATION IN CMOS FET DEVICES
P7(t) ----.
P8(t) ---
P9(t) ---0.
P10(t) ---
1e+30r---------,-------------r-----,
.......
' ......... -
...
........
........
.......
........
.......
......
......
......
.......
.......
1e-40L----------:-..I..c-=------------1---.... -... ...=.:! ....
1e-10
1e-30
Transition interval t (seconds)
Figure 2.19 Average power transfer during a switching transistor versus the transi-
tion interval.
In order to graphically represent the various limits we are about to study,
the average power transfer P during a binary switching transition have been
plotted versus the transition time t; in Figure 2.19. Limits imposed by
interconnections have been graphically represented by plotting the square of
the reciprocal of interconnect length (1/L
2
) versus the response time T in
Figure 2.20. For logarithmic scales, diagonal lines in the P-versus-t
d
plane
represent loci of constant switching energy. Similarly, for logarithmic scales,
diagonal lines in the length- (1/L
2
) versus-'T plane represent loci of constant
distributed resistance-capacitance product for an interconnect.
2.4.3 Fundamental Limits
The fundamental limits are independent of devices, materials, and circuits.
They are derived from the basic principles of thermodynamics, quantum
mechanics, and electromagnetics.
The limit from thermodynamic principles results from the need to have, at
any node with an equivalent resistor R to the ground, the signal power P
s
exceed the available noise power P
avaiJ
:
e; 1 4kTRB 1
P = 'YP "' = "11-- = 1'--- = "I1kTB
s aval 14R 4 R I
by the law remains valid two decades later today, albeit the rate has slowed
to 1.5 times per year. The growth in number of transistors per chip has been
accompanied by an increase in reliability while the price has remained
virtually unchanged. What is of more immediate interest to us is that in the
same time period the power-delay product Pt
d
or the energy E consumed
(transformed from electrical energy to heat and dissipated away) by a binary
transition has declined by a factor of 1/10
5
The decline in the power-delay
product per binary transition has been, largely but not entirely, a by-product
of scaling. It has nevertheless been an indispensable by-product for without it
the problem of heat removal would have become serious enough to come in
the way of continued scaling. Microelectronics being undoubtedly the most
important technology in the present information era, much attention [29-32]
is being paid to the limits upon this scaling that may arise from power
dissipation or from any of the other considerations. This section considers
the different limits that apply to continued scaling, the state of the VLSI
circuit technology vis-a-vis the limits, and ways of realizing and possibly going
beyond these limits.
Researchers began to ponder over limits as far back as 1983 [33]. More
recently Nagata [29] reviewed physical limitations on MOS devices and the
ways in which the limitations constrain the way the devices scale. Hu also
considers scaling of MOS devices [30] but with focus on reliability constraints.
Meindl described a hierarchy of limits [31] that would govern the realization
of billion-tr;lllsistor chips. Most recently Taur et aJ. [32] addressed the
challenges in further scaling the MOS devices into the sub-lOO-nm region in
Ught of fundamental physical effects and practical considerations.
2.4.1 Principles of Low-Power Design
To deduce the limits on low-power design, it is important to understand
the different aspects-from fundamental physical laws to practical considera-
tions-that govern it. There are three key principles [31,34] of low-power
design: (1) using the lowest possible supply voltage, (2) using the smallest
geometry, highest frequency devices but operating them at the lowest possi-
ble frequency, (3) using parallelism and pipelining to lower required fre-
quency of operation, (4) power management by disconnecting the power
source when the system is idle, and (5) designing systems to have lowest re-
quirements on subsystem performance for the given user level functionality.
2.4.2 Hierarchy of Limits
Meindl [31] defines a hierarchy of limits that has five levels: (l) fundamental,
(2) material, (3) device, (4) circuit, and (5) systems. At each level two types of
limits exist: (1) from theoretical considerations and (2) from practical consid-
erations.
LOW-POWER VLSI DESIGN: LIMITS 41
1e+20,----------.....,-------------.....,-------,
nect to be always less than the speed of light in free space, co:
1e-30 '--------..,..1e-_.L
1
-::"O----------.J-----'
Response time t: (8)
Figure 2.20 Square of reciprocal length of an interconnect versus interconnect
circuit response time.
1
J 1e+10
1
&
lI)
'0
1e-
1
0r
e
a. 1e-20
.
a:
iL2a(t:}-
iL2b(t:)--
iL2c(t:} ----

L
-
7
where L is the length of the interconnect and 7 is the interconnect transit
time. The corresponding loci is labeled iL2a(T) in Figure 2.20.
2.4.4 Material Limits
Material limits are independent of the particular devices built with the
materials and, in turn, the particular circuits composed from those devices.
The attributes of a semiconductor material that determine the properties of a
device built with the material are (1) carrier mobility j.t, (2) carrier saturation
velocity, <T;, (3) self-ionizing electric field strength E
e
, and (4) thermal
conductivity K.
Semiconductor material limits that are independent of the structures and
the geometry of devices can be calculated by considering a cube of the
undoped material of dimension Ax that is imbedded in a three-dimensional
matrix of similar cubes. The voltage difference Vn across a pair of its opposite
faces is just as large as necessary to produce a'iJ electric 'field equal to the
self-ionizing electric field strength B
c
, that is, VolAx = E
c
The limit on
switching energy and the switching time can then be calculated as the amount
of electrostatic energy stored in the cube and the transit time of a carrier
through the cube:
Solving,
where we have used Fourier's law of heat conduction, K is the thermal
conductivity of the semiconductor material, A is the surface area through
The corresponding loci is labeled P3(t) in Figure 2.19.
The second material level limit arises from heat removal considerations.
To derive this limit, an isolated generic device that resides in an ideal heat
sink maintained at temperature To is considered. The device is hemispherical
in shape with a radius of 's = o'h. The power or the rate of transfer of the
heat energy from the device to the heat sink is then given by
where 'Y ;;::: 1 is some constant factor, e; is open-circuit mean-square voltage
across the equivalent resistor, k is Boltzmann's constant, T is the absolute
temperature, and B is the bandwidth of the node. The corresponding loci is
labeled Pl(t) in Figure 2.19. Because of consideration that we will discuss in
a later section, 'Y = 4 is recommended. Then at T = 300 K, Ps must be larger
than 0.104 eV. In practice the signal power today is larger by a factor of
nearly 10
7
The quantum theoretic limit on low power comes from the Heisenberg
uncertainty principle. In order to be able to measure the effect of a switching
transition of duration At, it must involve an energy greater than hl4t:
where h is the Planck's constant. The corresponding loci is labeled P2(t) in
Figure 2.19. Finally the fundamental limit based on electromagnetic theory
results in the velocity of propagation of a high-speed pulse on an intercon-
which the heat flow is occurring, and dTI (]x is the temperature gradient. The
corresponding locus is labeled P4(t) in Figure 2.19.
An interesting use of the above limit is to compare suitability of GaAs and
Si for low-power applications. Using representative values, Pltd comes out
to be 0.21 nS/Wfor Si and 0.69 ns/W for GaAs. This shows that while GaAs
has the speed advantage demonstrated earlier, it needs to conduct away
three times as much heat for the same transition time.
If we now consider an SOl structure by surrounding the above generic
device in a hemispherical shell of SiO
z
of radius r
i
, the thermal conductivity
of the structure as a whole is given by [311
By substituting K
ox
O.1K
Si
and ri = l.5r" 2", 4", we obtain K
eq
"'"
0.029K
si
, 0.02K
si
, 0.013K
si
, indicating a two-order-of-magnitude reduction in
thermal conductivity.
The interconnect material limit again arises from speed-of-light considera-
tions. The propagation time through an interconnect of length L of a
material with a relative dielectric constant 8
r
must satisfy -
L
The corresponding locus is labeled iL2b(T) in Figure 2.20.
2.4.5 Device Limits
The device limits are independent of the circuits that may have been
composed with the devices. As the MOSFET device is used significantly
more than any other, it will be considered in this section. The most important
attribute of a MOSFET is its allowable minimum effective channel length
L
min
[35]. As we saw earlier in the chapter, MOSFET devices with small
effective channel length exhibit the undesirable short-channel effects. Hence
means of achieving L
min
while minimizing the short-channel effects are
required. In order to achieve L
min
, both the gate oxide thickness T
ox
and
source-drain junction depth Xi should be as small as possible [36, 37J.
Decreasing T
ox
leads to increased tunneling leakage currents [29] and de-
creasing Xi leads to increase in parasitic source-drain conductance [38].
As we saw earJier, short-channel effects in bulk MOSFETs can be con-
trolled by using channels with lower impurity concentration and abrupt
retrograde doping profiles. Studies have shown the use of dual gates on the
two sides of a channel as being effective in controlling short-channel effects
[39-41]. Agarwal et al. [36] analyzed six different MOSFET structures using a
combination of options from deep versus shallow junction and uniform versus
low-impurity channel in case of bulk MOSFETs and single versus dual gate
in case of SOl MOSFETs. The results of analysis indicate the possibility of
shallow-junction retrograde channel profile bulk. MOSFETs with channel
length as short as 60 nm and dual-gate or delta MOSFETs with channel
length as short as 30 nm.
Besides the channel length, the thickness of the oxide layer and its
permittivity are important parameters for controlling the short-channel-length
effects as indicated by the expression for the threshold voltage shift given
below (derived earlier in the chapter):
MOSFET device leakage current and its overall reliability are affected by
factors other than the threshold voltage shift, for example, bulk punchthrough,
gate-induced drain barrier lowering, and impact ionization. In determining
the MOSFET device limits, the latter need to be considered too.
The energy transferred during a switching transition is stored on the gate
of a MOSFET prior to the transition. Therefore, the minimum effective
channel length 'translates into a limit on the switching energy given by
Since
L
E = Ptd = p-!!!!!!..
V
sat
If the minimum transition times corresponding to material and device limits
are computed for even conservative value of L
min
, and T
ox
equal to 100 and 3
nm, respectively, it is seen that the difference between them is small [loci
labeled P4(t) and P7(t) in Figure 2.19]. This indicates that the MOSFET
device limits are already pushing against the material limits of silicon.
At the device level, a global interconnect can be modeled as a canonical
distributed resistance-capacitance network. When such a network is driven
by an ideal voltage source that applies a unit step function, the 0-90%
response time of the network is given by [31]
p e 2
T=RC= --L
HpH"
where p/ H
p
is the conductor sheet resistance in ohms per square, 8/He is
the sheet capacitance in farads, per square centimeter, and L is the length of
the interconnect. The above expression specifies a limit on the minimum
response time of an interconnect given its length.
2.4.6 Circuit Limits
The circuit level limits are independent of the architecture of a particular
system. There are four principal circuit level limits.
To be able to distinguish between the "zero" and "one" logic levels with
very nearly zero error is the most basic requirement of a digital logic gate.
For a static CMOS logic gate this means that at the transition point of the
static transfer characteristics of the gate (i.e., where output voltage is equal
to the input voltage), the incremental voltage gain a" must exceed unity in
absolute value. ./i... C!\10S inverter can only satisrj this requirement if its
supply voltage is larger than a minimum limit V
dd
, min [42]
combination of options from deep versus shallow junction and uniform versus
low-impurity channel in case of bulk MOSFETs and single versus dual gate
in case of SOl MOSFETs. The results of analysis indicate the possibility of
shallow-junction retrograde channel profile bulk. MOSFETs with channel
length as short as 60 nm and dual-gate or delta MOSFETs with channel
length as short as 30 nm.
Besides the channel length, the thickness of the oxide layer and its
permittivity are important parameters for controlling the short-channel-length
effects as indicated by the expression for the threshold voltage shift given
below (derived earlier in the chanter): ----- ~ .._-- ~ -- --- ....
MOSFET device leakage current and its overall reliability are affected by
factors other than the threshold voltage shift, for example, bulk punchthrough,
gate-induced drain barrier lowering, and impact ionization. In determining
the MOSFET device limits, the latter need to be considered too.
The energy transferred during a switching transition is stored on the gate
of a MOSFET prior to the transition. Therefore, the minimum effective
channel length "translates into a limit on the s\
1I
1itching energ'j given by
2kT ( C
fS
) ( Co )
V
dd
~ Jldd,min = q 1 + Co + Cd In 2 + Cd
{3kT
~
q
Since
L
rnin
E =Pt
d
=P--
V
sat
If the minimum transition times corresponding to material and device limits
are computed for even conservative value of L
min
, and T
ox
equal to 100 and 3
run, respectively, it is seen that the difference between them is small [loci
labeled P4(t) and P7(t) in Figure 2.19]. This indicates that the MOSFET
device limits are already pushing against the material limits of silicon.
At the device level, a global interconnect can be modeled as a canonical
distributed resistance-capacitance network. When such a network is driven
by an ideal voltage source that applies a unit step function, the 0-90%
response time of the network is given by [31]
p e 2
T=RC= --L
HpH
e
where Cfs is channel fast s u r f ~ state, Co is gate oxide capacitance, Cd is
channel depletion region capacitance, and {3 is typically between 2 and 4. At
T = 300 K. Jldd,min "" 0.1 V. This also is the reason for selecting the constant
'Y = 4 in the fundamental limit on switching energy E = 'YkT.
In practice, a value of Jldd = 0.1 V cannot be used because the threshold
voltage V; would need to be so small that the drain leakage current in the off
state of the MOSFET would be unacceptably large. In considering logic and
memory circuit behavior, Jldd = 1.0 V appears to be a good compromise for
small dynamic and static power dissipation.
Tne second generic circuit limit for CMOS technoiogy is the often dis-
cussed switching energy per transition
where C
ro
is taken as the total load capacitance of a ring oscillator stage,
including output diffusion capacitance, wiring capacitance, and input gate
capacitance for an inverter that occupies a substrate area of 100P2 (P =
minimum feature size = 0.1 #Lm).
The third generic circuit limit is on the intrinsic gate delay and IS given by
the time taken to charge/discharge the load capacitance C
ro
' Hence,
1 CcV
o
t =---
d 2 Ids
46 PHYSICS OF POWER DISSIPATION IN CMOS FET DEVICES LOW-POWER VLSI DESIGN: LIMITS 47
__ ':[7(N:-
0
.5 - 1) _
R
ri
- 9 4P- 0 .5 - 1
1Nr.5 ]1 - 4
P
-
1
1 - 4P-O,5 1 - NP-l
g
where n = 0.45 (determined emoiricallv for microorocessors [43]) is Rent's
Evaluation returns R
r
; :::< 6 the set of assumptions.
The total wire length a gate has to drive is then
where l\rf is the fanout of the gate and A
rl
the gate Typical values for
them are M = 3 and A
rl
= 200F
2
The gate area is also assumed to be
limited by the transistor packing density. The assumption causes stringent
demands to be placed on the local wiring area, which requires a logic gate
dimension [43]
[
A ]1/2 =R
rl rl e n
w w
where n
w
is the number of wiring levels, Pw is the wiring pitch, and e
w
is the
wiring efficiency factor. The gate logic area is found to be logic limited for
values n
w
= 4, Pw = 0.2 p.,m, and e
w
= 0.75 as well as n
w
= 6, Pw = 0.2 p.m,
and e
w
= 0.5.
The system switching energy limit is defined by a composite gate that
characterizes the critical path within a macrocell. The critical path is as-
sumed to pass through n
cp
random logic gates and include a total intercon-
nect length corresponding to the comer-to-corner Manhattan distance 2L
2.4.7 System Limits
System limits depend on all the other limits and are the most restrictive ones
in the hierarchy. There are five generic system limits that are given rise to by
(l) the architecture of the chip, (2) the power-delay product of the CMOS
technology used to implement the chip, (3) the heat removal capacity of the
chip package, (4) the clock frequency, and (5) its physical size. To illustrate
these limits, a broadly applicable architecture is selected. The system is a
systolic array [44] of 1024 identical square macrocells measuring L to a side.
. Communication is assumed to occur only among neighboring macrocells at
the shared boundary. A five-level ciock distribution H-tree delivers an
unskewed clock signal to each macrocell. The maximum Manhattan distance
the clock signal has to travel within a macrocell is L and the same for a logic
signal is 2L.
Before we can progress further, a set of boundary conditions need to be
assumed: (1) the number of gates N
g
' in each macroceU is 1 billion divided by
1024, (2) the feature size used is a conservative 0.1 p.,m, (3) the package
cooling coefficient is 50 W/cm
2
, (4) the clock frequency is 1 GHz, and (5) the
system is implemented as a single chip.
Using Rent's rule [45], the average length of an interconnect in gate
pitches is
which, given one of P, the power consumption during a transition, or t
d
, the
duration of the transition, specifies a lower bound on the other. The
corresponding locus is labeled P9(t) in Figure 2.19.
The fourth generic circuit limit considers a global (i.e., extending from one
corner of the chip to the other) interconnect represented as a distributed
resistance-capacitance network. The response time of this interconnect cir-
cuit is [43]
where R
tr
is the output resistance of the driving transistor and Rim and C
int
are the total resistance and capacitance, respectively, of the global intercon-
nect. The circuit should be designed so that R
int
< 2.3R
tr
to ensure the delay
due to wiring resistance is not excessive. Then,
Combining with the expression for energy per switching transition,
Assuming carrier velocity saturation in the MOSFET, an approximate value
for the drain saturation current Ids is
where Z is the channel width, V; is the threshold voltage, and the gate
voltage = Yo' Therefore,
where C
int
is the capacitance per unit length of the interconnect. If we model
the interconnect as a nearly Iossless transmission electron microscopy (TEM)
mode line, then the distributed capacitance is given by c
int
= 1/l/Zo, where
v = Col {i; is the wave propagation velocity of the line, B
r
is the relative
permittivity of its dielectric, Zo = ,jp.,o/80 8
r
is its characteristic impedance,
and Co = ,jl/8
0
p.,o is the velocity of light in free space.
The global interconnect response time limit is then given by
The corresponding locus is labeled iL2c(T) in Figure 2.20.
LOW-POWER VLSI DESIGN: UMITS 49
[46]. Then the prorated capacitance loading per gate is C
rl
+ Ccc/n
cp
where
Cd includes the MOSFET diffusion capacitance, wiring capacitance for an
interconnect of length i
r
\> and the MOSFET gate capacitance and Ceo is the
capacitance of the corner-to-corner interconnect. The switching energy of the
composite gate therefore is
The effective propagation delay time of the composite gate can be analo-
gously formulated as
where t
drl
is the delay time of a random logic gate and Tee is the response
time of the corner-to-corner interconnect.
The system heat removal limit is defined by the requirement that the
average power dissipation of a composite gate is must be less than the
cooling capacity of the packaging or
_ aE
P= T 5QA
c
where E is the average switching energy of the composite gate, a the
probability that a gate switches during a clock interval, ~ = l/fe is the clock
interval, Q is the package cooling coefficient, and A is the substrate area
occupied by the critical path composite gate. The substrate area A has a
prorated share of the area Ace due to the comer-to-corner driver in addition
to the random logic gate area ArlO Let
,d r
"rl ~ r l
Hence,
Since the number of gates on the critical path is assumed to be n
cp
if the
small clock skew is taken into account using a factor Scp > 1, the clock period
can be expressed as
T,; =sCpncpt
d
Combining the above four expressions,
scpn
cp
( C
ee
)
P5--QArI
1
+-c
a ncp rl
gives the limit on P that is a result of the finite cooling capacity of the
package. Combining with the expression for the switching energy,
The corresponding locus is labeled P11(t) in Figure 2.19. Typical values for
some of the parameters used are C
ee
= 100 fF, C
rl
= 3.28 fF, scp = 1.11, R
int
= 2.3R
tp
H
p
= He = 0.3 JLm, and L
2
= NgA
rl

At the system level, the longest interconnect obviously needs to be focused
on for the (l/L)2-versus-td limit. The system cycle time limit is given by
where T
es
is the maximum clock skew within a macroc-e!! and Tee is response
time of the global interconnect of length 2L.
2.4.8 Practical Limits
The basis for practical limits is the opinion that beyond a certain point in
scaling, the cost of designing, manufacturing, testing, and packaging will
cause the cost per function to level off and begin to increase. To facilitate
further analysis, the number of transistors per chip N can be expressed as
N = F-
2
D
2
PE.
The optimistic predictions for the minimum feature size F are to reach
0.0625 JLm by the second decade of the millennium, for the chip area D to
reach over (50 mm)2, and for the packing efficiency PE to reach one
transistor per minimum feature area [31]. This would make 100 billion
transistor chips economically viable in addition to being technically possible.
2.4.9 Quasi-Adiabatic Microelectronics
In any thermodynamic system that proceeds from one equilibrium process to
another, the entropy of a closed system either remains unchanged or in-
creases. In a computational process, it is only those steps that discard
information or increase disorder that have a lower limit on the energy
dissipation. During an adiabatic process no loss or gain of heat occurs-con-
sequently the intriguing prospect of inventing quasi-adiabatic computational
technology and reducing the power dissipation to levels beyond the limits of
nonadiabatic computation. In a following chapter of this book the quasi-
adiabatic circuits will be examined in detail.
The P-versus-t
d
limits can also be formulated for quasi-adiabatic micro-
electronics [31]. At the fundamental level of the hierarchy, Ed = ykT, when
the rise/fall time of input voltage T
d
= 2t
d
, the propagation or the response
time is td. At the material level Ed = 8Si V/2E;0' and at the device level
Ed = O ~ i n Vt/2. Unlike the unchanging materials and device structures,
the circuit configurations used for quasi-adiabatic operations must change
significantly. Without identifying specific circuit configurations and system
architectures, the respective limits cannot be analyzed.
2.5 CONCLUSIONS
In this chapter we studied the physics of power consumption in CMOS VLSI
circuits. We derived the threshold voltage of an MIS diode and then the
L 1... 1...1 1 ..J. ... 1.. 1.. ...L 1.-_1..1 J.. .... _ 1 \..r __....1 It.. ...
tureSuOIU vOltage anu UL i1 IUUg-l;Ui1UUl;;1
When a low supply voltage is used to minimize the dynamic component of
overall power consumption, correspondingly low threshold voltage has to be
used to ensure sufficient noise margin. However, we saw that the subthresh-
old current increases exponentially with threshold voltage and
results in a larger static component to overall power consumption. Submi-
crometer MOSFET was considered next. The threshold voltage shift due to
the various short-channel effects was examined and an expression for it was
derived using a model based on DIBL.
The different components of overall power consumption in CMOS VLSI
circuits were discussed. The dynamic component of power consumption itself
comprises switching and short-circuit subcomponents. The dynamic compo-
nent, though still the dominant component, may not be so as supply voltage
continues to decrease.
The hierarchy of theoretical limits on microelectronics summarized in the
orecedinll discussion indicates that the trend of ever more transistors per
not continue unabated through th: first fe,,: ?f the new
millennium. The paramount issue from pract1cal consideration 1S whether
there will continue to be sufficient economic incentives to risk the ever-grow-
ing capital investments required for further reduction of the cost per function
of chips.
REFERENCES
[1] G. Baccarani et aL, "Analytical IGFET Model Including Drift and Diffusion
Currents," lEE J. Solid State Electron, Devices, vol. 2, p. 62, 1978.
[2] J. R. Brews, "A Charge-Sheet Model of the MOSFET," Solid State Electron.,
vol. 21, p. 345, 1978.
[3] S. M. Sze, Physics of Semiconductor Devices, Wiley-Interscience, New York,
1969.
[4] C. G. B. Garett and W. H. Brattain, "Physical Theory of Semiconductor
Surfaces," Phys. Rev., vol. 99, p. 376, 1955.
[5] L. D. Yau, "A Simple Theory to Predict the Threshold Voltage in Short-
Channel IGFETs," Solid-State Electron., vol. 17, p. 1059, 1974.
[6) F.-C. Hsu et al., "An Analytical Breakdown Model for Short-Channel MOFETs,"
IEEE Trans. Electron. Dev., vol. 30, p. 571, 1983.
REFERENCES 51
[7] Z.-H. Liu et aI., "Threshold Voltage Model for Deep-Submicrometer
MOSFETs," IEEE Trans. Electron. Dev., vol. 40, p. 86,1993.
[8] J. R. Brews et aI., "Generalized Guide for MOSFET Miniaturization," IEEE
Electron. Dev. Lett., vol. 1, p. 2, 1980.
[9) G. W. Taylor, Solid State Electron., vol. 22, p. 701, 1979.
[10] G. Merkel, "A Simple Model of the Threshold Voltage of Short and Narrow
Channel MOSFETs," Solid State Electron., vol. 23, p. 1207, 1983.
[11] C. R. Ji and C. T. Shah, "Two-Dimensional Analysis of the Narrow-Gate Effect
in MOSFETs," IEEE Trans. Electron. Dev., vol. 30, p. 635, 1983.
[12] S. S. Chung and T.-C. Li, "An Analytical Threshold Voltage Model of the
Trench-Isolated MOS Devices with Nonuniformly Doped Substrates," IEEE
Trans. Electron. Devices, vol. 13, p. 614, 1992.
[13] C. Y. Lu and J. M. Sung, "Reverse Short-Channel Effects on Threshold Voltage
in Submicron Salicide Devices," IEEE Electron Dev. Lett, vol. 10, p. 446, 1989.
[14] M. Orlowski et aI., "Submicron Short-Channel Effects Due to Gate Reoxidation
Induced Lateral Diffusion," IEDM Tech. Dig., vol. 32, p. 632, 1987.
[15] N. D. Arora and M. S. Sharma, "ModeJling the Anomalous Threshold Voltage
Behavior of Submicron MOSFETs," IEEE Electron. Dev. Lett., vol. 13, p. 92,
1992.
[16] H. Hanafi et aI., "A Model for Behavior in
MOSFET," iEEE Electron. Dev. Lett., VOl. 14, p. :> I:>,
[17] D. Sadana et al., "Enhanced Short-Channel Effects in NMOSFETs Due to
Boron Redistribution Introduced by Arsenic Source and Drain Implant," IEDM
Tech. Dig., vol. 37, p. 849, 1992.
[18] H. Jacobs et aI., "MOSFET Short Channel Effect Due to Silicon Interstitial
Capture in Gate Oxide," lEDAf Tech. Dig., vol. 38, p. 307, 1993.
[19] c. S. Rafferty et al., "Explanation of Reverse Short-Channel Effect by Defect
Gradients," IEDM Tech. Dig., vol. 38, p. 311, 1993.
[20) J. Zhu et aI., "Punchthrough Current for Submicrometer MOSFETs in CMOS
VLSI," IEEE Trans. Electron. Dev., vol. 35, p. 145, 1988.
[21] C. Hu, "Future Scaling and ReHabilit'j," Proc. IEEE, vol. 81, p. 682,
1993.
[22] F. M. Klassen, "Design and Performance of Micron-Sized Devices," Solid State
Electron., vol. 21, p. 565, 1978.
[23] T. Shibata et aI., "An Optimally Designed Process for Submicrometer
MOSFETs," IEEE Trans. Electron. Dev., vol. 29, p. 531, 1982.
[24] C. F. Codella and S. Ogura, "Halo Doping Effects in Submicron DI-LDD
Device Design," IEDM Tech. Dig., p. 230, 1985.
[25] A. Hori et al., "A Self Aligned Pocket Implantation (SPI) Technology for
0.2 Gate CMOS," IEDM Tech. Dig., vol. 36, p. 642, 1991.
[26] J. R. Brews, "Subthreshold Behavior of Uniformly and Non-Uniformly Doped
Long-Channel MOSFETs," IEEE Trans. Electron. Devices, vol. ED-26, no. 9,
p. 1282, 1979.
[27] H. Veendrick, "Short Circuit Dissipation of Static CMOS Circuitry and its
Impact on the Design of Buffer Circuits," IEEE J. Solid-State Circuits, vol. 19,
no. 4, Aug. 1984.
[28] L. Bisdounis, O. Koufopavlou, and S. Nikolaidis, "Accurate Evaluation of
CMOS Short Circuit Power Dissipation for Short Channel Devices," Interna-
tional Symposium on Low Power Electronics & Design, Monterey, CA, Aug.
1996, pp. 181-192.
[29] M. Nagata, "Limitations, Innovations and Challenges of Circuits and Devices
into a Half Micrometer and Beyond," IEEE J. Solid-State Circuits, vol. 27,
pp. 465-472, 1992.
[30] C. Hu, "MOSFET Scaling in the Next Decade and Beyond,"Proc. International
Semiconductor Device Research Symp., Semicon. Int., pp. 105-114, June 1994.
[31] J. D. Meindl, "Low Power Microelectronics: Retrospect and Prospect," Proc.
IEEE, vol. 83, no. 4, pp. 619-635, 1995.
[32] Y. Taur et aI., "High-Performance 0.1 mm, CMOS Devices with 1.5 V Power
Supply," IEDM Tech. Dig., vol. 38, pp. 127-130, 1993.
[33] J. D. Meindl, "Theoretical, Practical, and Analogical Limits in ULSI," IEDM
Tech. Dig., vol. 28, pp. 8-13, 1983.
[34] A. P. Chandrakasan et aI., "Low Power CMOS Digital Design," IEEE J.
Solid-State Circuits, vol. 27, pp. 473-484, 1992.
[35] K. N. Ratnakumer et al., "Short-Channel MOSFET Threshold Voltage Model,"
IEEE J. Solid-State Circuits, vol. SC-17, pp. 937-947, 1982.
[36] B. Agarwla et aI., "Opportunities for Scaling MOSFETs for GSI," Proc.
ESSDERC 1993, voL 25, pp. 919-926, September 1993.
[37] C. Fiegna et aI., "A New Scaling Method for 0.1-0.25 Micron MOSFET," Symp.
VLSI Tech. Dig., pp. 33-34, May 1993.
[38} M. Ono et aI., "Sub-59 nm Gate Length N-MOSFET's with 10 nm Phosphorous
SID Junctions," IEDM Tech. Dig., vol. 38, pp. 119-121, 1993.
[39] D. Hisamoto et aI., "A Funy Depleted Lean Channel Transistor (DELTA...) a
Novel Vertical Ultrathin SOl MOSFET," IEEE Electron. Devices Lett., vol. 11,
pp. 36-38, 1990.
[40] D. J. Frank et aI., "Monte-Carlo Simulation of a 30 nm Dual Gate MOSFET:
How Short Can Si Go?" IEDM Tech. Dig., vol. 37, pp. 553-556, 1992.
[41] T. Tanaka et aI., "Ultrafast Low Power Operation of P + N + Double-Gate
SOl MOSFETS," Symp. VLSI Tech. Dig., pp. 11-12,1994.
[42] R. M. Swanson et aI., "Ion-Implanted Complimentary MOS Transistors in
Low-Voltage Circuits," IEEE J. Solid-State Circuits, vol. SC-7, pp. 146-152;
1972.
[43] B. Bakoglu, Circuits, Interconnections and Packaging for VLSI, Addison-Wesley,
Reading, MA, pp. 198-200, 1990.
[44] H. S. Stone et aI., "Computer Architecture in the 1990s," IEEE Computer, vol.
24, pp. 30-38, Sept. 1991.
[45] B. S. Landrum and R. L. Russo, "On Pin Versus Block Relationship for
Partitioning of Logic Graphs," IEEE Trans. on Computers, vol. C-20, pp.
1469-1479, Dec. 1971.
[46] A. Masaki, "Possibilities of Deep Submicrometer CMOS for Very High-Speed
Computer Logic," Proc. IEEE, vol. 81, pp. 1311-1324, 1993.
[47] M. Shoji, CMOS Digital Circuit Technology, Prentice Hall, New Jersey, 1988.

Physics of Power Dissipation in CMOS

Uploaded by

Copyright:

Available Formats

Physics of Power Dissipation in CMOS

Uploaded by

Document Information

Original Description:

Copyright

Available Formats

Share this document

Share or Embed Document

Sharing Options

Did you find this document useful?

Is this content inappropriate?

Copyright:

Available Formats

Physics of Power Dissipation in CMOS

Uploaded by

Copyright:

Available Formats

This chapter begins with a study of the physics of small geometry MOSFET

The mean current is given by dividing by T the result of integrating the

You might also like