Shared memory multiprocessor system

Recent advances in the development of reconfigurable optical interconnect technologies allow for the fabrication of low cost and run-time adaptable interconnects in large distributed shared-memory (DSM) multiprocessor machines. This can allow the use of adaptable interconnection networks that alleviate the huge bottleneck present due to the gap between the processing speed and the memory access time over the network. In this paper we have studied the scheduling of tasks by the kernel of the operating system (OS) and its influence on communication between the processing nodes of the system, focusing on the traffic generated just after a context switch. We aim to use these results as a basis to propose a potential reconfiguration of the network that could provide a significant speedup.

Toward the direction of supporting an end-to-end video-on-demand (VOD) system with guaranteed quality over ATM networks, this paper introduces our e orts to solve this challenging problem from the source: building VOD servers. One of the performance objectives of building VOD servers is to support the maximum number of concurrent video streams with acceptable quality of services (e.g., guaranteed delay, bandwidth, and jitter). We have designed and implemented a controllable software architecture for a VOD server. With the proposed software architecture, the design issues for the storage, processing and network subsystems have been addressed. We have investigated several disk striping schemes in the storage subsystem. The impact of these disk striping schemes on the utilization of system resources has been measured. For the processing component, we have observed that additional concurrent video streams can be supported by using e cient memory interleaving. Bu ering with a large memory space in the processing subsystem is a common technique to alleviate the latency variance of accessing di erent system components. By employing user-level control and scheduling, the variance can be decreased and therefore the resulting bu er space for each video stream is reduced. For the network subsystem, we have adopted a server-driven approach for investigating the MPEG-2 video delivery over the ATM networks. The VOD server controls the pace of video transmission and reduces the complexity of the clients. Since the client only has limited bu er space because of the cost consideration, we have reduced the bu er requirement by regulating the transmission based on the timing information embedded in MPEG-2 streams. Our research and experimental results are based on a VOD server which is under construction. The current prototype server is based on an SGI shared-memory multiprocessor with a mass storage system which consists of RAID-3 and RAID-5 disk arrays. Using 30 RAID-3 disk arrays, preliminary experimental results show that it can potentially support more than 360 high-quality video streams with careful design and coordination of the di erent system components.

We present Lazy Binary Splitting (LBS), a user-level scheduler of nested parallelism for shared-memory multiprocessors that builds on existing Eager Binary Splitting work-stealing (EBS) implemented in Intel's Threading Building Blocks (TBB), but improves performance and ease-of-programming. In its simplest form (SP), EBS requires manual tuning by repeatedly running the application under carefully controlled conditions to determine a stop-splitting-threshold (sst) for every do-all loop in the code. This threshold ...

Multiprocessor systems are increasingly becoming the systems of choice for low and high-end servers, running such diverse tasks as number crunching, large-scale simulations, data base engines and world wide web server applications. With such diverse workloads, system utilization and throughput, as well as execution time become important performance metrics. In this paper we present efficient kernel scheduling policies and propose a new kernel-user interface aiming at supporting efficient parallel execution in diverse workload environments. Our approach relies on support for user level threads which are used to exploit parallelism within applications, and a two-level scheduling policy which coordinates the number of resources allocated by the kernel with the number of threads generated by each application. We compare our scheduling policies with the native gang scheduling policy of the IRIX 6.4 operating system on a Silicon Graphics Ori-gin2000. Our experimental results show substantial performance gains in terms of overall workload execution times, individual application execution times, and cache performance.

Distributed Shared Memory is a good solution to the scalability, complexity and high cost problems of large scale Shared Memory Multiprocessors, as well as to the difficulty of the programming model problem of the message passing Distributed Memory Multiprocessors. During recent years many software Distributed Shared Memory systems, operating on top of the Message Passing system have appeared. These systems are forced to use coherence protocols based on directory schemes for the preservation of the consistency of shared data. In this paper, we compare these schemes, focusing on fully centralized and fully distributed directory schemes. We construct a formal mathematical model of a 2-D grid Message Passing multiprocessor and predict the protocols' behaviour.

The specification and verification of shared-memory multiprocessor cache coherence protocols is a paradigmatic example of parallel technologies where formal methods can be applied. In this paper we present the specification and verification of a cache protocol and a set of formalisms which are based on 'process theory'. System correctness is not established by simple techniques such as testing and simulation, but 'ensured'in terms of the underlying formalism. In order to manipulate the specification and verify the properties we have used ...

We study a high order fiuite difference scheme to solve the time accurate flow field of a jet using the compressible Navier-Stokes equations. As part of our ongoing efforts, we have implemented our numerical model on three parallel computing platforms to study the computational, communication, and scalability characteristics. The platforms chosen for this study axe a cluster of workstations connected through fast networks (the LACE experimental testbed at NASA Lewis), a shared memory multiprocessor (the Cray YMP), and a distributed memory multiprocessor (the IBM SP1). Our focus in this study is on the LACE testbed. We present some results for the Cray YMP and the IBM SP1 mainly for comparison purposes. On the LACE testbed, we study: (a) the communication characteristics of Ethernet, FDDI and the ALLNODE networks and (b) the overheads *Most of this work was performed while the author was in residence at Ohio Aerospace Institute,

We describe a parallel resolution theorem prover, called Parthenon* that handles full first order logic. Although there has been much work on parallel implementations of logic programming languages, our system is apparently the first general purpose theorem prover to be developed for a multiprocessor. The system implements a variant of Loveland's model elimination procedure within the framework of Warren's SRI model for or-parallelism. It has been evaluated on various shared memory multiprocessors including a 16-processor Encore Multimax, producing both impressive absolute run times and near-linear speedup curves.

This paper presents Jade, a high-level parallel programming language for managing coarse-grain concurrency. Jade simplifies programming by providing the programmer with the abstractions of sequential execution and a shared address space. Jade programmers augment sequential, imperative programs with constructs that declare how parts of the program access data; the Jade implementation dynamically interprets this information to execute the program in parallel. This parallel execution preserves the serial semantics of the original program. Jade has been implemented as an extension to C on shared-memory multiprocessors, a message-passing machine, networks of heterogeneous workstations, and systems with special-purpose functional units. Programs written in Jade run on all of these platforms without modification.

We propose a new parallel Branch and Bound algorithm for the Quadratic Assignment Problem, which is a Combinatorial Optimization problem known to be very hard to solve exactly. An original method to distribute work to processors using the notion of Feeding Tree is presented. When adequately used, it allows to reduce memory contention and load unbalance. Therefore, a linear speed-up in the number of processors is reached on a shared memory multiprocessor, the Cray 2 and the optimality of solutions for famous problems of size less than 20 (Nugent 16, Elshafei 19, Scriabin-Vergin 20,...) is proved by this program. The implementation analysis shows that these results are more than an improvement due to hardware evolution and confirms the usefulness of our parallel Branch and Bound algorithm for larger Quadratic Assignment Problems.

Shared memory multiprocessors come back to popularity thanks to rapid spreading of commodity multi-core architectures. As ever, shared memory programs are fairly easy to write and quite hard to optimise; providing multi-core programmers with optimising tools and programming frameworks is a nowadays challenge. Few efforts have been done to support effective streaming applications on these architectures. In this paper we introduce FastFlow, a low-level programming framework based on lock-free queues explicitly designed to support high-level languages for streaming applications. We compare FastFlow with state-of-the-art programming frameworks such as Cilk, OpenMP, and Intel TBB. We experimentally demonstrate that FastFlow is always more efficient than all of them in a set of micro-benchmarks and on a real world application; the speedup edge of FastFlow over other solutions might be bold for fine grain tasks, as an example +35% on OpenMP, +226% on Cilk, +96% on TBB for the alignment of protein P01111 against UniProt DB using Smith-Waterman algorithm.

This paper presents an extension of the Latency Time (LT) scheduling algorithm for assigning tasks with arbitrary execution times on a multiprocessor with shared memory. The Extended Latency Time (ELT) algorithm adds to the priority function the synchronization associated with access to the shared memory. The assignment is carried out associating with each task a time window of the same size as its duration, which decreases for every time unit that goes by. The proposed algorithm is compared with the Insertion Scheduling Heuristic (ISH). Analysis of the results established that ELT has better performance with fine granularity tasks (computing time comparable to synchronization time), and also, when the number of processors available to carry out the assignment increases.

Modern shared-memory multiprocessors require complex interconnection networks to provide sufficient communication bandwidth between processors. They also rely on advanced memory systems that allow multiple memory operations to be made in parallel. It is expensive to maintain a high consistency level in a machine based on a general network, but for special interconnection topologies, some of these costs can be reduced. We define and study one class of interconnection networks, race-free networks. New conditions for sequential consistency are presented whichshow that sequential consistency can be maintained if all accesses in a multiprocessor can be ordered in an acyclic graph. We show that this can be done in race-free networks without the need for a transaction to be globally performed before the next transaction can be issued. We also investigate what is required to maintain processor consistency in race-free networks. In a race-free network which maintains processor consistency, w...

Recent advances in the development of reconfigurable optical interconnect technologies allow for the fabrication of low cost and run-time adaptable interconnects in large distributed shared-memory (DSM) multiprocessor machines. This can allow the use of adaptable interconnection networks that alleviate the huge bottleneck present due to the gap between the processing speed and the memory access time over the network. In this paper we have studied the scheduling of tasks by the kernel of the operating system (OS) and its influence on communication between the processing nodes of the system, focusing on the traffic generated just after a context switch. We aim to use these results as a basis to propose a potential reconfiguration of the network that could provide a significant speedup.

In this work we put into evidence how the memory performance of a Web-Server machine may depend on the sharing induced by process migration. We considered a shared-bus shared-memory multiprocessor as the simplest multiprocessor architecture to be used for accelerating Web-based and commercial applications. It is well known that, in this kind of system, the bus is the critical element that may limit the scalability of the machine. Nevertheless, many factors that influence bus utilization, when process migration is permitted, have not been thoroughly investigated yet. We analyze a basic four-processor and a high-performance sixteen-processor machine. We show that, even in the four-processor case, the overhead induced by the sharing of private data as a consequence of process migration, namely passive sharing, cannot be neglected. Then, we consider the sixteen-processor case, where the effects on performance are more massive. The results show that even though the performance may take advantage of larger caches or from cache affinity scheduling, there is still a great amount of passive sharing, besides false sharing and active sharing. In order to limit false sharing overhead, we can adopt an accurate design of kernel data structures. Passive sharing can be reduced, or even eliminated, by using appropriate coherence protocols. The evaluation of two of such protocols (AMSD and PSCR) shows that we can achieve better processor utilization compared to the MESI case.

Communication has always been a limiting factor in making efficient computing architectures with large processor counts. Reconfigurable interconnects can help in this respect, since they can adapt the interprocessor network to the changing communication requirements imposed by the running application. In this paper, we present a performance evaluation of these reconfigurable interconnection networks in the context of shared-memory multiprocessor (SMP) machines. We look at the effects of architectural parameters such as reconfiguration speed and topological constraints, and analyze how these results scale up with higher processor counts. We find that for 16 processors connected in a torus topology, reconfigurable interconnects with switching speeds in the order of milliseconds can provide up to 20% reduction in communication delay. For larger networks, up to 64 processors, the expected gain can rise up to 40%. This shows that reconfigurable networks can help in removing the communication bottleneck from future interconnection designs.

In this paper, we propose efficient parallel implementations of the auction/sequential shortest path and the e-relaxation algorithms for solving the linear minimum cost flow problem. In the parallel auction algorithm, several augmenting paths can be found simultaneously, each of them starting from a different node with positive surplus. Convergence results of an asynchronous version of the algorithm are also given. For the e-relaxation method, there exist already parallel versions implemented on CM-5 and CM-2; our implementation is the first on a shared memory multiprocessor. We have obtained significant speedup values for the algorithms considered; it turns out that our implementations are effective and efficient.

This paper deals with a new class of parallel asynchronous iterative algorithms for the solution of nonlinear systems of equations. The main feature of the new class of methods presented here is the possibility of flexible communication between processors. In particular partial updates can be exchanged. Approximation of the associated fixed point mapping is also considered. A detailed convergence study is presented. A connection with the Schwarz alternating method is made for the solution of nonlinear boundary value problems. Computational results on a shared memory multiprocessor IBM 3090 are briefly presented.

We propose a new parallel Branch and Bound algorithm for the Quadratic Assignment Problem, which is a Combinatorial Optimization problem known to be very hard to solve exactly. An original method to distribute work to processors using the notion of Feeding Tree is presented. When adequately used, it allows to reduce memory contention and load unbalance. Therefore, a linear speed-up in the number of processors is reached on a shared memory multiprocessor, the Cray 2 and the optimality of solutions for famous problems of size less than 20 (Nugent 16, Elshafei 19, Scriabin-Vergin 20,...) is proved by this program. The implementation analysis shows that these results are more than an improvement due to hardware evolution and confirms the usefulness of our parallel Branch and Bound algorithm for larger Quadratic Assignment Problems.

In this work, we characterized the impact of operating system activities like process migration on a shared-bus shared-memory multiprocessor running typical DBMS workload. Our workload has been setup utilizing the TPC-D benchmark on the PostgreSQL DBMS. Analysis has been performed via trace driven simulation enhanced technique which includes most important operating system activities and analyzes the sharing overhead in detail. We evaluated a basic four-processor and a high-end sixteen-processor machine, implementing MESI and other coherence protocols that deal with migration of processes and data. Our results show that even in the four-processor case operating system effects may not be neglected. In fact, different coherence protocols can more effectively reduce the effects of process migration. The consequences on performance become more important in high-end machines (16 or more processors). In this case, even little sharing, as we found in DBMS applications can become crucial for system performance. Better speed up may be achieved adopting several alternatives including redesign of kernel data structure. Cache affinity is somewhat useful in reducing migration effect, but it is not effective in every load conditions.

Allowing multiple threads to execute within the same address space makes it easier to write programs that deal with related asynchronous activities and that execute faster on shared-memory multiprocessors. Supporting multiple threads places new constraints on the design of operating system interfaces. We present several guidelines for designing or redesigning interfaces for multithreaded clients. We show how 1 these guidelines were used to design an interface to UNIX -compatible file and process management facilities in the Topaz operating system. Two implementations of this interface are in everyday use: a native one for the Firefly multiprocessor, and a layered one running within a UNIX process.

12 3.3 Characteristics of most time-consuming subroutines of COMMIX-1AR/P for data set Plr0 running in baseline SV mode on Cray X..MP (from PERFTRAC_) ...... 13 3.4 Characteristics of most, time-consuming subroutines of COMMIX-1AR/P for data set Plrl running in baseline SV mode on Cray X-MP (from PERFTRAC_,)...... 13 3.5 Characteristics of most time-consuming subroutines for data set Plr2 running in b_eline SV mode on Cray X-MP (from PERFTRACE). ................. 13 3.6 Characteristics of most time-consuming subroutines for data set P2 running in baseline SV mode on Cray X-MP (from PERrTRACe). 14 3.7 Characteristics of most time-consuming subroutines for data set P3 running in baseline SV mode on Cray X:MP

We present a framework for parallel programming, based on three conceptual classes for understanding parallelism and three programming paradigms for implementing parallel programs. The conceptual classes are result parallelism, which centers on parallel computation of all elements in a ...

Many aftempts have been made to add con-currency to C+ +, often by extensive compiler extensions, but much of the work has not exploited the power of C+ +. This pa er shows how the object-oriented facilities of [+ + are powerful enough to encapsulate concurrency creation and control. We have developed a concurrent C+ +-based prototype system (ABC+ +)

We study the computational, communication, and scalability characteristics of a computational fluid dynamics application, which solves the time-accurate flow field of a jet using the compressible Navier-Stokes equations, on a variety of parallel architectural platforms. The platforms chosen for this study are a cluster of workstations (the LACE experimental testbed at NASA Lewis), a shared-memory multiprocessor (the CRAY Y-MP), and

In this work, we characterized the impact of operating system activities like process migration on a shared-bus shared-memory multiprocessor running typical DBMS workload. Our workload has been setup utilizing the TPC-D benchmark on the PostgreSQL DBMS. Analysis has been performed via trace driven simulation enhanced technique which includes most important operating system activities and analyzes the sharing overhead in detail. We evaluated a basic four-processor and a high-end sixteen-processor machine, implementing MESI and other coherence protocols that deal with migration of processes and data. Our results show that even in the four-processor case operating system effects may not be neglected. In fact, different coherence protocols can more effectively reduce the effects of process migration. The consequences on performance become more important in high-end machines (16 or more processors). In this case, even little sharing, as we found in DBMS applications can become crucial for system performance. Better speed up may be achieved adopting several alternatives including redesign of kernel data structure. Cache affinity is somewhat useful in reducing migration effect, but it is not effective in every load conditions.

In this work, we characterized the impact of operating system activities like process migration on a shared-bus shared-memory multiprocessor running typical DBMS workload. Our workload has been setup utilizing the TPC-D benchmark on the PostgreSQL DBMS. Analysis has been performed via trace driven simulation enhanced technique which includes most important operating system activities and analyzes the sharing overhead in detail. We evaluated a basic four-processor and a high-end sixteen-processor machine, implementing MESI and other coherence protocols that deal with migration of processes and data. Our results show that even in the four-processor case operating system effects may not be neglected. In fact, different coherence protocols can more effectively reduce the effects of process migration. The consequences on performance become more important in high-end machines (16 or more processors). In this case, even little sharing, as we found in DBMS applications can become crucial for system performance. Better speed up may be achieved adopting several alternatives including redesign of kernel data structure. Cache affinity is somewhat useful in reducing migration effect, but it is not effective in every load conditions.

12 3.3 Characteristics of most time-consuming subroutines of COMMIX-1AR/P for data set Plr0 running in baseline SV mode on Cray X..MP (from PERFTRAC_) ...... 13 3.4 Characteristics of most, time-consuming subroutines of COMMIX-1AR/P for data set Plrl running in baseline SV mode on Cray X-MP (from PERFTRAC_,)...... 13 3.5 Characteristics of most time-consuming subroutines for data set Plr2 running in b_eline SV mode on Cray X-MP (from PERFTRACE). ................. 13 3.6 Characteristics of most time-consuming subroutines for data set P2 running in baseline SV mode on Cray X-MP (from PERrTRACe). 14 3.7 Characteristics of most time-consuming subroutines for data set P3 running in baseline SV mode on Cray X:MP

We describe the design and implementation of Tornado, a new operating system designed from the ground up specifically for today's shared memory multiprocessors. The need for improved locality in the operating system is growing as multiprocessor hardware evolves, increasing the costs for cache misses and sharing, and adding complications due to NUMAness. Tornado is optimized so that locality and independence in application requests for operating system services-whether from multiple sequential applications or a single parallel applicationare mapped onto locality and independence in the servicing of these requests in the kernel and system servers. By contrast, previous shared memory multiprocessor operating systems all evolved from designs constructed at a time when sharing costs were low, memory latency was low and uniform, and caches were small; for these systems, concurrency was the main performance concern and locality was not an important issue. Tornado achieves this locality by starting with an objectoriented structure, where every virtual and physical resource is represented by an independent object. Locality, as well as concurrency, is further enhanced with the introduction of three key innovations: (i) clustered objects that support the partitioning of contended objects across processors, (ii) a protected procedure call facility that preserves the locality and concurrency of IPC's, and (iii) a new locking strategy that allows all locking to be encapsulated within the objects being protected and greatly simplifies the overall locking protocols. As a result of these techniques, Tornado has far better performance characteristics, particularly for multithreaded applications, than existing commercial operating systems. Tornado has been fully implemented and runs both on Toronto's NUMAchine hardware and on the SimOS simulator.

In a modern shared memory multiprocessor, it is possible to support more than one protocol for maintaining cache coherence. Possible candidates might be based on the Write-Back/Invalidate, Write-Through/Invalidate, and Write-Update protocols. Hybrid protocols allow the use of different protocols for different data blocks, and dynamic hybrid protocols additionally allow for changes in the choice of protocol during the execution of an application. In this paper, we introduce a set of analytical models for predicting the performance of parallel applications under various cache coherence protocol assumptions. These models can be used at compile time to determine which protocols are to be used for which data blocks, and also to determine when to change protocols in the case of dynamic protocols. Although we focus on tightly-coupled multiprocessor systems, the models apply equally well to loosely-coupled distributed systems such as networks of workstations. Our models are unique in that they lie between a large body of theoretical models that assume independence and a uniform distribution of memory accesses across processors, and a large body of address-trace oriented models that assume the availability of a precise characterization of interleaving behavior of memory accesses. The former are not very realistic, and the latter are not suitable for compile-time and run-time usage. In contrast, our models use a set of parameters that characterize the access behavior of applications well, and can be obtained with advanced compiler technology. We present the models and show how the required parameters can be obtained. We assess the accuracy of our models on 15 parallel applications and show that we can predict performance within a 10% margin. As part of this study, we also show the potential advantage of using dynamic hybrid protocols. 1. The concept of classifying data by how it is accessed (i.e. degree of sharing and access mode) has also been used by other researches [8, 25-27], although their classification differs slightly from ours.

In the standard kernel organization on a bus-based multiprocessor, all processors share the code and data of the operating system; explicit synchronization is used to control access to kernel data structures. Distributed-memory multicomputers use an alternative approach, in which each instance of the kernel performs local operations directly and uses remote invocation to perform remote operations. Either approach to interkernel communication can be used in a large-scale shared-memory multiprocessor. In the paper we discuss the issues and architectural features that must be considered when choosing between remote memory access and remote invocation. We focus in particular on experience with the Psyche multiprocessor operating system on the BBN Butterfly Plus. We find that the Butterfly architecture is biased towards the use of remote Invocation for kernel operations that perform a significant number of memory references, and that current architectural trends are likely to increase this bias in future machines. This conclusion suggests that straightforward parallelization of existing kernels (e.g. by using semaphores to protect shared data) is unlikely in the future to yield acceptable performance. We note, however, that remote memory access is useful for small, frequently-executed operations, and is likely to remain so. *Eliseu Chaves is with the Universidade Federal do Rio de Janeim, Brazil. He spent six months on leave at the University of Rochester in 1990. Prakash Das is now with Transarc Corp. in Pittsburgh, PA. Brian Marsh is now with the Matsushita Information Technology Lab in Princeton, NJ. 1 t is customary to refer to bus-based machines as UMA (uniform memory access) multiprocessors, but the terminology can be misleading. Main memory (if present) is equally far from all processors, but caches are not, and caches are the dominant determinant of memory performance.

Load balancing is a crucial factor in achieving good performance for parallel discrete event simulations. We present a load balancing scheme that combines both static partitioning and dynamic load balancing. The static partitioning scheme maps simulation ...

Protection and security are becoming essential requirements in commercial servers. In this paper, we present a fast and efficient method for providing secure memory and cache-to-cache communications in shared memory multiprocessor systems that are becoming enormously popular in designing servers for various applications. Since our scheme is independent of underlying interconnects and cache coherence protocols, we refer to it as Interconnects-Independent Security Enhanced Shared Memory Multiprocessor Systems (I 2 SEMS). The main challenge in designing I 2 SEMS is how to precompute keystreams in a timely manner, which is critical to minimize performance overhead. We achieve this goal by adopting a single system-wide Global Counter Controller (GCC) and three additional components for each processor: a keystream queue, a keystream cache, and a keystream pool. The GCC assigns a unique range of counters as a way to help processors precompute the counters' keystreams. We have implemented I 2 SEMS using Simics with Wisconsin multifacet General Execution-driven Multiprocessor Simulator (GEMS). We tested our design with SPLASH-2 benchmarks on up to 16-processor shared memory multiprocessor systems. Simulation results show that the overall performance slowdown is 4% on average and the keystream hit rate is as high as 78%. The stable keystream hit rate shows that I 2 SEMS works well with both memory-read and memory-write dominant applications. Similar to the conventional cache, a large keystream pool size is beneficial to high hit rates.

We constructed a simulation model, using the PAWS simulation modeling tools, to predict the peflormance of a shared memory multiprocessor operating system. The operating system is divided into 5 distinct sections, called empires. We used the model to predict the efficiency of this paradigm of multiprocessing for the Hewlett-Packard HP-UX Release 8.0 operating system. The simulation results show that the empires architecture is effective in providing enough concurrency for a 4-way computer under a program development workload. We will describe the model and its parameters, present and discuss the results, provide a statistical analysis of the data, and analyze the results.

Speculative parallelization aggressively executes in parallel codes that cannot be fully parallelized by the compiler. Past proposals of hardware schemes have mostly focused on single-chip multiprocessors (CMPs), whose effectiveness is necessarily limited by their small size. Very few schemes have attempted this technique in the context of scalable shared-memory systems. In this paper, we present and evaluate a new hardware scheme for scalable speculative parallelization. This design needs relatively simple hardware and is efficiently integrated into a cache-coherent NUMA system. We have designed the scheme in a hierarchical manner that largely abstracts away the internals of the node. We effectively utilize a speculative CMP as the building block for our scheme. Simulations show that the architecture proposed delivers good speedups at a modest hardware cost. For a set of important non-analyzable scientific loops, we report average speedups of 4.2 for 16 processors. We show that sup...

12 3.3 Characteristics of most time-consuming subroutines of COMMIX-1AR/P for data set Plr0 running in baseline SV mode on Cray X..MP (from PERFTRAC_) ...... 13 3.4 Characteristics of most, time-consuming subroutines of COMMIX-1AR/P for data set Plrl running in baseline SV mode on Cray X-MP (from PERFTRAC_,)...... 13 3.5 Characteristics of most time-consuming subroutines for data set Plr2 running in b_eline SV mode on Cray X-MP (from PERFTRACE). ................. 13 3.6 Characteristics of most time-consuming subroutines for data set P2 running in baseline SV mode on Cray X-MP (from PERrTRACe). 14 3.7 Characteristics of most time-consuming subroutines for data set P3 running in baseline SV mode on Cray X:MP

A common operation in multiprocessor programs is acquiring a lock to protect access to shared data. Typically, the requesting thread is blocked if the lock it needs is held by another thread. The cost of blocking one thread and activating another can be a substantial part of program execution time. Alternatively, the thread could spin until the lock is free,

We propose a new parallel Branch and Bound algorithm for the Quadratic Assignment Problem, which is a Combinatorial Optimization problem known to be very hard to solve exactly. An original method to distribute work to processors using the notion of Feeding Tree is presented. When adequately used, it allows to reduce memory contention and load unbalance. Therefore, a linear speed-up in the number of processors is reached on a shared memory multiprocessor, the Cray 2 and the optimality of solutions for famous problems of size less than 20 (Nugent 16, Elshafei 19, Scriabin-Vergin 20,...) is proved by this program. The implementation analysis shows that these results are more than an improvement due to hardware evolution and confirms the usefulness of our parallel Branch and Bound algorithm for larger Quadratic Assignment Problems.

Parallel processing has been proposed as a means of improving network protocol throughput. Several different strategies have been taken towards parallelizing protocols. A relatively popular approach is packet-level parallelism, where packets are distributed across processors. This paper provides an experimental performance study of packet-level parallelism on a contemporary shared-memory multiprocessor. We examine several unexplored areas in packet-level parallelism and investigate how various protocol structuring and implementation techniques can affect performance. We study TCP/IP and UDP/IP protocol stacks, implemented with a parallel version of the x-kernel running in user space on Silicon Graphics multiprocessors. Our results show that only limited packet-level parallelism can be achieved within a single connection under TCP, but that using multiple connections can improve available parallelism. We also demonstrate that packet ordering plays a key role in determining single-con...

Parallelizing compilers for multiprocessors face many hurdles. However, SUIF’s robust analysis and memory optimization techniques enabled speedups on three fourths of the NAS and SPECfp95 benchmark programs. © 1996 IEEE. Reprinted, with permission, from Computer, December 1996, pages 84–89. This paper has been modified for publication here with the addition of the section The Status and Future of SUIF. The affordability of shared memory multiprocessors offers the potential of supercomputer-class performance to the general public. Typically used in a multiprogramming mode, these machines increase throughput by running several independent applications in parallel. But multiple processors can also work together to

Abstract Filtered back projection is a popular algorithm for the reconstruction of n -dimensional signals from their ( n -1)-dimensional projections (in the sense of line integrals). Here we specifically treat the problem of the three-dimensional (3D) reconstruction of an object from its two-dimensional (2D) projection images. In this work we analyze the implementation of the filtered back projection method in shared-memory multiprocessor systems. The resulting parallel algorithm turns out to be scalable as the result of the use of large/medium granularity and an adequate allocation ofdata on the processors. A number of experimental results (such as run time, speed-up and efficiency) on a BBN Butterfly are also reported.