Device Modeling

Green light emission has been measured from Er-doped GaN electroluminescent devices ͑ELDs͒ at an applied bias as low as 5 V. The GaN-Er ELDs were grown by solid source molecular beam epitaxy on Si ͑111͒ substrates. We have achieved this low-voltage operation ͑ten-fold reduction in optical turn-on voltage͒ by using heavily doped ͑ϳ0.01 ⍀ cm͒ Si substrates and by decreasing the GaN-Er layer thickness to several hundred nanometers. A simple device model is presented for the indium tin oxide/GaN-Er/Si/Al ELD. This work demonstrates the voltage excitation efficiency of Er 3ϩ luminescent centers and the compatibility of GaN rare earth-doped ELDs with low-voltage drive circuitry.

This paper compares the temperature-dependent Early voltage of a silicon germanium heterojunction bipolar transistor (HBT) to that of a silicon bipolar junction transistor (BJT) fabricated with identical geometry. Derived is an isothermal expression for the forward Early voltage specifically suited to the base composition of a SiGe HBT. The expression includes two fit factors, one for the Si 10x Ge x alloy and the other for the nonuniform doping density. The fit factors are functions of the device temperature and are determined through pulsed bias measurements.

We find that self-heating effects are not pronounced in silicon nanowire transistors with channel length 10 nm even in the presence of the wrap-around oxide. We observe a maximum current degradation of 6% for V G = V D = 1.0 V in a structure in which the metal gates are far away from the channel. The overall small current degradation is attributed to the significant velocity overshoot effect in these structures. The lattice temperature profile shows moderate temperature rise and velocity of the carriers is slightly deteriorated due to self-heating effects when compared to isothermal simulations. Keywords Analytic bands MC device modeling 1 Motivation for this work As semiconductor devices are scaled into nanometer dimensions [1], a number of issues become important that prevent further transistor scaling. These can be classified into (1) mobility degradation mechanisms (due to increased Coulomb scattering, more pronounced interface roughness due to narrower triangular confinement, line edge roughness, etc.) and (2) statistical effects due to discrete and random nature of the number and position of the impurity atoms

A physics-based model for the Insulated Gate Bipolar Transistor (IGBT) is implemented into the widely available circuit simulation package IG-SPICE. Based on analytical equations describing the semiconductor-physics, the model acboundaries, recombination, and carrier scattering, and effectively predicts the device conductivity modulation. In this paper, the procedure used to incorporate the model into IG-SPICE and various methods necessary to ensure convergence are described. The effectiveness of the SPICE-based IGBT model is demonstrated by investigating the static and dynamic current sharing of paralleled IGBTs with different device model parameters. The simulation p + body region (see ). Thus the IGBT behaves as a bipolar transistor that is supplied base current by a MOSFET as indicated by the simplified equivalent circuit in ~i~. 2.

Electrical current has been recommended for use on chronic wounds; however, the ability of this modality to improve healing of various types of chronic ulcers, arterial, venous, mixed arterial and venous ulcers, diabetic, and pressure ulcers is not well established. The purpose of this study was to examine the eVect of frequency rhytmic electrical modulation system (FREMS) on healing of chronic painful leg ulcers.

An efficient model scheme that combines the nonlinear behaviour of the input parasitics with the intrinsic fundamental device rate equations of the Vertical Cavity Surface Emitting Lasers (VCSELs) is proposed. The model parameter values are extracted using a fully defined systematic technique from dc current-optical power-voltage (I-L-V) and ac S 11 -S 21 response measurements. Extraction and simulation procedures are implemented in commercial integrated circuit design tools. Investigation on their accuracy and efficiency is performed by comparing simulation results with the experimental measurements.

AS CMOS FEATURE size scales downward, the interaction between design and process intensifies, resulting in strong layout-dependent proximity effects. These effects occur because a transistor's electrical properties depend on the context of its placement. 1-4 A MOSFET's channel length L and width W are no longer sufficient to determine its characteristics. Layout parameters such as polysilicon spacing, length of diffusion (LOD), and well boundary placement 5 become necessary to fully model device behavior. At 45 nm, the systematic variation between two transistors of the same L and W can reach more than 30% in drive current (I ON ) and as high as 100 mV in threshold voltage (V TH ). Such strong layout-dependent effects pose challenges to circuit design and demand fundamental changes in modeling and design methodologies.

Compact-modeling principles and solutions for nanoscale double-gate and gate-all-around MOSFETs are explained. The main challenges of compact modeling for these devices are addressed, and different approaches for describing the electrostatics, the transport mechanisms, and the high-frequency behavior are explained. Several approximations used to derive analytical solutions of Poisson's equation for doped and undoped devices are discussed, and the need for self-consistency with Schrödinger's equation and with the current continuity equation resulting from the transport models is addressed. Several techniques to extend the compact modeling to the high-frequency regime and to study the RF performance, including noise, are presented and discussed.

A mobility curve for electrons in MOSFET's inversion charge layer is determined from measured drain current of transistors produced by a wide range of MOS technologies. A comparison between this mobility curve and previously published results shows that a truly universal mobility curve does not exist and only "local" universal mobility curves can be expected, i.e., unique mobility curves which are valid over a finite range of MOS technologies and/or over a particular set of fabrication facilities. However, its basic characteristics of being technology independent over a wide range of process variation point out the potential of using such a local universal mobility curve as a powerful basis for developing predictive device modeling tools. This potential is demonstrated for an analytical MOSFET model and a twodimensional device simulator where the mobility models have the general characteristics of experiment based local universal mobility curves.

Neural-network computational modules have recently gained recognition as an unconventional and useful tool for RF and microwave modeling and design. Neural networks can be trained to learn the behavior of passive/active components/circuits. A trained neural network can be used for high-level design, providing fast and accurate answers to the task it has learned. Neural networks are attractive alternatives to conventional methods such as numerical modeling methods, which could be computationally expensive, or analytical methods which could be difficult to obtain for new devices, or empirical modeling solutions whose range and accuracy may be limited. This tutorial describes fundamental concepts in this emerging area aimed at teaching RF/microwave engineers what neural networks are, why they are useful, when they can be used, and how to use them. Neural-network structures and their training methods are described from the RF/microwave designer's perspective. Electromagnetics-based training for passive component models and physics-based training for active device models are illustrated. Circuit design and yield optimization using passive/active neural models are also presented. A multimedia slide presentation along with narrative audio clips is included in the electronic version of this paper. A hyperlink to the NeuroModeler demonstration software is provided to allow readers practice neural-network-based design concepts.

A systematic methodology for layout optimization of active devices for millimeter-wave (mm-wave) application is proposed. A hybrid mm-wave modeling technique was developed to extend the validity of the device compact models up to 100 GHz. These methods resulted in the design of a customized 90 nm device layout which yields an extrapolated max of 300 GHz from an intrinsic device = 100 GHz. The device is incorporated into a low-power 60 GHz amplifier consuming 10.5 mW, providing 12.2 dB of gain, and an output 1db of +4dBm.Anexperimental three-stage 104 GHz tuned amplifier has a measured peak gain of 9.3 dB. Finally, a Colpitts oscillator operating at 104 GHz delivers up to 5 dBm of output power while consuming 6.5 mW.

A physics-based model for PiN power diodes is developed and implemented as a SPICE subcircuit. The model is based on a distributed equivalent circuit representation of the PiN base region, which is obtained by solving the ambipolar diffusion equation with the finite difference method. The model is validated against experimental characterization that is carried out on the commercial fast recovery power diodes. Comparisons between the results of the SPICE model with experimental and simulation results taken from the literature and from SILVACO mixed-mode simulations are also presented. Finally, the simulation of a realistic power circuit demonstrates the practical suitability of the proposed model for circuit design in terms of computational efficiency, convergence, and robustness. Index Terms-Device modeling, discrete power device, Fast REcovery Diode (FRED), PiN power diode, power semiconductor device.

A physics-based model for PiN power diodes is developed and implemented as a SPICE subcircuit. The model is based on a distributed equivalent circuit representation of the PiN base region, which is obtained by solving the ambipolar diffusion equation with the finite difference method. The model is validated against experimental characterization that is carried out on the commercial fast recovery power diodes. Comparisons between the results of the SPICE model with experimental and simulation results taken from the literature and from SILVACO mixed-mode simulations are also presented. Finally, the simulation of a realistic power circuit demonstrates the practical suitability of the proposed model for circuit design in terms of computational efficiency, convergence, and robustness.

NANOSIL Network of Excellence [NANOSIL NoE web site 〈www.nanosil-noe.eu〉], funded by the European Commission in the 7th Framework Programme (ICT-FP7, no 216171), aims at European scale integration of the excellent European research laboratories and their capabilities in order to strengthen scientific and technological excellence in the field of nanoelectronic materials and devices for terascale integrated circuits (ICs), and to disseminating the results in a wide scientific and industrial community.NANOSIL is exploring and assessing the science and technological aspects of nanodevices and operational regimes relevant to the n+4 technology node and beyond. It encompasses projects on nanoscale CMOS and beyond-CMOS. Innovative concepts, technologies and device architectures are proposed—with fabrication down to the finest features, and utilising a wide spectrum of advanced deposition and processing capabilities, extensive characterization and very rigorous device modeling. This work is carried out through a network of joint processing, characterization and modeling platforms. This critical interaction strengthens European integration in nanoelectronics and will speed up technological innovation for the nanoelectronics of the next two to three decades.

In the present paper, a two-dimensional (2-D) analytical model for graded channel fully depleted cylindrical/surrounding gate MOS-FET (GC FD CGT/SGT) has been developed by solving the Poisson's equation in cylindrical coordinates. An abrupt transition of silicon film doping at the interface has been assumed and the effects of the doping and the lengths of the high and low doped regions have been taken into account. The model is used to obtain the expressions of surface potential and electric field in the two regions. The analysis is extended to obtain the expressions for threshold voltage (V th ) and subthreshold swing. It is shown that a graded doping profile in the channel leads to suppression of short channel effects (SCEs) like threshold voltage roll-off, drain induced barrier lowering (DIBL) and hot carrier effects. The results so obtained have been compared with simulated results obtained using the device simulator ATLAS 3D and are found to be in good agreement.

A drain-current model for undoped symmetric double-gate MOSFETs is proposed. Channel-length modulation and drain-induced barrier lowering are modeled by using an approximate solution of the 2-D Poisson equation. The new model is valid and continuous in linear and saturation regimes, as well as in weak and strong inversions. Excellent agreement was found with Silvaco-ATLAS simulations. Index Terms-Compact device modeling, double gate (DG), MOSFET, short-channel effects.

The comparative analysis of the well known DDR (Double Drift Region) IMPATT diode structure and the new n + pvnp + structure for the avalanche diode has been realized on the basis of the precise numerical model. The new type of the diode was named as the Double Avalanche Region (DAR) IMPATT diode. This structure includes the two avalanche regions inside the diode. The phase delay, which was produced by means of the two avalanche zones and the drift zone v is sufficient for the negative resistance obtain for the wide frequency region. The numerical model that is used for the analysis of the various diode structures includes all the principal features of the physical phenomena inside the semiconductor structure. The admittance characteristics of both types of the diodes were analyzed in very wide frequency region.

In this paper, we report an analytical modeling and 2-D Synopsys Sentaurus TCAD simulation of ion implanted silicon carbide MESFETs. The model has been developed to obtain the threshold voltage, drain-source current, intrinsic parameters such as, gate capacitance, drain-source resistance and transconductance considering different fabrication parameters such as ion dose, ion energy, ion range and annealing effect parameters. The model is useful in determining the ion implantation fabrication parameters from the optimization of the active implanted channel thickness for different ion doses resulting in the desired pinch off voltage needed for high drain current and high breakdown voltage. The drain current of approximately 10 A obtained from the analytical model agrees well with that of the Synopsys Sentaurus TCAD simulation and the breakdown voltage approximately 85 V obtained from the TCAD simulation agrees well with published experimental results. The gate-to-source capacitance and gate-todrain capacitance, drain-source resistance and transconductance were studied to understand the device frequency response. Cut off and maximum frequencies of approximately 10 GHz and 29 GHz respectively were obtained from Sentaurus TCAD and verified by the Smith's chart.

A synchronous buck converter based multiphase architecture is evaluated to determine whether or not the most widespread voltage regulator (VR) topology can meet the power delivery requirements of next-generation computer processors. The applied analysis methodology relies on accurate device models for circuit simulations, where the power MOSFETs are central due to their primary relevance to power losses. The method is referred to as virtual design loop and aims at optimizing the overall system performance with minimum empirical efforts. This is successfully applied to the development of a power MOSFET technology offering outstanding dynamic and static performance characteristics in the application. From a system perspective, the limits of power density conversion will be explored for this and other emerging technologies that promise to open up a new paradigm in power integration capabilities.

Thin-film transistors (TFTs), which use zinc oxide (ZnO) as an active layer, were fabricated and investigated in detail. The transport properties of ZnO deposited by spray pyrolysis (SP) on a TFT structure are studied in a wide range of temperatures, electrical conditions (i.e., subthreshold, above-threshold linear, and saturation regions), and at different channel lengths. It is shown that ZnO deposited by SP is a nanocrystalline material; its field-effect mobility is temperature activated and increases with carrier concentration. On the basis of this analysis, we propose the multiple-trapping-and-release (MTR)-transport mechanism to describe the charge transport in ZnO. By means of numerical simulations, we prove that MTR is a suitable approach, and we calculate the density of states. We show that the tail states extend in a wide range of energy and that they strongly influence the transport properties. Finally, an analytical physical-based DC model is proposed and validated with experiments and numerical simulations. The model is able to reproduce the measurements on devices with different channel length in a wide range of bias voltages and temperatures by means of a restricted number of parameters, which are linked directly to the physical properties of the ZnO semiconductor. For the first time, the charge transport in the ZnO is investigated by means of the MTR, and a consistent Manuscript He is currently an Associate Professor of electronics with the University of Brescia and teaches courses on electronic devices and power electronics. He is the author of more than 100 scientific publications, including international journals, conference proceedings, and international patents. His research interests include various aspects of microelectronics, including device physics and characterization, current transport in semiconductor materials and devices, amorphous and organic thin-film transistors, submicrometer metal-oxide-semiconductor field-effect-transistor design, the numerical analysis of semiconductor devices, integrated analog circuit design, electromagnetic interference analysis, low-power portable ultrawideband radars, and integrated voltage converters. Zsolt M. Kovacs-Vajna (M'90-SM'00) received the D.Eng. degree (with honors) and the Ph.D. degree in electronics engineering and computer sciences from

A simple analytical model has been developed to simulate the performance of solar cells with polysilicon contact on the front surface. The polysilicon layer with a columnar grain structure is modeled by an effective recombination velocity using a two-dimensional transport equation. A one-dimensional transport equation in the single-crystal emitter is solved, taking into account bulk recombination and non-uniformly doped emitter. Then, simple analytical expressions for the emitter reverse saturation current and light-generated current densities are obtained. The collection of the light-generated carriers in polysilicon layer has been discussed and an analytical solution of the light-generated current is derived. The results show that the polysilicon layer can result in a decrease in emitter reverse saturation current density and an increase in solar cell photovoltaic parameters. In fact, the emitter region should not be treated as a ‘dead layer’ because thin polysilicon layer front surface contact gives an improvement of about 60 mV for the open-circuit voltage, 3.6 mA/cm2 for the photocurrent, and 3.9% for the cell efficiency.

Since VHDL-AMS standard has been set up (IEEE 1076.1, March 1999), this hardware description language has been used many times for modeling active power devices, such as "Smart Power" devices (diodes, power MOSFETs, IGBTs, ...). Libraries of Power Electrical Engineering Models can be built with these models, but "passive" devices models are often missing although they are much more important and complex than in micro-electronics. This paper presents the opportunity that VHDL-AMS may offer by adding complementary modeling advantages in active devices (self-heating in power MOSFETs, for instance), in passive power components and by suggesting a possible strategy for building a library of reusable models for power electrical engineering.

The design of analog and RF circuits in CMOS technology has become increasingly more difficult as device modeling faces new challenges in the deep-submicrometer regime and emerging circuit applications. In this paper, we investigate the influence of both channel and gate engineering on the analog and RF performances of double-gate (DG) MOSFETs for system-on-chip applications. The gate engineering technique used here is the dualmetal gate technology, and the channel engineering technique is the conventional halo doping process. For analog applications, importance is given to the subthreshold regime as CMOS circuits operated in this regime are very much attractive for ultralow-power high-gain performances. Gate-and channel-engineered devices show an increase of gain by 45% and 35%, respectively, compared with the single-metal DG MOSFET. The gate-engineered device shows an improvement of 21.6% and 20% in the case of f T and f MAX values, whereas the channel-engineered device exhibits a reduction of f T by 2.7% with nearly equal f MAX .

The aim of the study is to find a method to model electromagnetic devices which generate consequent magnetic leakage. Classical methods have proved to be efficient but time consuming. The method proposed in this paper is based on the magnetic moment method (MMM). An original methodology to obtain a simplified MMM model is described, adjusted with simple RNM model results. Besides the good accuracy, the simplicity of the model makes it possible to consider complicated studies with reasonable resolution times.

We have developed compact and physics-based distributed numerical models for cryogenic bulk MOSFET operation down to 20 K to advance simulation and first-pass design of device and circuit operation at low temperatures. To achieve this, we measured and simulated temperature-dependent current-voltage characteristics of 0.16-and 0.18-µm bulk MOSFETs. Our measurements indicate that these MOSFETs supply approximately 40% more current in the saturation and linear regions of operation when they are cooled from room temperature to 20 K. The threshold voltage monotonically increases as the temperature is lowered, but it saturates below 40 K. The subthreshold slope decreases with the temperature lowering but at a rate that is less than theoretically predicted. The extrapolation of the subthreshold slope indicates a finite value at near absolute zero. We show that the measured behavior can be well corroborated with distributed numerical simulations using the drift-diffusion transport model. In addition, to obtain a compact model for use in low-temperature circuit design, SPICE-type compact models need to be modified to incorporate the subtle temperature effects that are not part of the standard models. To this end, we use the analog behavioral language Verilog-A and the BSIM3 model equation set to include additional temperature dependences into the standard compact models to accurately reproduce measured characteristics.

Heterojunction with intrinsic thin layer or "HIT" solar cells are considered favorable for large-scale manufacturing of solar modules, as they combine the high efficiency of crystalline silicon ͑c-Si͒ solar cells, with the low cost of amorphous silicon technology. In this article, based on experimental data published by Sanyo, we simulate the performance of a series of HIT cells on N-type crystalline silicon substrates with hydrogenated amorphous silicon ͑a-Si:H͒ emitter layers, to gain insight into carrier transport and the general functioning of these devices. Both single and double HIT structures are modeled, beginning with the initial Sanyo cells having low open circuit voltages but high fill factors, right up to double HIT cells exhibiting record values for both parameters. The one-dimensional numerical modeling program "Amorphous Semiconductor Device Modeling Program" has been used for this purpose. We show that the simulations can correctly reproduce the electrical characteristics and temperature dependence for a set of devices with varying I-layer thickness. Under standard AM1.5 illumination, we show that the transport is dominated by the diffusion mechanism, similar to conventional P/N homojunction solar cells, and tunneling is not required to describe the performance of state-of-the art devices. Also modeling has been used to study the sensitivity of N-c-Si HIT solar cell performance to various parameters. We find that the solar cell output is particularly sensitive to the defect states on the surface of the c-Si wafer facing the emitter, to the indium tin oxide/P-a-Si:H front contact barrier height and to the band gap and activation energy of the P-a-Si:H emitter, while the I-a-Si:H layer is necessary to achieve both high V oc and fill factor, as it passivates the defects on the surface of the c-Si wafer. Finally, we describe in detail for most parameters how they affect current transport and cell properties.

The importance of long term reliability in MOS VLSI circuits is becoming an important subject because of the increasing densities of VLSI chips. Hot carrier effects cause noncatastrophic failures which develop gradually over time and change the circuit performance.

Pseudo-MOSFETs (9-MOSFET) are routinely used for silicon-on-insulator (SOI) material characterization, allowing threshold voltage, electron and hole mobility, doping density, oxide charge, interface trap density, etc. to be determined. The HgFET, one version of the 9-MOSFET, uses mercury source and drain contacts. It is a very effective SOI test structure, but its currentvoltage behavior is critically dependent on the Hg-Si interface. We have investigated this interface through current-voltage measurements of HgFETs and Schottky diodes and through device modeling. We show that modest barrier height changes of 0.2 eV lead to current changes of up to three orders of magnitude. Etching the Si surface in a mild HF : H 2 O solution can easily change barrier heights and we attribute this behavior to Si surface passivation of dangling bonds. As this surface passivation diminishes with time, the Si surface becomes a more active generation site and the barrier height of the Hg-Si interface changes, taking on the order of 50-100 h at room temperature in air.

It has previously been reported that the lateral electric field (E x ) in the drain extension of thin SOI HV (700V) field plate assisted RESURF devices can be extracted from their I D -V D characteristics in the subthreshold regime. In this work the prerequisites for valid field extraction and the (voltage) range of validity are established for linearly graded drain extension based RESURF devices through a combination of analytical calculations and TCAD device modeling. It is shown that the most important condition for field extraction is that an increment dV DS should not affect the lateral field at the already depleted zone. This unique condition is found to be met in the drain extension at distances larger than a specific length (5.3λ ) governed by the drain extension silicon and oxide thicknesses. For realistic device parameters the method is shown to hold for devices with a BV DS of ∼ 150V and higher.

Because of their superior radiation resistance, three-dimensional (3D) silicon sensors are receiving more and more interest for application in the innermost layers of tracker systems for experiments running in very high luminosity colliders. Their short electrode distance allows for both a low depletion voltage and a high charge collection efficiency even at extremely high radiation fluences. In order to fully understand the properties of a 3D detector, a thorough characterization of the signal formation mechanism is of paramount importance. In this work the shape of the current induced by localized and uniform charge depositions in a single-type column 3D detector is studied. A first row estimation is given applying the Ramo theorem, then a more complete TCAD simulation is used to provide a more realistic pulse shape. r 2007 Published by Elsevier B.V.

Device modeling plays an important role in VLSI circuit design because computer-aided circuit analysis results are only as accurate as the models used. This indicates a need for robust tools that can facilitate the testing, validation and characterization procedure of semiconductor device models. Certify, the graphical tool for model characterization and validation, is a step in this direction [1]. The

In the context of the ACRä (Advanced CANDU Reactor), 3D transport calculations are required in order to simulate the reactivity devices located perpendicularly to the fuel channels. The computational scheme that is usually used for CANDU-6 and ACR reactors is based on a simplified supercell geometry in which the fuel clusters and devices are replaced by annuli. Recently, an exact modeling of 3D supercell configurations was introduced within the framework of the ACR calculations. However, with such a model, fine meshing requirements lead to problems that are very demanding in terms of computational resources.

We present an analytical device model for a field-effect transistor based on a heterostructure which consists of an array of nanoribbons clad between the highly conducting substrate (the back gate) and the top gate controlling the source-drain current. The equations of the model of a graphene nanoribbon field-effect transistor (GNR-FET) include the Poisson equation in the weak nonlocality approximation. Using this model, we find explicit analytical formulas for the spatial distributions of the electric potential along the channel and for the GNR-FET current-voltage characteristics (the dependences of the source-drain current on the drain voltages as well as on the back gate and top gate voltages) for different geometric parameters of the device. It is shown that the shortening of the top gate can result in a substantial modification of the GNR-FET current-voltage characteristics.

We describe an electronic transport model and an implementation approach that respond to the challenges of device modeling for gigascale integration. We use the density-gradient (DG) transport model, which adds tunneling and quantum smoothing of carrier density profiles to the driftdiffusion model. We present the current implementation of the DG model in PROPHET, a partial differential equation solver developed by Lucent Technologies. This implementation approach permits rapid development and enhancement of models, as well as run-time modifications and model switching. We show that even in typical bulk transport devices such as P-N diodes and BJTs, DG quantum effects can significantly modify the I-V characteristics. Quantum effects are shown to be even more significant in small, surface transport devices, such as sub-0.1µm MOS-FETs. In thin-oxide MOS capacitors, we find that quantum effects may reduce gate capacitance by 25% or more. The inclusion of quantum effects in simulations dramatically improves the match between C-V simulations and measurements. Significant quantum corrections also occur in the I-V characteristics of short-channel MOSFETs due to the gate capacitance correction.

An international interlaboratory comparison for numerical calculations of head phantom SAR involving three mobile phones with computer-aided design-based models has been conducted in order to evaluate the repeatability of such calculations and for providing input in the development of standardized procedures. SAR in the standardized specific anthropomorphic mannequin (SAM) head phantom was calculated by ten laboratories in a blind study manner. The agreement in calculated SAR between the participating laboratories is very similar to the agreement obtained in interlaboratory comparisons involving SAR measurements. The results support the opinion that standardized procedures for numerical calculations of SAR can be developed. The agreement between calculated SAR results and corresponding measurement results ranges from good to poor for the three phone models. Most probably, a significant reason for the observed deviations is the simplifications made to the models, which implies that device modeling specifications are of utmost importance in standards.

A detailed investigation of the device operation of a blue-emitting multilayer organic light-emitting device (OLED) using an electronic device model is presented. In particular, a transient electroluminescence overshoot at turn-on is found to originate from charge and recombination confinement effects at internal interfaces. The location of the emission zone is obtained from the electronic model and its experimental determination exemplified by a sensing layer method. Moreover, the optimization of emission intensity and color is discussed for a red-emitting OLED. The thin-film interference effects are analyzed with help of an optical device model.

Abstract—Neural-network computational modules have re-cently gained recognition as an unconventional and useful tool for RF and microwave modeling and design. Neural networks can be trained to learn the behavior of passive/active components/circuits. A trained neural network can ...

A constructive theory of randomness for functions, based on computational complexity, is developed, and a pseudorandom function generator is presented. This generator is a deterministic polynomial-time algorithm that transforms pairs (g, r), where g is any one-way function and r is a random k-bit string, to polynomial-time computable functionsf,: { 1, . . . , 2') + { 1, . . . , 2kl. Thesef,'s cannot be distinguished from random functions by any probabilistic polynomial-time algorithm that asks and receives the value of a function at arguments of its choice. The result has applications in cryptography, random constructions, and complexity theory.

In this paper, we demonstrate analytical device models and a unique subcircuit approach to physically and accurately model the dopant-segregated Schottky (DSS) gate-all-around (GAA) Si-nanowire (SiNW) MOSFETs. The direct current characteristics of the DSS GAA SiNW MOSFETs are investigated through numerical simulations and fabricated devices. Transport mechanisms are studied and explained with numerical devices from ambipolar thermionic tunneling to unipolar drift-diffusion and a combination of both as the dopant segregation doping and thickness are varied. The convex curvature in the I ds -V ds characteristics is accurately reproduced by the subcircuit compact model, and it is shown for the first time that such a unique g ds -V ds characteristic in DSS devices is only feasible to be modeled by the subcircuit approach. Index Terms-Ambipolar, compact model, dopant-segregated Schottky (DSS), drift-diffusion (DD), gate-all-around (GAA), gate-induced drain leakage (GIDL), MOSFET, Schottky barrier (SB), subcircuit, thermionic tunneling (TT), unipolar.

The paper presents a general approach to numerically simulate the noise behavior of bipolar solid-state electron devices through a physics-based multidimensional device model. The proposed technique accounts for noise sources due to carrier velocity and population fluctuations. The power and correlation spectra of the external current or voltage fluctuations are evaluated through a Green's function, linear perturbation theory equivalent to the classical Impedance Field Method for noise analysis and its generalizations. The numerical implementation of the method is performed through an efficient technique, which allows noise analysis to be carried out with negligible overhead with respect to the small-signal simulation. Some case studies are analyzed in order to compare the present approach with theoretical results from the classical noise theory of pn junctions and bipolar transistors.

Capability and accuracy of microwave measuring methods and instruments can be substantially improved by the use of general-purpose digital computers. One of the fruitful applications is concerned with redundant measurements and their evaluation. In a redundant measurement more data are measured than would be necessary for a singular evaluation and the excess information is used to reduce measurement errors.

IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, VOL. 44, NO. 6, JUNE 1996 ... Transistors Using a Full-Wave Time-Domain :Model ... Mohammad A. Alsunaidi, S. M. Sohel Imtiaz, Student Member, IEEE, and Samir M. El-Ghazaly, Senior Member, IEEE

Type-II GaAsSb/InP double heterojunction bipolar transistors (DHBTs) with a novel InGaAsP ledge structure were studied utilizing a 2-D hydrodynamic physical device model for the first time. The proposed ultrathin InGaAsP ledge design provides a simple and effective approach to suppress the emitter size effect and enables nanoscale GaAsSb/InP DHBTs to further increase the operating frequencies and integration levels for submillimeterwave applications.

Artificial Neural Networks are emerging as a powerful technology for RF and microwave characterization, modeling, and design. Neuron Modeler is the first software in the industry that embraces this technology with complete RF and microwave orientation. It helps you to immediately start developing neural models for RFMicrowave components and circuits and helps to provide neural models for your simulators. The device is modeled by a black box whose small signal and noise parameters are evaluated through a neural network, based upon the fitting of both of these parameters for the multiple bias or configuration. In this study, two types of neural network were compared for the existing device modeling technique, The concurrent modeling procedure does not require solving device physics equations repeatedly during optimization.

This paper presents a complete 0.13 m SiGe BiCMOS technology fully dedicated to millimeter-wave applications, including a high-speed (230/280 GHz f T f MAX ) and medium voltage SiGe HBT, thick-copper back-end designed for high performance transmission lines and inductors, 2 fF m 2 high-linearity MIM capacitor and complementary double gate oxide MOS transistors. Details are given on HBT integration, reliability and models as well as on back-end devices models.