A analytical and explicit drain-current equation has been derived for undoped symmetric double-ga... more A analytical and explicit drain-current equation has been derived for undoped symmetric double-gate MOSFETs. This current equation is expressed clearly with surface potential and verified with numerical results both in the subthreshold and the saturation region. It facilitates the calculation of drain current if only the surface potential is known, which is suitable for compact model development.
A compact model for the surface and mid-gap potentials of doped symmetric double-gate MOSFETs is ... more A compact model for the surface and mid-gap potentials of doped symmetric double-gate MOSFETs is presented. A unified regional approach is used to derive the model equations from Poisson equation. The fully-depleted double-gate MOSFET has four regions of operation, accumulation, depletion, weak or volume inversion, and strong inversion. The model is derived physically in all regions, with expressions for the flat-band, fully-depleted, and threshold voltages scalable over silicon channel doping and thickness, and unified to obtain a single-piece explicit model for the surface potential and mid-gap potential. The model has been verified in comparison with numerical device potentials, charges, and capacitances for various channel doping and thickness.
Introductory question: best models and approaches to various MOS structures and operations? Strai... more Introductory question: best models and approaches to various MOS structures and operations? Strained-Si heterostructure channel Doped symmetric-DG Undoped DG/SOI Latest: Doped asymmetric-DG Application and results Summary and conclusions Unified view and unification of MOS models Unified regional approach Continuum Transformation: FET to BJT Continuum Transformation: FET to BJT WCM 2006 MSM / Nanotech X. ZHOU 3 Similar transformation from classical bulk-MOS to non-classical SOI/MG MOSFETs? Field effect Potential effect Courtesy: S. M. Sze, High-speed semiconductor devices, Wiley, 1990. MOSFET Compact Models: History and Future MOSFET Compact Models: History and Future WCM 2006 MSM / Nanotech X. ZHOU 4 Sah-Pao (input) Voltage Equation Pao-Sah (output) Current Equation Ļ s -based Q i -based V t -based Q b linearization Q i linearization Iterative / explicit 1966 1978 1985 1995 2006 Poisson + GCA Classical bulk-CMOS Non-classical CMOS Charge Sheet Model (Q sc =Q b +Q i ) BSIM BSIM PSP PSP 40 yrs SOI SOI MG MG Bulk Voltage/Current Equations, CSM New Voltage/Current Equations
This paper presents the calibration methodology for our unified length/width-dependent MOSFET dra... more This paper presents the calibration methodology for our unified length/width-dependent MOSFET drain-current (I ds) model with length/width-dependent threshold-voltage (V t) model in the entire geometry/bias range based on a 0.11-Āµm CMOS technology. The model has been formulated with built-in physical effects to account for electrical characteristics of fabricated short-channel/narrow-width devices while maintaining Gummel symmetry. Through a one-iteration parameter extraction using minimum measurement data, the model can predict accurately and physically the experimental IāV data, including output conductance, transconductance, and their derivatives.
ESSDERC 2008 - 38th European Solid-State Device Research Conference, 2008
ABSTRACT A physics-based compact model for undoped symmetric double-gate MOSFETs with Schottky-ba... more ABSTRACT A physics-based compact model for undoped symmetric double-gate MOSFETs with Schottky-barrier source and drain is formulated based on the quasi-2D surface-potential solution and Miller-Good tunneling method. Essential physics due to the screening of the gate field by free carriers, which is absent in previous literatures, is included in the model. Electron and hole transports for all positive/negative gate/drain biases are modeled within the single-piece core model that scales with device geometry, body/oxide thickness, SB workfunction, and source/drain contact size. Unlike 2D numerical simulation, the proposed compact model, which is simple and fast yet accurate, is circuit-compatible and suitable for future VLSI circuit design using SB-MOS devices. The proposed modeling methodology can be easily extended to handle other promising devices such as SB silicon nanowires.
2007 7th IEEE Conference on Nanotechnology (IEEE NANO), 2007
A non-charge-sheet surface-potential-based compact drain-current model for long-channel undoped g... more A non-charge-sheet surface-potential-based compact drain-current model for long-channel undoped gate-all-around (GAA) silicon-nanowire (SiNW) MOSFETs is developed. The surface-potential equation is derived from cylindrical Poisson equation for undoped silicon and solved iteratively with a very good initial guess to reach equation residue below 10-16 V within a few iterations. The single-piece current equation is derived and validated with numerical simulations for
Inductors that can be integrated on a silicon chip have been reported in the literature. This has... more Inductors that can be integrated on a silicon chip have been reported in the literature. This has lead to the development of silicon RF integrated circuits (RFICs) where previously discrete component inductors had to be used. Now the size of circuits can be greatly reduced with the integration of RF circuits or even complete systems on a silicon chip. This has raised enormous interest in the study of the on-chip inductor. This paper presents a comparison of various inductor expressions available in the literature. Error trends are highlighted and discussed in the 1 to 10 nH inductance region. The focus of the design is the square spiral inductor. The details of the 'new-physic' closed-form expression is found to be the most accurate expression and its implication to inductor synthesis is discussed.
Demand for mixed signal and RF devices on 0.18 Ī¼m CMOS silicon is driving the Foundry industry to... more Demand for mixed signal and RF devices on 0.18 Ī¼m CMOS silicon is driving the Foundry industry to rapidly incorporate these additional modules. This paper reports on the electrical characteristics and optimization of four mixed signal devices. Using a modular approach, Deep N-well isolated RF transistors, Native transistors, Inductors, and MIM capacitors were successfully integrated into our major Foundry Compatible 0.18 Ī¼m CMOS Logic process, without adversely affecting the digital devices. Twenty-nine different inductor structures were built and evaluated. The presence of Deep N-well implant under the inductors greatly reduced Qpeak. Self Resonance Frequency was dominated by factors controlling capacitive coupling to the substrate (line width, number of coil turns).
This paper reviews the basic governing equations for a double-gate/gate-all-around (DG/GAA) MOSFE... more This paper reviews the basic governing equations for a double-gate/gate-all-around (DG/GAA) MOSFET in a generic and unified description. Starting from generic Poisson solution and input voltage equation, a paradigm shift with ground-reference and source/drain by label is proposed, which is essential in formulating equations for DG FinFETs without body contact. The unified regional modeling (URM) approach is used for unified
A physics-based single-piece charge model for strained-silicon (s-Si) MOSFETs from accumulation t... more A physics-based single-piece charge model for strained-silicon (s-Si) MOSFETs from accumulation to strong-inversion regions is presented. The model is formulated from regional solutions of the well-known Pao-Sah equation and unified with interpolation functions while keeping the physics in the derived flat-band voltages that depend on the device material and structural parameters, such as band gaps, conduction and valence band offsets, Ge mole fraction, layer thickness, and doping. The model is validated by comparison with numerical devices for a wide range of Ge mole fractions and s-Si layer thicknesses. It is shown that the model accurately describes the physical behavior of the surface potentials, terminal charges and capacitances, especially charge accumulation/depletion at the s-Si/SiGe interface that gives rise to the observed "plateau" in the capacitance-voltage characteristics.
This paper reviews the development of the MOSFET model (Xsim), for unification of various types o... more This paper reviews the development of the MOSFET model (Xsim), for unification of various types of MOS devices, such as bulk, partially/fully-depleted SOI, double-gate (DG) FinFETs and gate-all-around (GAA) silicon-nanowires (SiNWs), based on the unified regional modeling (URM) approach. The complete scaling of body doping and thickness with seamless transitions from one structure to another is achieved with the unified regional surface potential, in which other effects (such as those due to poly-gate doping and quantum-mechanical) can be incorporated. The unique features of the Xsim model and the essence of the URM approach are described.
A new technique for calculating surface and interface potentials in heterostructure MOSFETs such ... more A new technique for calculating surface and interface potentials in heterostructure MOSFETs such as strained-Si/SiGe using an internal iteration approach is presented. It is based on the unified regional approach with coupled iterative potential solutions at the surface and heterostructure interface, and it has been applied to modeling strained-Si/SiGe MOSFETs charge and capacitance in all bias regions, scalable for Ge mole fraction, strained-Si and SiGe layer thicknesses and doping. The formulations are shown for a buried-channel nMOSFET, and the approach to the solutions is generic to all heterostructures, which exhibit confinement of carriers at the different interfaces.
The effect of substrate doping on the capacitance-voltage characteristics of a surface-channel st... more The effect of substrate doping on the capacitance-voltage characteristics of a surface-channel strained-silicon p-channel MOSFET has been studied to explain a measured anomalous behavior in which a "plateau" in the accumulation region was observed. It is found that this plateau is substrate doping dependent and it switches from a plateau on the inversion side to that on the accumulation side as the substrate doping increases. The physics behind this behavior has been explained by the one-dimensional Poisson solution and validated with numerical simulations and experimental data.
This paper presents a methodology for extraction of the physical parameters of strained-silicon M... more This paper presents a methodology for extraction of the physical parameters of strained-silicon MOSFET from one capacitance-voltage (C-V) measurement based on physics-based compact model and conventional C-V characterization techniques. The extracted physical parameters (such as strained-silicon layer thickness and doping as well as conduction band offset) are used to create a numerical (Medici) device structure, from which the simulated C-V data is compared with the measured data as well as that from the compact model (Xsim), which validates the extraction technique. The proposed approach provides a simple yet physical means to probe into strained-silicon MOSFFET structures useful for characterize and model these devices, which are emerged as promising candidates for the enhancement and extension to conventional bulk-Si CMOS technology.
In existing impact-ionization current (I sub ) models for short-channel MOSFETs, various models f... more In existing impact-ionization current (I sub ) models for short-channel MOSFETs, various models for the characteristic ionization length (l) or the velocity-saturation region length (l sat ) have been developed by using the polynomial-fitting method in order to model the bias dependence of the maximum electric field (E m ) in the channel. This paper proposes a bias-voltage-and gate-length-dependent effective maximum electric field (E m,eff ) based on energy-balance equation, aimed at obtaining an accurate expression of E m to increase the accuracy of the I sub model for deep submicrometer devices. This new method overcomes the complicated modeling of l, avoids the extraction of different fitting constants for different devices, and enables unique extraction of the impact-ionization coefficients (A and B) for different devices. This improved model demonstrates excellent agreements with the numerical data of nMOSFETs from a 90-nm-technology wafer file. Only one unique set of parameters is needed to fit the data from devices with different biases and lengths for the same technology node. Moreover, since the lattice temperature (T l ) is built in the formulation of E m,eff , a compact I sub model with self-lattice-heating is developed, which also accounts for the excess substrate current observed in the SOI devices due to carrier heating in the channel.
A analytical and explicit drain-current equation has been derived for undoped symmetric double-ga... more A analytical and explicit drain-current equation has been derived for undoped symmetric double-gate MOSFETs. This current equation is expressed clearly with surface potential and verified with numerical results both in the subthreshold and the saturation region. It facilitates the calculation of drain current if only the surface potential is known, which is suitable for compact model development.
A compact model for the surface and mid-gap potentials of doped symmetric double-gate MOSFETs is ... more A compact model for the surface and mid-gap potentials of doped symmetric double-gate MOSFETs is presented. A unified regional approach is used to derive the model equations from Poisson equation. The fully-depleted double-gate MOSFET has four regions of operation, accumulation, depletion, weak or volume inversion, and strong inversion. The model is derived physically in all regions, with expressions for the flat-band, fully-depleted, and threshold voltages scalable over silicon channel doping and thickness, and unified to obtain a single-piece explicit model for the surface potential and mid-gap potential. The model has been verified in comparison with numerical device potentials, charges, and capacitances for various channel doping and thickness.
Introductory question: best models and approaches to various MOS structures and operations? Strai... more Introductory question: best models and approaches to various MOS structures and operations? Strained-Si heterostructure channel Doped symmetric-DG Undoped DG/SOI Latest: Doped asymmetric-DG Application and results Summary and conclusions Unified view and unification of MOS models Unified regional approach Continuum Transformation: FET to BJT Continuum Transformation: FET to BJT WCM 2006 MSM / Nanotech X. ZHOU 3 Similar transformation from classical bulk-MOS to non-classical SOI/MG MOSFETs? Field effect Potential effect Courtesy: S. M. Sze, High-speed semiconductor devices, Wiley, 1990. MOSFET Compact Models: History and Future MOSFET Compact Models: History and Future WCM 2006 MSM / Nanotech X. ZHOU 4 Sah-Pao (input) Voltage Equation Pao-Sah (output) Current Equation Ļ s -based Q i -based V t -based Q b linearization Q i linearization Iterative / explicit 1966 1978 1985 1995 2006 Poisson + GCA Classical bulk-CMOS Non-classical CMOS Charge Sheet Model (Q sc =Q b +Q i ) BSIM BSIM PSP PSP 40 yrs SOI SOI MG MG Bulk Voltage/Current Equations, CSM New Voltage/Current Equations
This paper presents the calibration methodology for our unified length/width-dependent MOSFET dra... more This paper presents the calibration methodology for our unified length/width-dependent MOSFET drain-current (I ds) model with length/width-dependent threshold-voltage (V t) model in the entire geometry/bias range based on a 0.11-Āµm CMOS technology. The model has been formulated with built-in physical effects to account for electrical characteristics of fabricated short-channel/narrow-width devices while maintaining Gummel symmetry. Through a one-iteration parameter extraction using minimum measurement data, the model can predict accurately and physically the experimental IāV data, including output conductance, transconductance, and their derivatives.
ESSDERC 2008 - 38th European Solid-State Device Research Conference, 2008
ABSTRACT A physics-based compact model for undoped symmetric double-gate MOSFETs with Schottky-ba... more ABSTRACT A physics-based compact model for undoped symmetric double-gate MOSFETs with Schottky-barrier source and drain is formulated based on the quasi-2D surface-potential solution and Miller-Good tunneling method. Essential physics due to the screening of the gate field by free carriers, which is absent in previous literatures, is included in the model. Electron and hole transports for all positive/negative gate/drain biases are modeled within the single-piece core model that scales with device geometry, body/oxide thickness, SB workfunction, and source/drain contact size. Unlike 2D numerical simulation, the proposed compact model, which is simple and fast yet accurate, is circuit-compatible and suitable for future VLSI circuit design using SB-MOS devices. The proposed modeling methodology can be easily extended to handle other promising devices such as SB silicon nanowires.
2007 7th IEEE Conference on Nanotechnology (IEEE NANO), 2007
A non-charge-sheet surface-potential-based compact drain-current model for long-channel undoped g... more A non-charge-sheet surface-potential-based compact drain-current model for long-channel undoped gate-all-around (GAA) silicon-nanowire (SiNW) MOSFETs is developed. The surface-potential equation is derived from cylindrical Poisson equation for undoped silicon and solved iteratively with a very good initial guess to reach equation residue below 10-16 V within a few iterations. The single-piece current equation is derived and validated with numerical simulations for
Inductors that can be integrated on a silicon chip have been reported in the literature. This has... more Inductors that can be integrated on a silicon chip have been reported in the literature. This has lead to the development of silicon RF integrated circuits (RFICs) where previously discrete component inductors had to be used. Now the size of circuits can be greatly reduced with the integration of RF circuits or even complete systems on a silicon chip. This has raised enormous interest in the study of the on-chip inductor. This paper presents a comparison of various inductor expressions available in the literature. Error trends are highlighted and discussed in the 1 to 10 nH inductance region. The focus of the design is the square spiral inductor. The details of the 'new-physic' closed-form expression is found to be the most accurate expression and its implication to inductor synthesis is discussed.
Demand for mixed signal and RF devices on 0.18 Ī¼m CMOS silicon is driving the Foundry industry to... more Demand for mixed signal and RF devices on 0.18 Ī¼m CMOS silicon is driving the Foundry industry to rapidly incorporate these additional modules. This paper reports on the electrical characteristics and optimization of four mixed signal devices. Using a modular approach, Deep N-well isolated RF transistors, Native transistors, Inductors, and MIM capacitors were successfully integrated into our major Foundry Compatible 0.18 Ī¼m CMOS Logic process, without adversely affecting the digital devices. Twenty-nine different inductor structures were built and evaluated. The presence of Deep N-well implant under the inductors greatly reduced Qpeak. Self Resonance Frequency was dominated by factors controlling capacitive coupling to the substrate (line width, number of coil turns).
This paper reviews the basic governing equations for a double-gate/gate-all-around (DG/GAA) MOSFE... more This paper reviews the basic governing equations for a double-gate/gate-all-around (DG/GAA) MOSFET in a generic and unified description. Starting from generic Poisson solution and input voltage equation, a paradigm shift with ground-reference and source/drain by label is proposed, which is essential in formulating equations for DG FinFETs without body contact. The unified regional modeling (URM) approach is used for unified
A physics-based single-piece charge model for strained-silicon (s-Si) MOSFETs from accumulation t... more A physics-based single-piece charge model for strained-silicon (s-Si) MOSFETs from accumulation to strong-inversion regions is presented. The model is formulated from regional solutions of the well-known Pao-Sah equation and unified with interpolation functions while keeping the physics in the derived flat-band voltages that depend on the device material and structural parameters, such as band gaps, conduction and valence band offsets, Ge mole fraction, layer thickness, and doping. The model is validated by comparison with numerical devices for a wide range of Ge mole fractions and s-Si layer thicknesses. It is shown that the model accurately describes the physical behavior of the surface potentials, terminal charges and capacitances, especially charge accumulation/depletion at the s-Si/SiGe interface that gives rise to the observed "plateau" in the capacitance-voltage characteristics.
This paper reviews the development of the MOSFET model (Xsim), for unification of various types o... more This paper reviews the development of the MOSFET model (Xsim), for unification of various types of MOS devices, such as bulk, partially/fully-depleted SOI, double-gate (DG) FinFETs and gate-all-around (GAA) silicon-nanowires (SiNWs), based on the unified regional modeling (URM) approach. The complete scaling of body doping and thickness with seamless transitions from one structure to another is achieved with the unified regional surface potential, in which other effects (such as those due to poly-gate doping and quantum-mechanical) can be incorporated. The unique features of the Xsim model and the essence of the URM approach are described.
A new technique for calculating surface and interface potentials in heterostructure MOSFETs such ... more A new technique for calculating surface and interface potentials in heterostructure MOSFETs such as strained-Si/SiGe using an internal iteration approach is presented. It is based on the unified regional approach with coupled iterative potential solutions at the surface and heterostructure interface, and it has been applied to modeling strained-Si/SiGe MOSFETs charge and capacitance in all bias regions, scalable for Ge mole fraction, strained-Si and SiGe layer thicknesses and doping. The formulations are shown for a buried-channel nMOSFET, and the approach to the solutions is generic to all heterostructures, which exhibit confinement of carriers at the different interfaces.
The effect of substrate doping on the capacitance-voltage characteristics of a surface-channel st... more The effect of substrate doping on the capacitance-voltage characteristics of a surface-channel strained-silicon p-channel MOSFET has been studied to explain a measured anomalous behavior in which a "plateau" in the accumulation region was observed. It is found that this plateau is substrate doping dependent and it switches from a plateau on the inversion side to that on the accumulation side as the substrate doping increases. The physics behind this behavior has been explained by the one-dimensional Poisson solution and validated with numerical simulations and experimental data.
This paper presents a methodology for extraction of the physical parameters of strained-silicon M... more This paper presents a methodology for extraction of the physical parameters of strained-silicon MOSFET from one capacitance-voltage (C-V) measurement based on physics-based compact model and conventional C-V characterization techniques. The extracted physical parameters (such as strained-silicon layer thickness and doping as well as conduction band offset) are used to create a numerical (Medici) device structure, from which the simulated C-V data is compared with the measured data as well as that from the compact model (Xsim), which validates the extraction technique. The proposed approach provides a simple yet physical means to probe into strained-silicon MOSFFET structures useful for characterize and model these devices, which are emerged as promising candidates for the enhancement and extension to conventional bulk-Si CMOS technology.
In existing impact-ionization current (I sub ) models for short-channel MOSFETs, various models f... more In existing impact-ionization current (I sub ) models for short-channel MOSFETs, various models for the characteristic ionization length (l) or the velocity-saturation region length (l sat ) have been developed by using the polynomial-fitting method in order to model the bias dependence of the maximum electric field (E m ) in the channel. This paper proposes a bias-voltage-and gate-length-dependent effective maximum electric field (E m,eff ) based on energy-balance equation, aimed at obtaining an accurate expression of E m to increase the accuracy of the I sub model for deep submicrometer devices. This new method overcomes the complicated modeling of l, avoids the extraction of different fitting constants for different devices, and enables unique extraction of the impact-ionization coefficients (A and B) for different devices. This improved model demonstrates excellent agreements with the numerical data of nMOSFETs from a 90-nm-technology wafer file. Only one unique set of parameters is needed to fit the data from devices with different biases and lengths for the same technology node. Moreover, since the lattice temperature (T l ) is built in the formulation of E m,eff , a compact I sub model with self-lattice-heating is developed, which also accounts for the excess substrate current observed in the SOI devices due to carrier heating in the channel.
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Papers by Guan Huei See