IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1993
Absfracf-? his paper proposer a [io\ el electrical method for determining two of the most importa... more Absfracf-? his paper proposer a [io\ el electrical method for determining two of the most important RIOSk formance parameters, the phjsical dimension (trode at the gate oxide interface (hottoni dimension) arid the on-state (substrate in h e r r i o n) fringing capacitance of the gate. For characteriiatioii, the method requires simple capacitors, fabricated uring identical procersing rteps that dfiect the dimen5ions of a RIOSFET's gate electrode. rhe required data are quasi-static C-\ niearurenients at t i r o or more hiaser. The phg\ical bask and potential accuracj of this characteriiatioii method ha\e been \eritifd. based on detailed t\\o-din~enrioiial numerical deb ice simulation. 1 hir proposed method ~iotentiall\ can he applied to monitor process \ ariationr and to rtudier of the cause-effect relation het\\een processes arid de\ ice pertormance. I n addition, the accurate determination of these paranieterr from de\ice wafers is fundamentall! required for calibrating ph) \icall> based t\+o-dinienrional prow\\ and de\ ice \imulators, and improb ing their predicthe capahilit!.
When Government drawings, specifications, or other data are used for any purpose other than in co... more When Government drawings, specifications, or other data are used for any purpose other than in connection with a definitely related Government procurement operation, the United States Government thereby incurs no responsibility nor any obligation whatsoever; and the fact that the government may have formulated, furnished, or in any way supplied the said drawings, specir-cations, or other data, is not to be regarded by implication or otherwie as in any manner licensing the holder or any other person or corporetion, or conveying any rights or permission to manufacture use, or sell any patented invention that may in any way be related thereto. This report has been reviewed by the Office of Public Affairs (ASD/PA) and is releasable to the National Technical Information Service (NTIS). At NTIS, it will be available to the general public, including foreign nations. This technical report has been reviewed and is approved for publication.
A closed-loop evaluation of a saturation transconductance (g msat(i)) based method for determinin... more A closed-loop evaluation of a saturation transconductance (g msat(i)) based method for determining the scattering limited carrier velocity (νsat) in enhancement MOSFETs was performed with the use of a 2-D device simulator. Consistency in the extracted νsat over a wide range of gate oxide thickness (Tox), channel doping concentration, and bias condition was tested and verified. Also analyzed are the appropriate measurement condition, the significance of the parasitic effect due to the source and drain resistances, the applicability of the method used for compensating this parasitic effect, and the expected accuracy of the extracted νsat under ideal conditions. A plausible explanation is provided for the inconsistency between νsat determined from gmsat(i)(0), the extrapolated transconductance, and νsat determined from the slope of [ gmsat(i)(0)]-1 versus T ox characteristics observed in published results. The gmsat (i)-based method for extracting νsat has been applied to MOSFETs fabricated with three vastly different technologies, and the experimentally-based νsat of electrons at 300 K ranges from 7.37×106 to 7.92×106 cm/s, which shows its independence of technology
the metallurgical channel length of MOSFET, is proposed in this paper. This method has been exten... more the metallurgical channel length of MOSFET, is proposed in this paper. This method has been extensively evaluated via twodimensional numerical device simulation of MOSFET's with different source/drain tip and channel impurity concentration profiles as well as different gate oxide thicknesses. For all the impurity profiles tested, results demonstrated that the accuracy in extracting Lrrlrt of MOSFET's with gate oxides thinner than 100 A is better than 110 W. This method is applicable even when there is significant source/drain reoxidation induced gate oxide thickening, as long as the gate oxide thickening is not extended into the region directly above the metallurgically defined channel region. Unlike the determination of Lee, the effective electrical channel length, from the drain current, LlrlrI is extracted from capacitance data and the extraction is free from complications that can be introduced by incomplete removal of the resistive effects associated with contacts and the lightly doped source/drain region. Extensive measurements were performed on MOSFET's of different technologies. It is shown that the measurement is accurately repeatable and no device stressing is experienced over the required bias range. The Let and L,m extracted from measured capacitance and drain current data are compared.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1989
A mobility curve for electrons in MOSFET's inversion charge layer is determined from measured dra... more A mobility curve for electrons in MOSFET's inversion charge layer is determined from measured drain current of transistors produced by a wide range of MOS technologies. A comparison between this mobility curve and previously published results shows that a truly universal mobility curve does not exist and only "local" universal mobility curves can be expected, i.e., unique mobility curves which are valid over a finite range of MOS technologies and/or over a particular set of fabrication facilities. However, its basic characteristics of being technology independent over a wide range of process variation point out the potential of using such a local universal mobility curve as a powerful basis for developing predictive device modeling tools. This potential is demonstrated for an analytical MOSFET model and a twodimensional device simulator where the mobility models have the general characteristics of experiment based local universal mobility curves.
This paper presents a new and physical modeling approach for neutron SER with excellent accuracy ... more This paper presents a new and physical modeling approach for neutron SER with excellent accuracy demonstrated on SRAMs fabricated using 0.18pm CMOS technology. The SER contribution of each type of recoil ion and a fast roll-off behavior of neutron SER for high QCRIT nodes are reported for the first time.
1999 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.99CH36325), 1999
Soft errors (single event upset) due to alpha particles from radioactive impurities in packaging ... more Soft errors (single event upset) due to alpha particles from radioactive impurities in packaging materials were first observed on DRAMs. While terrestrial cosmic rays also cause soft errors and dominate logic circuit soft-error rate (SER), alpha-SER contributes significantly to SRAM circuit total SER and increases at a higher rate as processing technology advances to sub-0.25 μm feature sizes where even
International Conferencre on Simulation of Semiconductor Processes and Devices, 2002
This paper highlights the emerging need for selective integration of physical-model based TCAD mo... more This paper highlights the emerging need for selective integration of physical-model based TCAD modeling and simulation tools that have been mostly applied to technology development with ECAD tools that have been traditionally used for product design. The emerging technology trends that lead to this paradigm shift are highlighted. The architecture and requirements of integrated TCAD-ECAD solutions are also discussed along
The circuit performance of CMOS technologies with silicon dioxide (SiO2) and reoxidized nitrided ... more The circuit performance of CMOS technologies with silicon dioxide (SiO2) and reoxidized nitrided oxide (RONO) gate dielectrics over the normal regime of digital circuit operation, i.e. VGS⩽5 V and BDS⩽5 V, is discussed. The simulation of a simple CMOS inverter has shown that the SiO2 inverter consistently outperforms the RONO inverter over temperatures ranging from 300 to 100 K. This
IEEE 14th Topical Meeting on Electrical Performance of Electronic Packaging, 2005., 2000
This paper presents a novel surface-based finite element method for full-wave modeling of largesc... more This paper presents a novel surface-based finite element method for full-wave modeling of largescale 3D physical circuits. In contrast to traditional fmiite element methods that involve 3D volumetric unknowns, this method reduces the unknowns one needs to solve to those on 2D surface elements of interest only. It preserves the advantages of the finite element method in circuit application such as the flexibility in modeling irregular geometry, the capability in handling arbitrary inhomogeneity, and the handling of sparse matrices. Meanwhile, it eliminates the disadvantages long associated with traditional finite element methods such as large memory requirement and high CPU cost resulted from 3D volumetric discretization. Experimental and numerical results are given to demonstrate its accuracy and computational efficiency.
1999 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.99CH36325), 1999
Soft errors (single event upset) due to alpha particles from radioactive impurities in packaging ... more Soft errors (single event upset) due to alpha particles from radioactive impurities in packaging materials were first observed on DRAMs. While terrestrial cosmic rays also cause soft errors and dominate logic circuit soft-error rate (SER), alpha-SER contributes significantly to SRAM circuit total SER and increases at a higher rate as processing technology advances to sub-0.25 μm feature sizes where even
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1993
Absfracf-? his paper proposer a [io\ el electrical method for determining two of the most importa... more Absfracf-? his paper proposer a [io\ el electrical method for determining two of the most important RIOSk formance parameters, the phjsical dimension (trode at the gate oxide interface (hottoni dimension) arid the on-state (substrate in h e r r i o n) fringing capacitance of the gate. For characteriiatioii, the method requires simple capacitors, fabricated uring identical procersing rteps that dfiect the dimen5ions of a RIOSFET's gate electrode. rhe required data are quasi-static C-\ niearurenients at t i r o or more hiaser. The phg\ical bask and potential accuracj of this characteriiatioii method ha\e been \eritifd. based on detailed t\\o-din~enrioiial numerical deb ice simulation. 1 hir proposed method ~iotentiall\ can he applied to monitor process \ ariationr and to rtudier of the cause-effect relation het\\een processes arid de\ ice pertormance. I n addition, the accurate determination of these paranieterr from de\ice wafers is fundamentall! required for calibrating ph) \icall> based t\+o-dinienrional prow\\ and de\ ice \imulators, and improb ing their predicthe capahilit!.
When Government drawings, specifications, or other data are used for any purpose other than in co... more When Government drawings, specifications, or other data are used for any purpose other than in connection with a definitely related Government procurement operation, the United States Government thereby incurs no responsibility nor any obligation whatsoever; and the fact that the government may have formulated, furnished, or in any way supplied the said drawings, specir-cations, or other data, is not to be regarded by implication or otherwie as in any manner licensing the holder or any other person or corporetion, or conveying any rights or permission to manufacture use, or sell any patented invention that may in any way be related thereto. This report has been reviewed by the Office of Public Affairs (ASD/PA) and is releasable to the National Technical Information Service (NTIS). At NTIS, it will be available to the general public, including foreign nations. This technical report has been reviewed and is approved for publication.
A closed-loop evaluation of a saturation transconductance (g msat(i)) based method for determinin... more A closed-loop evaluation of a saturation transconductance (g msat(i)) based method for determining the scattering limited carrier velocity (νsat) in enhancement MOSFETs was performed with the use of a 2-D device simulator. Consistency in the extracted νsat over a wide range of gate oxide thickness (Tox), channel doping concentration, and bias condition was tested and verified. Also analyzed are the appropriate measurement condition, the significance of the parasitic effect due to the source and drain resistances, the applicability of the method used for compensating this parasitic effect, and the expected accuracy of the extracted νsat under ideal conditions. A plausible explanation is provided for the inconsistency between νsat determined from gmsat(i)(0), the extrapolated transconductance, and νsat determined from the slope of [ gmsat(i)(0)]-1 versus T ox characteristics observed in published results. The gmsat (i)-based method for extracting νsat has been applied to MOSFETs fabricated with three vastly different technologies, and the experimentally-based νsat of electrons at 300 K ranges from 7.37×106 to 7.92×106 cm/s, which shows its independence of technology
the metallurgical channel length of MOSFET, is proposed in this paper. This method has been exten... more the metallurgical channel length of MOSFET, is proposed in this paper. This method has been extensively evaluated via twodimensional numerical device simulation of MOSFET's with different source/drain tip and channel impurity concentration profiles as well as different gate oxide thicknesses. For all the impurity profiles tested, results demonstrated that the accuracy in extracting Lrrlrt of MOSFET's with gate oxides thinner than 100 A is better than 110 W. This method is applicable even when there is significant source/drain reoxidation induced gate oxide thickening, as long as the gate oxide thickening is not extended into the region directly above the metallurgically defined channel region. Unlike the determination of Lee, the effective electrical channel length, from the drain current, LlrlrI is extracted from capacitance data and the extraction is free from complications that can be introduced by incomplete removal of the resistive effects associated with contacts and the lightly doped source/drain region. Extensive measurements were performed on MOSFET's of different technologies. It is shown that the measurement is accurately repeatable and no device stressing is experienced over the required bias range. The Let and L,m extracted from measured capacitance and drain current data are compared.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1989
A mobility curve for electrons in MOSFET's inversion charge layer is determined from measured dra... more A mobility curve for electrons in MOSFET's inversion charge layer is determined from measured drain current of transistors produced by a wide range of MOS technologies. A comparison between this mobility curve and previously published results shows that a truly universal mobility curve does not exist and only "local" universal mobility curves can be expected, i.e., unique mobility curves which are valid over a finite range of MOS technologies and/or over a particular set of fabrication facilities. However, its basic characteristics of being technology independent over a wide range of process variation point out the potential of using such a local universal mobility curve as a powerful basis for developing predictive device modeling tools. This potential is demonstrated for an analytical MOSFET model and a twodimensional device simulator where the mobility models have the general characteristics of experiment based local universal mobility curves.
This paper presents a new and physical modeling approach for neutron SER with excellent accuracy ... more This paper presents a new and physical modeling approach for neutron SER with excellent accuracy demonstrated on SRAMs fabricated using 0.18pm CMOS technology. The SER contribution of each type of recoil ion and a fast roll-off behavior of neutron SER for high QCRIT nodes are reported for the first time.
1999 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.99CH36325), 1999
Soft errors (single event upset) due to alpha particles from radioactive impurities in packaging ... more Soft errors (single event upset) due to alpha particles from radioactive impurities in packaging materials were first observed on DRAMs. While terrestrial cosmic rays also cause soft errors and dominate logic circuit soft-error rate (SER), alpha-SER contributes significantly to SRAM circuit total SER and increases at a higher rate as processing technology advances to sub-0.25 μm feature sizes where even
International Conferencre on Simulation of Semiconductor Processes and Devices, 2002
This paper highlights the emerging need for selective integration of physical-model based TCAD mo... more This paper highlights the emerging need for selective integration of physical-model based TCAD modeling and simulation tools that have been mostly applied to technology development with ECAD tools that have been traditionally used for product design. The emerging technology trends that lead to this paradigm shift are highlighted. The architecture and requirements of integrated TCAD-ECAD solutions are also discussed along
The circuit performance of CMOS technologies with silicon dioxide (SiO2) and reoxidized nitrided ... more The circuit performance of CMOS technologies with silicon dioxide (SiO2) and reoxidized nitrided oxide (RONO) gate dielectrics over the normal regime of digital circuit operation, i.e. VGS⩽5 V and BDS⩽5 V, is discussed. The simulation of a simple CMOS inverter has shown that the SiO2 inverter consistently outperforms the RONO inverter over temperatures ranging from 300 to 100 K. This
IEEE 14th Topical Meeting on Electrical Performance of Electronic Packaging, 2005., 2000
This paper presents a novel surface-based finite element method for full-wave modeling of largesc... more This paper presents a novel surface-based finite element method for full-wave modeling of largescale 3D physical circuits. In contrast to traditional fmiite element methods that involve 3D volumetric unknowns, this method reduces the unknowns one needs to solve to those on 2D surface elements of interest only. It preserves the advantages of the finite element method in circuit application such as the flexibility in modeling irregular geometry, the capability in handling arbitrary inhomogeneity, and the handling of sparse matrices. Meanwhile, it eliminates the disadvantages long associated with traditional finite element methods such as large memory requirement and high CPU cost resulted from 3D volumetric discretization. Experimental and numerical results are given to demonstrate its accuracy and computational efficiency.
1999 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.99CH36325), 1999
Soft errors (single event upset) due to alpha particles from radioactive impurities in packaging ... more Soft errors (single event upset) due to alpha particles from radioactive impurities in packaging materials were first observed on DRAMs. While terrestrial cosmic rays also cause soft errors and dominate logic circuit soft-error rate (SER), alpha-SER contributes significantly to SRAM circuit total SER and increases at a higher rate as processing technology advances to sub-0.25 μm feature sizes where even
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Papers by Shiuh-Wuu Lee