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    VLSI Design: Dept. of CSE Bangladesh University

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    Rasd sda
    This document provides an overview of CMOS VLSI design. It discusses how transistors are built on a silicon substrate and doped to be either n-type or p-type semiconductors. The document describes how nMOS and pMOS transistors function as electrically controlled switches based on the voltage applied to the gate. Basic CMOS logic gates like inverters and NAND gates are constructed by combining nMOS and pMOS transistors.

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    VLSI Design: Dept. of CSE Bangladesh University

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    Rasd sda
    17 views15 pages
    This document provides an overview of CMOS VLSI design. It discusses how transistors are built on a silicon substrate and doped to be either n-type or p-type semiconductors. The document describes how nMOS and pMOS transistors function as electrically controlled switches based on the voltage applied to the gate. Basic CMOS logic gates like inverters and NAND gates are constructed by combining nMOS and pMOS transistors.

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    VLSI_2

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    This document provides an overview of CMOS VLSI design. It discusses how transistors are built on a silicon substrate and doped to be either n-type or p-type semiconductors. The document describes how nMOS and pMOS transistors function as electrically controlled switches based on the voltage applied to the gate. Basic CMOS logic gates like inverters and NAND gates are constructed by combining nMOS and pMOS transistors.

    Copyright:

    © All Rights Reserved
    Download as PPTX, PDF, TXT or read online from Scribd
    Download as pptx, pdf, or txt
    17 views15 pages

    VLSI Design: Dept. of CSE Bangladesh University

    Uploaded by

    Rasd sda
    This document provides an overview of CMOS VLSI design. It discusses how transistors are built on a silicon substrate and doped to be either n-type or p-type semiconductors. The document describes how nMOS and pMOS transistors function as electrically controlled switches based on the voltage applied to the gate. Basic CMOS logic gates like inverters and NAND gates are constructed by combining nMOS and pMOS transistors.

    Copyright:

    © All Rights Reserved
    Download as PPTX, PDF, TXT or read online from Scribd
    Download as pptx, pdf, or txt
    of 15

    VLSI Design

    CSE-316

    nMOS and cMOS

    Dept. of CSE
    Bangladesh University
    CMOS VLSI Design 4th Ed.
    Silicon Lattice
     Transistors are built on a silicon substrate
     Silicon is a Group IV material
     Forms crystal lattice with bonds to four neighbors

    Si Si Si

    Si Si Si

    Si Si Si

    CMOS VLSI Design 4th Ed. 2


    Dopants
     Silicon is a semiconductor
     Pure silicon has no free carriers and conducts poorly
     Adding dopants increases the conductivity
     Group V: extra electron (n-type)
     Group III: missing electron, called hole (p-type)

    Si Si Si Si Si Si
    - +

    + -
    Si As Si Si B Si

    Si Si Si Si Si Si

    CMOS VLSI Design 4th Ed. 3


    p-n Junctions
     A junction between p-type and n-type semiconductor
    forms a diode.
     Current flows only in one direction

    p-type n-type

    anode cathode

    CMOS VLSI Design 4th Ed. 4


    nMOS Transistor
     Four terminals: gate, source, drain, body
     Gate – oxide – body stack looks like a capacitor
    – Gate and body are conductors
    – SiO2 (oxide) is a very good insulator
    – Called metal – oxide – semiconductor (MOS)
    capacitor Source Gate Drain
    Polysilicon
    – Even though gate is
    SiO2
    no longer made of metal*
    n+ n+
    Body
    p bulk Si
    * Metal gates are returning today!

    CMOS VLSI Design 4th Ed. 5


    nMOS Operation
     Body is usually tied to ground (0 V)
     When the gate is at a low voltage:
    – P-type body is at low voltage
    – Source-body and drain-body diodes are OFF
    – No current flows, transistor is OFF
    Source Gate Drain
    Polysilicon
    SiO2

    0
    n+ n+
    S D
    p bulk Si

    CMOS VLSI Design 4th Ed. 6


    nMOS Operation Cont.
     When the gate is at a high voltage:
    – Positive charge on gate of MOS capacitor
    – Negative charge attracted to body
    – Inverts a channel under gate to n-type
    – Now current can flow through n-type silicon from
    source through channel to drain, transistor is ON
    Source Gate Drain
    Polysilicon
    SiO2

    1
    n+ n+
    S D
    p bulk Si

    CMOS VLSI Design 4th Ed. 7


    pMOS Transistor
     Similar, but doping and voltages reversed
    – Body tied to high voltage (VDD)
    – Gate low: transistor ON
    – Gate high: transistor OFF
    – Bubble indicates inverted behavior
    Source Gate Drain
    Polysilicon
    SiO2

    p+ p+

    n bulk Si

    CMOS VLSI Design 4th Ed. 8


    Power Supply Voltage
     GND = 0 V
     In 1980’s, VDD = 5V
     VDD has decreased in modern processes
    – High VDD would damage modern tiny transistors
    – Lower VDD saves power
     VDD = 3.3, 2.5, 1.8, 1.5, 1.2, 1.0, …

    CMOS VLSI Design 4th Ed. 9


    Transistors as Switches
     We can view MOS transistors as electrically
    controlled switches
     Voltage at gate controls path from source to drain
    g=0 g=1

    d d d
    nMOS g OFF
    ON
    s s s

    d d d

    pMOS g OFF
    ON
    s s s

    CMOS VLSI Design 4th Ed. 10


    CMOS Inverter

    A Y VDD
    0 1
    1 0 OFF
    ON
    0
    1
    A Y
    ON
    OFF

    A Y
    GND
    CMOS VLSI Design 4th Ed. 11
    CMOS NAND Gate
    A B Y
    0 0 1 ON
    OFF
    ON
    OFF OFF
    ON
    0 1 1
    1
    Y
    1 0 1 0
    A ON
    OFF
    1 1 0
    0
    1
    1
    0
    B OFF
    ON
    ON
    OFF

    CMOS VLSI Design 4th Ed. 12


    CMOS NOR Gate
    A B Y
    0 0 A
    0 1
    1 0 B
    1 1 Y

    CMOS VLSI Design 4th Ed. 13


    3-input NAND Gate
     Y pulls low if ALL inputs are 1
     Y pulls high if ANY input is 0

    Y
    A
    B
    C

    CMOS VLSI Design 4th Ed. 14


    pMOS Logic

    CMOS VLSI Design 4th Ed.

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