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    Lecture 04

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    mekalajesi
    The document describes the CMOS fabrication process which involves depositing and etching materials onto a silicon wafer through a series of lithography steps to build up transistors and wires. Key steps include growing an oxide layer, depositing polysilicon for gates, and using masks to implant dopants or diffuse them into the silicon to create source, drain, and well regions. Metals are then deposited and patterned to connect the transistors and form logic gates such as inverters and NAND gates on the integrated circuit.

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    Lecture 04

    Uploaded by

    mekalajesi
    76 views39 pages
    The document describes the CMOS fabrication process which involves depositing and etching materials onto a silicon wafer through a series of lithography steps to build up transistors and wires. Key steps include growing an oxide layer, depositing polysilicon for gates, and using masks to implant dopants or diffuse them into the silicon to create source, drain, and well regions. Metals are then deposited and patterned to connect the transistors and form logic gates such as inverters and NAND gates on the integrated circuit.

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    Lecture 04

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    The document describes the CMOS fabrication process which involves depositing and etching materials onto a silicon wafer through a series of lithography steps to build up transistors and wires. Key steps include growing an oxide layer, depositing polysilicon for gates, and using masks to implant dopants or diffuse them into the silicon to create source, drain, and well regions. Metals are then deposited and patterned to connect the transistors and form logic gates such as inverters and NAND gates on the integrated circuit.

    Copyright:

    Attribution Non-Commercial (BY-NC)
    Download as PPT, PDF, TXT or read online from Scribd
    Download as ppt, pdf, or txt
    76 views39 pages

    Lecture 04

    Uploaded by

    mekalajesi
    The document describes the CMOS fabrication process which involves depositing and etching materials onto a silicon wafer through a series of lithography steps to build up transistors and wires. Key steps include growing an oxide layer, depositing polysilicon for gates, and using masks to implant dopants or diffuse them into the silicon to create source, drain, and well regions. Metals are then deposited and patterned to connect the transistors and form logic gates such as inverters and NAND gates on the integrated circuit.

    Copyright:

    Attribution Non-Commercial (BY-NC)
    Download as PPT, PDF, TXT or read online from Scribd
    Download as ppt, pdf, or txt
    of 39

    EE466: CMOS VLSI

    Lecture 04: Fabrication

    CMOS Fabrication
    CMOS transistors are fabricated on silicon wafer Lithography process similar to printing press On each step, different materials are deposited or etched Easiest to understand by viewing both top and cross-section of wafer in a simplified manufacturing process

    0: Introduction

    CMOS VLSI Design

    Slide 2

    Inverter Cross-section
    Typically use p-type substrate for nMOS transistors Requires n-well for body of pMOS transistors
    A GND Y VDD SiO2 n+ diffusion n+ n+ p substrate nMOS transistor pMOS transistor p+ n well p+ p+ diffusion polysilicon metal1

    0: Introduction

    CMOS VLSI Design

    Slide 3

    Well and Substrate Taps


    Substrate must be tied to GND and n-well to VDD Metal to lightly-doped semiconductor forms poor connection called Shottky Diode Use heavily doped well and substrate contacts / taps
    A GND Y VDD

    p+

    n+

    n+ p substrate

    p+ n well

    p+

    n+

    substrate tap

    well tap

    0: Introduction

    CMOS VLSI Design

    Slide 4

    Inverter Mask Set


    Transistors and wires are defined by masks Cross-section taken along dashed line

    GND nMOS transistor substrate tap pMOS transistor well tap

    VDD

    0: Introduction

    CMOS VLSI Design

    Slide 5

    Detailed Mask Views


    Six masks n-well Polysilicon n+ diffusion p+ diffusion Contact Metal
    n well

    Polysilicon

    n+ Diffusion

    p+ Diffusion

    Contact

    Metal

    0: Introduction

    CMOS VLSI Design

    Slide 6

    Fabrication Steps
    Start with blank wafer Build inverter from the bottom up First step will be to form the n-well Cover wafer with protective layer of SiO2 (oxide) Remove layer where n-well should be built Implant or diffuse n dopants into exposed wafer Strip off SiO2

    p substrate

    0: Introduction

    CMOS VLSI Design

    Slide 7

    Oxidation
    Grow SiO2 on top of Si wafer 900 1200 C with H2O or O2 in oxidation furnace

    SiO2

    p substrate

    0: Introduction

    CMOS VLSI Design

    Slide 8

    Photoresist
    Spin on photoresist Photoresist is a light-sensitive organic polymer Softens where exposed to light

    Photoresist SiO2

    p substrate

    0: Introduction

    CMOS VLSI Design

    Slide 9

    Lithography
    Expose photoresist through n-well mask Strip off exposed photoresist

    Photoresist SiO2

    p substrate

    0: Introduction

    CMOS VLSI Design

    Slide 10

    Etch
    Etch oxide with hydrofluoric acid (HF) Seeps through skin and eats bone; nasty stuff!!! Only attacks oxide where resist has been exposed

    Photoresist SiO2

    p substrate

    0: Introduction

    CMOS VLSI Design

    Slide 11

    Strip Photoresist
    Strip off remaining photoresist Use mixture of acids called piranah etch Necessary so resist doesnt melt in next step

    SiO2

    p substrate

    0: Introduction

    CMOS VLSI Design

    Slide 12

    n-well
    n-well is formed with diffusion or ion implantation Diffusion Place wafer in furnace with arsenic gas Heat until As atoms diffuse into exposed Si Ion Implanatation Blast wafer with beam of As ions Ions blocked by SiO2, only enter exposed Si
    SiO2 n well

    0: Introduction

    CMOS VLSI Design

    Slide 13

    Strip Oxide
    Strip off the remaining oxide using HF Back to bare wafer with n-well Subsequent steps involve similar series of steps

    n well p substrate

    0: Introduction

    CMOS VLSI Design

    Slide 14

    Polysilicon
    Deposit very thin layer of gate oxide < 20 (6-7 atomic layers) Chemical Vapor Deposition (CVD) of silicon layer Place wafer in furnace with Silane gas (SiH4) Forms many small crystals called polysilicon Heavily doped to be good conductor
    Polysilicon Thin gate oxide n well p substrate

    0: Introduction

    CMOS VLSI Design

    Slide 15

    Polysilicon Patterning
    Use same lithography process to pattern polysilicon

    Polysilicon

    Polysilicon Thin gate oxide n well p substrate

    0: Introduction

    CMOS VLSI Design

    Slide 16

    Self-Aligned Process
    Use oxide and masking to expose where n+ dopants should be diffused or implanted N-diffusion forms nMOS source, drain, and n-well contact

    n well p substrate

    0: Introduction

    CMOS VLSI Design

    Slide 17

    N-diffusion
    Pattern oxide and form n+ regions Self-aligned process where gate blocks diffusion Polysilicon is better than metal for self-aligned gates because it doesnt melt during later processing

    n+ Diffusion

    n well p substrate

    0: Introduction

    CMOS VLSI Design

    Slide 18

    N-diffusion cont.
    Historically dopants were diffused Usually ion implantation today But regions are still called diffusion

    n+

    n+ n well p substrate

    n+

    0: Introduction

    CMOS VLSI Design

    Slide 19

    N-diffusion cont.
    Strip off oxide to complete patterning step

    n+

    n+ n well p substrate

    n+

    0: Introduction

    CMOS VLSI Design

    Slide 20

    P-Diffusion
    Similar set of steps form p+ diffusion regions for pMOS source and drain and substrate contact

    p+ Diffusion

    p+

    n+

    n+ p substrate

    p+ n well

    p+

    n+

    0: Introduction

    CMOS VLSI Design

    Slide 21

    Contacts
    Now we need to wire together the devices Cover chip with thick field oxide Etch oxide where contact cuts are needed

    Contact

    Thick field oxide p+ n+ n+ p substrate p+ n well p+ n+

    0: Introduction

    CMOS VLSI Design

    Slide 22

    Metalization
    Sputter on aluminum over whole wafer Pattern to remove excess metal, leaving wires

    Metal

    Metal Thick field oxide p+ n+ n+ p substrate p+ n well p+ n+

    0: Introduction

    CMOS VLSI Design

    Slide 23

    Transistors as Switches
    We can view MOS transistors as electrically controlled switches Voltage at gate controls path from source to drain
    g=0 d nMOS g s s d ON s s s d OFF s d OFF g=1 d ON

    d pMOS g

    0: Introduction

    CMOS VLSI Design

    Slide 24

    CMOS Inverter
    A
    0 1

    VDD A Y

    GND
    0: Introduction CMOS VLSI Design Slide 25

    CMOS Inverter
    A
    0 1 0

    VDD OFF
    A=1 Y=0

    ON
    A Y

    GND
    0: Introduction CMOS VLSI Design Slide 26

    CMOS Inverter
    A
    0 1

    Y
    1 0

    VDD ON
    A=0 Y=1

    OFF
    A Y

    GND
    0: Introduction CMOS VLSI Design Slide 27

    CMOS NAND Gate


    A 0 0 B 0 1 Y

    Y A B

    1
    1

    0
    1

    0: Introduction

    CMOS VLSI Design

    Slide 28

    CMOS NAND Gate


    A 0 0 B 0 1 Y 1

    ON A=0 B=0

    ON Y=1 OFF OFF

    1
    1

    0
    1

    0: Introduction

    CMOS VLSI Design

    Slide 29

    CMOS NAND Gate


    A 0 0 B 0 1 Y 1 1

    OFF A=0 B=1

    ON Y=1 OFF ON

    1
    1

    0
    1

    0: Introduction

    CMOS VLSI Design

    Slide 30

    CMOS NAND Gate


    A 0 0 B 0 1 Y 1 1

    ON A=1 B=0

    OFF Y=1 ON OFF

    1
    1

    0
    1

    0: Introduction

    CMOS VLSI Design

    Slide 31

    CMOS NAND Gate


    A 0 0 B 0 1 Y 1 1

    OFF A=1 B=1

    OFF Y=0 ON ON

    1
    1

    0
    1

    1
    0

    0: Introduction

    CMOS VLSI Design

    Slide 32

    CMOS NOR Gate


    A 0 0 B 0 1 Y 1 0

    A B Y

    1
    1

    0
    1

    0
    0

    0: Introduction

    CMOS VLSI Design

    Slide 33

    3-input NAND Gate


    Y pulls low if ALL inputs are 1 Y pulls high if ANY input is 0

    0: Introduction

    CMOS VLSI Design

    Slide 34

    3-input NAND Gate


    Y pulls low if ALL inputs are 1 Y pulls high if ANY input is 0

    Y A B C
    0: Introduction CMOS VLSI Design Slide 35

    Layout
    Chips are specified with set of masks Minimum dimensions of masks determine transistor size (and hence speed, cost, and power) Feature size f = distance between source and drain Set by minimum width of polysilicon Feature size improves 30% every 3 years or so Normalize for feature size when describing design rules Express rules in terms of l = f/2 E.g. l = 0.3 mm in 0.6 mm process
    0: Introduction CMOS VLSI Design Slide 36

    Simplified Design Rules


    Conservative rules to get you started

    0: Introduction

    CMOS VLSI Design

    Slide 37

    Inverter Layout
    Transistor dimensions specified as Width / Length Minimum size is 4l / 2l, sometimes called 1 unit In f = 0.6 mm process, this is 1.2 mm wide, 0.6 mm long

    0: Introduction

    CMOS VLSI Design

    Slide 38

    Summary
    MOS Transistors are stack of gate, oxide, silicon Can be viewed as electrically controlled switches Build logic gates out of switches Draw masks to specify layout of transistors

    Now you know everything necessary to start designing schematics and layout for a simple chip!

    0: Introduction

    CMOS VLSI Design

    Slide 39

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