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    Ee466: Cmos Vlsi: Lecture 04: Fabrication

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    The document describes the CMOS fabrication process which involves depositing and etching various materials on a silicon wafer through multiple lithography steps to build up transistors layer by layer. First, an n-well is implanted through a mask, then a thin gate oxide and polysilicon layer are deposited, followed by n-type and p-type diffusion masks to form the transistor sources and drains. Contact cuts are etched and an aluminum metal layer is deposited to connect the transistors, forming inverters, NAND gates, and more complex logic functions.

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    Ee466: Cmos Vlsi: Lecture 04: Fabrication

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    The document describes the CMOS fabrication process which involves depositing and etching various materials on a silicon wafer through multiple lithography steps to build up transistors layer by layer. First, an n-well is implanted through a mask, then a thin gate oxide and polysilicon layer are deposited, followed by n-type and p-type diffusion masks to form the transistor sources and drains. Contact cuts are etched and an aluminum metal layer is deposited to connect the transistors, forming inverters, NAND gates, and more complex logic functions.

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    Fabrication process is described here.

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    Fabrication Main

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    The document describes the CMOS fabrication process which involves depositing and etching various materials on a silicon wafer through multiple lithography steps to build up transistors layer by layer. First, an n-well is implanted through a mask, then a thin gate oxide and polysilicon layer are deposited, followed by n-type and p-type diffusion masks to form the transistor sources and drains. Contact cuts are etched and an aluminum metal layer is deposited to connect the transistors, forming inverters, NAND gates, and more complex logic functions.

    Copyright:

    © All Rights Reserved
    Download as PPT, PDF, TXT or read online from Scribd
    Download as ppt, pdf, or txt
    20 views39 pages

    Ee466: Cmos Vlsi: Lecture 04: Fabrication

    Uploaded by

    arsenal
    The document describes the CMOS fabrication process which involves depositing and etching various materials on a silicon wafer through multiple lithography steps to build up transistors layer by layer. First, an n-well is implanted through a mask, then a thin gate oxide and polysilicon layer are deposited, followed by n-type and p-type diffusion masks to form the transistor sources and drains. Contact cuts are etched and an aluminum metal layer is deposited to connect the transistors, forming inverters, NAND gates, and more complex logic functions.

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    © All Rights Reserved
    Download as PPT, PDF, TXT or read online from Scribd
    Download as ppt, pdf, or txt
    of 39

    EE466: CMOS VLSI

    Lecture 04: Fabrication

    CMOS Fabrication
    CMOS transistors are fabricated on silicon wafer
    Lithography process similar to printing press
    On each step, different materials are deposited or
    etched
    Easiest to understand by viewing both top and
    cross-section of wafer in a simplified manufacturing
    process

    CMOS VLSI Design

    0: Introduction
    Slide 2

    Inverter Cross-section
    Typically use p-type substrate for nMOS transistors
    Requires n-well for body of pMOS transistors
    A
    GND

    VDD

    SiO2
    n+ diffusion

    n+

    n+

    p substrate
    nMOS transistor

    p+

    p+
    n well

    p+ diffusion
    polysilicon
    metal1

    pMOS transistor

    CMOS VLSI Design

    0: Introduction
    Slide 3

    Well and Substrate Taps


    Substrate must be tied to GND and n-well to VDD
    Metal to lightly-doped semiconductor forms poor
    connection called Shottky Diode
    Use heavily doped well and substrate contacts / taps
    A
    GND

    VDD

    p+

    n+

    n+

    p+

    p+

    n+

    n well

    p substrate
    substrate tap

    well tap

    CMOS VLSI Design

    0: Introduction
    Slide 4

    Inverter Mask Set


    Transistors and wires are defined by masks
    Cross-section taken along dashed line

    GND

    VDD
    nMOS transistor

    pMOS transistor
    well tap

    substrate tap

    CMOS VLSI Design

    0: Introduction
    Slide 5

    Detailed Mask Views


    Six masks
    n-well
    Polysilicon
    n+ diffusion
    p+ diffusion
    Contact
    Metal

    n well

    Polysilicon

    n+ Diffusion

    p+ Diffusion

    Contact

    Metal

    CMOS VLSI Design

    0: Introduction
    Slide 6

    Fabrication Steps
    Start with blank wafer
    Build inverter from the bottom up
    First step will be to form the n-well
    Cover wafer with protective layer of SiO2 (oxide)
    Remove layer where n-well should be built
    Implant or diffuse n dopants into exposed wafer
    Strip off SiO2

    p substrate

    CMOS VLSI Design

    0: Introduction
    Slide 7

    Oxidation
    Grow SiO2 on top of Si wafer
    900 1200 C with H2O or O2 in oxidation furnace

    SiO2

    p substrate

    CMOS VLSI Design

    0: Introduction
    Slide 8

    Photoresist
    Spin on photoresist
    Photoresist is a light-sensitive organic polymer
    Softens where exposed to light

    Photoresist
    SiO2

    p substrate

    CMOS VLSI Design

    0: Introduction
    Slide 9

    Lithography
    Expose photoresist through n-well mask
    Strip off exposed photoresist

    Photoresist
    SiO2

    p substrate

    CMOS VLSI Design

    0: Introduction
    Slide 10

    Etch
    Etch oxide with hydrofluoric acid (HF)
    Seeps through skin and eats bone; nasty stuff!!!
    Only attacks oxide where resist has been exposed

    Photoresist
    SiO2

    p substrate

    CMOS VLSI Design

    0: Introduction
    Slide 11

    Strip Photoresist
    Strip off remaining photoresist
    Use mixture of acids called piranah etch
    Necessary so resist doesnt melt in next step

    SiO2

    p substrate

    CMOS VLSI Design

    0: Introduction
    Slide 12

    n-well
    n-well is formed with diffusion or ion implantation
    Diffusion
    Place wafer in furnace with arsenic gas
    Heat until As atoms diffuse into exposed Si
    Ion Implanatation
    Blast wafer with beam of As ions
    Ions blocked by SiO2, only enter exposed Si
    SiO2
    n well

    CMOS VLSI Design

    0: Introduction
    Slide 13

    Strip Oxide
    Strip off the remaining oxide using HF
    Back to bare wafer with n-well
    Subsequent steps involve similar series of steps

    n well
    p substrate

    CMOS VLSI Design

    0: Introduction
    Slide 14

    Polysilicon
    Deposit very thin layer of gate oxide
    < 20 (6-7 atomic layers)
    Chemical Vapor Deposition (CVD) of silicon layer
    Place wafer in furnace with Silane gas (SiH4)
    Forms many small crystals called polysilicon
    Heavily doped to be good conductor
    Polysilicon
    Thin gate oxide

    p substrate

    n well

    CMOS VLSI Design

    0: Introduction
    Slide 15

    Polysilicon Patterning
    Use same lithography process to pattern polysilicon

    Polysilicon

    Polysilicon
    Thin gate oxide

    p substrate

    n well

    CMOS VLSI Design

    0: Introduction
    Slide 16

    Self-Aligned Process
    Use oxide and masking to expose where n+ dopants
    should be diffused or implanted
    N-diffusion forms nMOS source, drain, and n-well
    contact

    p substrate

    n well

    CMOS VLSI Design

    0: Introduction
    Slide 17

    N-diffusion
    Pattern oxide and form n+ regions
    Self-aligned process where gate blocks diffusion
    Polysilicon is better than metal for self-aligned gates
    because it doesnt melt during later processing

    n+ Diffusion

    n well
    p substrate

    CMOS VLSI Design

    0: Introduction
    Slide 18

    N-diffusion cont.
    Historically dopants were diffused
    Usually ion implantation today
    But regions are still called diffusion

    n+

    n+
    p substrate

    n+
    n well

    CMOS VLSI Design

    0: Introduction
    Slide 19

    N-diffusion cont.
    Strip off oxide to complete patterning step

    n+

    n+
    p substrate

    n+
    n well

    CMOS VLSI Design

    0: Introduction
    Slide 20

    P-Diffusion
    Similar set of steps form p+ diffusion regions for
    pMOS source and drain and substrate contact

    p+ Diffusion

    p+

    n+

    n+
    p substrate

    p+

    p+

    n+

    n well

    CMOS VLSI Design

    0: Introduction
    Slide 21

    Contacts
    Now we need to wire together the devices
    Cover chip with thick field oxide
    Etch oxide where contact cuts are needed

    Contact

    Thick field oxide


    p+

    n+

    n+

    p+

    p+

    n+

    n well
    p substrate

    CMOS VLSI Design

    0: Introduction
    Slide 22

    Metalization
    Sputter on aluminum over whole wafer
    Pattern to remove excess metal, leaving wires

    Metal

    Metal
    Thick field oxide
    p+

    n+

    n+

    p+

    p+

    n+

    n well
    p substrate

    CMOS VLSI Design

    0: Introduction
    Slide 23

    Transistors as Switches
    We can view MOS transistors as electrically
    controlled switches
    Voltage at gate controls path from source to drain
    d
    nMOS

    pMOS

    g=0

    g=1

    d
    OFF

    ON

    OFF

    ON
    s

    CMOS VLSI Design

    0: Introduction
    Slide 24

    CMOS Inverter
    A

    VDD

    0
    1

    A
    A

    GND
    CMOS VLSI Design

    0: Introduction
    Slide 25

    CMOS Inverter
    A

    VDD

    0
    1

    OFF

    A=1

    Y=0

    ON
    A

    GND
    CMOS VLSI Design

    0: Introduction
    Slide 26

    CMOS Inverter
    A

    VDD
    ON
    A=0

    Y=1

    OFF
    A

    GND
    CMOS VLSI Design

    0: Introduction
    Slide 27

    CMOS NAND Gate


    A

    Y
    A
    B

    CMOS VLSI Design

    0: Introduction
    Slide 28

    CMOS NAND Gate


    A

    ON
    A=0
    B=0

    CMOS VLSI Design

    ON
    Y=1
    OFF
    OFF

    0: Introduction
    Slide 29

    CMOS NAND Gate


    A

    OFF
    A=0
    B=1

    CMOS VLSI Design

    ON
    Y=1
    OFF
    ON

    0: Introduction
    Slide 30

    CMOS NAND Gate


    A

    ON
    A=1
    B=0

    CMOS VLSI Design

    OFF
    Y=1
    ON
    OFF

    0: Introduction
    Slide 31

    CMOS NAND Gate


    A

    OFF
    A=1
    B=1

    CMOS VLSI Design

    OFF
    Y=0
    ON
    ON

    0: Introduction
    Slide 32

    CMOS NOR Gate


    A

    A
    B
    Y

    CMOS VLSI Design

    0: Introduction
    Slide 33

    3-input NAND Gate


    Y pulls low if ALL inputs are 1
    Y pulls high if ANY input is 0

    CMOS VLSI Design

    0: Introduction
    Slide 34

    3-input NAND Gate


    Y pulls low if ALL inputs are 1
    Y pulls high if ANY input is 0

    A
    B
    C
    CMOS VLSI Design

    0: Introduction
    Slide 35

    Layout
    Chips are specified with set of masks
    Minimum dimensions of masks determine transistor
    size (and hence speed, cost, and power)
    Feature size f = distance between source and drain
    Set by minimum width of polysilicon
    Feature size improves 30% every 3 years or so
    Normalize for feature size when describing design
    rules
    Express rules in terms of = f/2
    E.g. = 0.3 m in 0.6 m process
    CMOS VLSI Design

    0: Introduction
    Slide 36

    Simplified Design Rules


    Conservative rules to get you started

    CMOS VLSI Design

    0: Introduction
    Slide 37

    Inverter Layout
    Transistor dimensions specified as Width / Length
    Minimum size is 4 / 2sometimes called 1 unit
    In f = 0.6 m process, this is 1.2 m wide, 0.6 m
    long

    CMOS VLSI Design

    0: Introduction
    Slide 38

    Summary

    MOS Transistors are stack of gate, oxide, silicon


    Can be viewed as electrically controlled switches
    Build logic gates out of switches
    Draw masks to specify layout of transistors

    Now you know everything necessary to start


    designing schematics and layout for a simple chip!

    CMOS VLSI Design

    0: Introduction
    Slide 39

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