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    VLSI Design: Dept. of CSE Bangladesh University

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    The document discusses different types of NMOS logic gates. It describes NMOS inverters that use a resistor load, an enhancement transistor load, or a depletion transistor load. The depletion transistor load provides advantages like sharp voltage transfer characteristics, better noise margin, single power supply operation, and smaller layout area. The document also discusses implementing NOR, NAND, OR, and AND gates using NMOS transistors in series and parallel configurations. It introduces the concept of pseudo-NMOS logic and compound gates.

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    VLSI Design: Dept. of CSE Bangladesh University

    Uploaded by

    Rasd sda
    21 views15 pages
    The document discusses different types of NMOS logic gates. It describes NMOS inverters that use a resistor load, an enhancement transistor load, or a depletion transistor load. The depletion transistor load provides advantages like sharp voltage transfer characteristics, better noise margin, single power supply operation, and smaller layout area. The document also discusses implementing NOR, NAND, OR, and AND gates using NMOS transistors in series and parallel configurations. It introduces the concept of pseudo-NMOS logic and compound gates.

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    VLSI_Lec_3

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    The document discusses different types of NMOS logic gates. It describes NMOS inverters that use a resistor load, an enhancement transistor load, or a depletion transistor load. The depletion transistor load provides advantages like sharp voltage transfer characteristics, better noise margin, single power supply operation, and smaller layout area. The document also discusses implementing NOR, NAND, OR, and AND gates using NMOS transistors in series and parallel configurations. It introduces the concept of pseudo-NMOS logic and compound gates.

    Copyright:

    © All Rights Reserved
    Download as PPTX, PDF, TXT or read online from Scribd
    Download as pptx, pdf, or txt
    21 views15 pages

    VLSI Design: Dept. of CSE Bangladesh University

    Uploaded by

    Rasd sda
    The document discusses different types of NMOS logic gates. It describes NMOS inverters that use a resistor load, an enhancement transistor load, or a depletion transistor load. The depletion transistor load provides advantages like sharp voltage transfer characteristics, better noise margin, single power supply operation, and smaller layout area. The document also discusses implementing NOR, NAND, OR, and AND gates using NMOS transistors in series and parallel configurations. It introduces the concept of pseudo-NMOS logic and compound gates.

    Copyright:

    © All Rights Reserved
    Download as PPTX, PDF, TXT or read online from Scribd
    Download as pptx, pdf, or txt
    of 15

    VLSI Design

    CSE-316

    Dept. of CSE
    Bangladesh University
    NMOS Logic

     NMOS inverter with a resistor load.


     NMOS Inverter with an NMOS Enhancement Transistor Load
     NMOS Inverter with an NMOS Depletion Transistor Load
    NMOS Logic

    NMOS inverter with a resistor load

    Resistive Load
    NMOS Logic

    NMOS inverter with a resistor load


     

    R
    The silicon area required to implement this resistor is far larger
    than that for the transistor ( typically by a factor of 300). Thus it
    is not practical to use a resistor as a load and so an MOS device is
    used instead.
    NMOS Logic

    NMOS Inverter with an NMOS Enhancement Transistor Load


     Use of the same transistor type for both the load and
    the digital switch.
     M1 acts as the switch and is also referred to as the
    driver.
     M2 is the load and its gate is connected to Vdd .
     Drawback: The main drawback of an NMOS
    enhancement load, apart from the loss of voltage for
    high outputs, is the speed of the rising edge of the
    gate.
    NMOS Logic

    NMOS Inverter with an NMOS Depletion Transistor Load


     gate and source terminal of load are connected.
     So, VGS = 0.
     Thus, the threshold voltage of the load is
    negative.
     Hence, V_{GS,load}> V_{T,load} is satisfied
     Therefore, load device always has a conduction
    channel regardless of input and output voltage
    level.
    NMOS Logic

    Advantages of NMOS Inverter with an NMOS Depletion Transistor Load

     sharp VTC transition


     better noise margin
     single power supply
     smaller overall layout area.
    NMOS Logic

    NOR Gate
    NMOS Logic

    NAND Gate
    Pseudo-NMOS

    The inverter that uses a p-device pull-up or load that has its gate permanently ground. An n-device pull-down or
    driver is driven with the input signal. This roughly equivalent to use of a depletion load is NMOS technology and
    is thus called 'Pseudo-NMOS'.The advantage of pseudo-NMOS logic are its high speed.
    Series and parallel transistors

    AND & NOR


    Series and parallel transistors

    OR & NAND
    Compound Gate
    Compound Gate
    Compound Gate

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