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    TN 423: Vlsi Circuits: Lecture 4b

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    Bernard Mkumbwa Jr.
    The document discusses the fabrication process of CMOS integrated circuits. It begins by describing the structure and operation of nMOS transistors. It then explains that CMOS uses complementary pairs of nMOS and pMOS transistors for logic functions. The fabrication process involves 19 steps, starting with a p-substrate and including oxidation, photolithography, doping, deposition of polysilicon for gates, and metallization. Wells are used to integrate both nMOS and pMOS transistors on the same chip. The transistors act as electrically controlled switches, with the gate voltage turning the device on or off.

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    TN 423: Vlsi Circuits: Lecture 4b

    Uploaded by

    Bernard Mkumbwa Jr.
    31 views43 pages
    The document discusses the fabrication process of CMOS integrated circuits. It begins by describing the structure and operation of nMOS transistors. It then explains that CMOS uses complementary pairs of nMOS and pMOS transistors for logic functions. The fabrication process involves 19 steps, starting with a p-substrate and including oxidation, photolithography, doping, deposition of polysilicon for gates, and metallization. Wells are used to integrate both nMOS and pMOS transistors on the same chip. The transistors act as electrically controlled switches, with the gate voltage turning the device on or off.

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    vlsi

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    Lecture 4b

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    The document discusses the fabrication process of CMOS integrated circuits. It begins by describing the structure and operation of nMOS transistors. It then explains that CMOS uses complementary pairs of nMOS and pMOS transistors for logic functions. The fabrication process involves 19 steps, starting with a p-substrate and including oxidation, photolithography, doping, deposition of polysilicon for gates, and metallization. Wells are used to integrate both nMOS and pMOS transistors on the same chip. The transistors act as electrically controlled switches, with the gate voltage turning the device on or off.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    31 views43 pages

    TN 423: Vlsi Circuits: Lecture 4b

    Uploaded by

    Bernard Mkumbwa Jr.
    The document discusses the fabrication process of CMOS integrated circuits. It begins by describing the structure and operation of nMOS transistors. It then explains that CMOS uses complementary pairs of nMOS and pMOS transistors for logic functions. The fabrication process involves 19 steps, starting with a p-substrate and including oxidation, photolithography, doping, deposition of polysilicon for gates, and metallization. Wells are used to integrate both nMOS and pMOS transistors on the same chip. The transistors act as electrically controlled switches, with the gate voltage turning the device on or off.

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    © All Rights Reserved
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    of 43

    TN 423: VLSI CIRCUITS

    Lecture 4b

    FABRICATION OF CMOS ICs

    1
    Outline
    1. NMOS Transistor Fabrication
    2. CMOS Transistor fabrication
    3. CMOS Gate Design

    Ngeze, LV VLSI Circuits 2


    NMOS Transistor Fabrication…
    Ω NMOS Transistor structure

    Source Gate Drain


    Polysilicon
    SiO2

    n+ n+
    Body
    p bulk Si

    Ngeze, LV VLSI Circuits 3


    NMOS Transistor Fabrication…
    Ω Gate – oxide – body stack looks like a capacitor
    ✓ Gate and body are conductors
    ✓ SiO2 (oxide) is a very good insulator
    Ω Called metal – oxide – semiconductor (MOS)
    capacitor
    Source Gate Drain
    Polysilicon
    SiO2

    n+ n+
    Body
    p bulk Si

    Ngeze, LV VLSI Circuits 4


    nMOS Operation
    Ω Body is usually tied to ground (0 V)
    Ω When the gate is at a low voltage:
    ✓ P-type body is at low voltage
    ✓ Source-body diode is OFF
    ✓ drain-body diode is OFF
    ✓ No current flows, transistor is OFF
    Source Gate Drain
    Polysilicon
    SiO2

    0
    n+ n+
    S D
    p bulk Si

    Ngeze, LV VLSI Circuits 5


    NMOS Transistor Fabrication…
    Ω When the gate is at a high voltage:
    ✓ Positive charge on gate of MOS capacitor
    ✓ Negative charge attracted to body
    ✓ Inverts a channel under gate to n-type
    ✓ Now current can flow through n-type silicon from
    source through channel to drain
    ✓ transistor is ON
    Source Gate Drain
    Polysilicon
    SiO2

    1
    n+ n+
    S D
    p bulk Si

    6
    Ngeze, LV VLSI Circuits
    CMOS Fabrication Process…
    Ω CMOS is also sometimes referred to as.
    complementary-symmetry metal–oxide–
    semiconductor
    Ω The words "complementary-symmetry"
    refers to the fact that the typical design
    style with CMOS uses complementary
    and symmetrical pairs of p-type and n-
    type metal oxide semiconductor field
    effect transistors(MOSFETs) for logic
    functions
    Ngeze, LV VLSI Circuits 7
    CMOS Fabrication Process…
    Ω CMOS technology employs both nMOS
    and pMOS transistors to form the logic
    elements
    Ω The logic elements only draw significant
    current during the transitions from one
    state to another but draw very little current
    between transistors allowing power
    consumption to be minimized

    Ngeze, LV VLSI Circuits 8


    CMOS Fabrication Process
    Ω CMOS can be fabricated using different
    processes:
    1. n-well process
    2. p-well process
    3. twin-tub process
    Ω CMOS can be obtained by integrating both the
    NMOS and PMOS transistors on the same chip
    substrate
    Ω special regions called as wells or tubs are
    required in which semiconductor type and
    substrate type are opposite to each other
    Ngeze, LV VLSI Circuits 9
    CMOS Fabrication Process…
    Ω The fabrication of CMOS is described
    using the P-substrate, in which:
    ✓ the NMOS transistor is fabricated on a P-
    type substrate
    and
    ✓ the PMOS transistor is fabricated in N-well.
    Ω The fabrication process involves the
    following steps:

    Ngeze, LV VLSI Circuits 10


    CMOS Fabrication Process…
    Step1: Substrate
    ΩPrimarily, start the process with a P-
    substrate.

    Ngeze, LV VLSI Circuits 11


    CMOS Fabrication Process…
    Step2: Oxidation
    ΩThe oxidation process is done by using
    high-purity oxygen and hydrogen, which are
    exposed in an oxidation furnace
    approximately at 10000C.

    Ngeze, LV VLSI Circuits 12


    CMOS Fabrication Process…
    Step3: Photoresist
    ΩA light-sensitive polymer that softens
    whenever exposed to light is called as
    Photoresist layer. It is formed.

    Ngeze, LV VLSI Circuits 13


    CMOS Fabrication Process…
    Step4: Masking
    ΩThe photoresist is exposed to UV rays
    through the N-well mask

    Ngeze, LV VLSI Circuits 14


    CMOS Fabrication Process…
    Step5: Photoresist removal
    ΩA part of the photoresist layer is removed
    by treating the wafer with the basic or acidic
    solution.

    Ngeze, LV VLSI Circuits 15


    CMOS Fabrication Process…
    Step6: Removal of SiO2 using acid
    etching
    ΩThe SiO2 oxidation layer is removed
    through the open area made by the removal
    of photoresist using hydrofluoric acid.

    Ngeze, LV VLSI Circuits 16


    CMOS Fabrication Process…
    Step7: Removal of photoresist
    ΩThe entire photoresist layer is stripped off,
    as shown in the below figure.

    Ngeze, LV VLSI Circuits 17


    CMOS Fabrication Process…
    Step8: Formation of the N-well
    ΩBy using ion implantation or diffusion
    process N-well is formed.

    Ngeze, LV VLSI Circuits 18


    CMOS Fabrication Process…
    Step9: Removal of SiO2
    ΩUsing the hydrofluoric acid, the remaining
    SiO2 is removed.

    Ngeze, LV VLSI Circuits 19


    CMOS Fabrication Process…
    Step10: Deposition of poly silicon
    ΩChemical Vapor Deposition (CVD) process
    is used to deposit a very thin layer of gate
    oxide.

    Ngeze, LV VLSI Circuits 20


    CMOS Fabrication Process…
    Step11: Removing the layer barring a
    small area for the Gates
    ΩExcept the two small regions required for
    forming the Gates of NMOS and PMOS, the
    remaining layer is stripped off

    Ngeze, LV VLSI Circuits 21


    CMOS Fabrication Process…
    Step12: Oxidation process
    ΩNext, an oxidation layer is formed on this
    layer with two small regions for the formation
    of the gate terminals of NMOS and PMOS.

    Ngeze, LV VLSI Circuits 22


    CMOS Fabrication Process…
    Step13: Masking and N-diffusion
    ΩBy using the masking process small gaps are made for
    the purpose of N-diffusion.

    ΩThe n-type (n+) dopants are diffused or ion implanted,


    and the three n+ are formed for the formation of the
    terminals of NMOS.

    Ngeze, LV VLSI Circuits 23


    CMOS Fabrication Process…
    Step14: Oxide stripping
    ΩThe remaining oxidation layer is stripped
    off.

    Ngeze, LV VLSI Circuits 24


    CMOS Fabrication Process…
    Step15: P-diffusion
    ΩSimilar to the above N-diffusion process,
    the P-diffusion regions are diffused to form
    the terminals of the PMOS.

    Ngeze, LV VLSI Circuits 25


    CMOS Fabrication Process…
    Step16: Thick field oxide
    ΩA thick-field oxide is formed in all regions
    except the terminals of the PMOS and
    NMOS.

    Ngeze, LV VLSI Circuits 26


    CMOS Fabrication Process…
    Step17: Metallization
    ΩAluminum is sputtered on the whole wafer.

    Ngeze, LV VLSI Circuits 27


    CMOS Fabrication Process…
    Step18: Removal of excess metal
    ΩThe excess metal is removed from the
    wafer layer.

    Ngeze, LV VLSI Circuits 28


    CMOS Fabrication Process…
    Step19: Terminals
    ΩThe terminals of the PMOS and NMOS are
    made from respective gaps.

    Ngeze, LV VLSI Circuits 29


    CMOS Fabrication Process…
    Step20:
    ΩAssigning the names of the terminals of
    the NMOS and PMOS

    ΩFour terminals: gate, source, drain, body


    Ngeze, LV VLSI Circuits 30
    Transistors as Switches
    Ω We can view MOS transistors as
    electrically controlled switches
    Ω Voltage at gate controls path from source
    to drain g=0 g=1

    d d d
    nMOS g OFF
    ON
    s s s

    d d d

    pMOS g OFF
    ON
    s s s

    Ngeze, LV 31
    VLSI Circuits
    Power Supply Voltage
    Ω GND = 0 V
    Ω VDD = 5V (in the 1980s)
    Ω VDD has decreased in modern processes
    ✓ High VDD would damage modern tiny
    transistors
    ✓ Lower VDD saves power
    Ω VDD = 3.3, 2.5, 1.8, 1.5, 1.2, 1.0, …

    Ngeze, LV 32
    VLSI Circuits
    CMOS Gate Design
    Ω In general, a static CMOS gate has
    ✓ a pMOS pull-up network (PUP) to connect the output
    to 1(VDD), and
    ✓ an nMOS pull-down network (PUN) to connect the
    output to 0 (GND) and as shown in Figure
    pMOS
    pull-up why are they called pull-up and
    network pull-down??
    inputs
    output

    nMOS
    pull-down
    network

    Ω The networks are arranged such that one is ON


    and the other OFF for any 33input pattern.
    TN 423 VLSI
    UDOM
    CMOS Gate Design…
    Ω The inverter and NAND gates are
    examples of static CMOS logic gates,
    Ω Also called complementary CMOS gates.

    TN 423 VLSI UDOM 34


    CMOS Inverter

    A Y VDD
    00 11
    11 00 OFF
    ON
    0
    1
    A Y
    ON
    OFF

    A Y
    GND
    Ngeze, LV 35
    VLSI Circuits
    CMOS NAND Gate

    A B Y
    0 0 11 ON
    OFF
    OFF
    ON OFF
    ON
    0 1 11
    1
    Y
    1 0 11 0 ON
    A OFF
    1 1 00 0
    1
    1
    0 OFF
    ON
    B ON
    OFF

    Ngeze, LV 36
    VLSI Circuits
    CMOS NOR Gate

    A B Y
    0 0 1 A
    0 1 0
    1 0 0 B
    1 1 0 Y

    Ngeze, LV 37
    VLSI Circuits
    CMOS Gate Design
    Ω In general, when we join a pull-up network
    to a pull-down network to form a logic
    gate, they both will attempt to exert a logic
    level at the output.
    Ω The two possible levels are:
    ✓ The 1 level
    ✓ The 0 level
    Ω The networks are arranged such that one
    is ON and the other OFF for any input
    pattern.
    TN 423 VLSI 38
    UDOM
    CMOS Gate Design…
    Ω When both PUN and PDN are OFF: high
    impedance or floating Z output state, the
    results
    Ω When both PUP network and PUN
    network are simultaneously turned ON
    ✓ The crowbarred (or contention) X level.

    TN 423 VLSI UDOM 39


    CMOS Gate Design…
    Ω Two or more transistors in series are ON
    only if all of the series transistors are ON.
    Ω Two or more transistors in parallel are ON
    if any of the parallel transistors are ON.
    Ω This is illustrated in the figure for nMOS
    and pMOS transistor pairs.
    Ω By using combinations of these
    constructions, CMOS combinational gates
    can be constructed.
    TN 423 VLSI UDOM 40
    CMOS Gate Design…

    TN 423 VLSI UDOM 41


    CMOS Gate Design…

    TN 423 VLSI UDOM 42


    CMOS Gate Design…
    Ω Read CMOS VLSI Design
    A Circuits and Systems Perspective by
    Neil H E Weste and David Money Harris
    From Page 9-25

    Ngeze, LV VLSI Circuits 43

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