IC Manufacturing

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 nMOS Transistor
 Four terminals: gate, source, drain, body
 Gate – oxide – body stack looks like a capacitor
– Gate and body are conductors
– SiO2 (oxide) is a very good insulator
– Called metal – oxide – semiconductor (MOS)
capacitor Source Gate Drain
Polysilicon
– Even though gate is SiO2
no longer made of metal
n+ n+
Body
p bulk Si

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 nMOS Operation
 Body is usually tied to ground (0 V)
 When the gate is at a low voltage:
– P-type body is at low voltage
– Source-body and drain-body diodes are OFF
– No current flows, transistor is OFF
Source Gate Drain
Polysilicon
SiO2

0
n+ n+
S D
p bulk Si

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 nMOS Operation Cont.
 When the gate is at a high voltage:
– Positive charge on gate of MOS capacitor
– Negative charge attracted to body
– Inverts a channel under gate to n-type
– Now current can flow through n-type silicon from
source through channel to drain, transistor is ON
Source Gate Drain
Polysilicon
SiO2

1
n+ n+
S D
p bulk Si

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 pMOS Transistor
 Similar, but doping and voltages reversed
– Body tied to high voltage (VDD)
– Gate low: transistor ON
– Gate high: transistor OFF
– Bubble indicates inverted behavior
Source Gate Drain
Polysilicon
SiO2

p+ p+

n bulk Si

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 CMOS Inverter

A Y VDD
0 1
1 0 OFF
ON
0
1
A Y
ON
OFF

A Y
GND
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 CMOS Fabrication
 CMOS transistors are fabricated on silicon wafer
 Lithography process similar to printing press is used
 On each step, different materials are deposited or
etched
 Easiest to understand by viewing both top and
cross-section of wafer in a simplified manufacturing
process

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 Inverter Cross-section
 Typically use p-type substrate for nMOS transistors
 Requires n-well for body of pMOS transistors
A
GND VDD
Y SiO2

n+ diffusion

p+ diffusion
n+ n+ p+ p+
polysilicon
n well
p substrate
metal1

nMOS transistor pMOS transistor

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Well and Substrate Taps
 Substrate must be tied to GND and n-well to VDD
 Metal to lightly-doped semiconductor forms poor
connection
 Hence usse heavily doped well and substrate
contacts / taps A
GND VDD
Y

p+ n+ n+ p+ p+ n+

n well
p substrate

well
substrate tap
tap

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 Inverter Mask Set
 Transistors and wires are defined by masks
 Cross-section taken along dashed line

GND VDD

nMOS transistor pMOS transistor

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 Detailed Mask Views
 Six masks n well

– n-well
– Polysilicon
Polysilicon

– n+ diffusion
– p+ diffusion n+ Diffusion

– Contact p+ Diffusion

– Metal Contact

Metal

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 Fabrication
 Chips are built in huge factories called fabs (fabrication plants)
 Contain clean rooms as large as football fields

Courtesy of International
Business Machines Corporation.

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 Fabrication Steps
 Start with blank wafer
 Build inverter from the bottom up
 First step will be to form the n-well
– Cover wafer with protective layer of SiO2 (oxide)
– Remove layer where n-well should be built
– Implant or diffuse n dopants into exposed wafer
– Strip off SiO2

p substrate

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 Oxidation
 Grow SiO2 on top of Si wafer
– 900 – 1200 C with H2O or O2 in oxidation furnace

SiO2

p substrate

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 Photoresist
 Spin on photoresist
– Photoresist is a light-sensitive organic polymer
– Softens where exposed to light

Photoresist
SiO2

p substrate

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 Lithography
 Expose photoresist with UV rays through n-well
mask

Photoresist
SiO2

p substrate

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 Lithography
 Expose photoresist through n-well mask
 Wash off exposed photoresist

Photoresist
SiO2

p substrate

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 Etch
 Etch oxide with hydrofluoric acid (HF)
 Only attacks oxide where resist has been exposed

Photoresist
SiO2

p substrate

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 Strip Photoresist
 Strip off remaining photoresist
– Use mixture of acids called piranah etch
 Necessary so resist doesn’t melt in next step

SiO2

p substrate

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 n-well
 n-well is formed with diffusion or ion implantation
 Diffusion
– Place wafer in furnace with arsenic gas
– Heat until As atoms diffuse into exposed Si
 Ion Implanatation
– Blast wafer with beam of As ions
– Ions blocked by SiO2, only enter exposed Si
SiO2

n well

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 Strip Oxide
 Strip off the remaining oxide using HF
 Back to bare wafer with n-well
 Subsequent steps involve similar series of steps

n well
p substrate

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 Polysilicon
 Deposit very thin layer of gate oxide
– < 20 Å (6-7 atomic layers)
 Chemical Vapor Deposition (CVD) of silicon layer
– Place wafer in furnace with Silane gas (SiH4)
– Forms many small crystals called polysilicon
– Heavily doped to be good conductor for gate
terminal
Polysilicon
Thin gate oxide

n well
p substrate

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 Polysilicon Patterning
 Use same lithography process to pattern polysilicon

Polysilicon

Polysilicon
Thin gate oxide

n well
p substrate

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 N-diffusion
 Use oxide and masking to expose where n+ dopants
should be diffused or implanted
 Use same lithography process
 N-diffusion forms nMOS source, drain, and n-well
contact

n well
p substrate

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 N-diffusion
 Use oxide and masking to expose where n+ dopants
should be diffused or implanted
 Use same lithography process
 N-diffusion forms nMOS source, drain, and n-well
contact

n+ Diffusion

n well
p substrate

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 N-diffusion cont.
 Historically dopants were diffused
 Usually ion implantation today
 But regions are still called diffusion

n+ n+ n+

n well
p substrate

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 N-diffusion cont.
 Strip off oxide to complete patterning step

n+ n+ n+

n well
p substrate

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 P-Diffusion
 Similar set of steps form p+ diffusion regions for
pMOS source and drain and substrate contact

p+ Diffusion

p+ n+ n+ p+ p+ n+

n well
p substrate

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 Contacts
 Now we need to wire together the devices
 Cover chip with thick field oxide
 Etch oxide where contact cuts are needed

Contact

Thick field oxide

n well
p substrate

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 Metalization
 Sputter on aluminum over whole wafer
 Pattern to remove excess metal, leaving wires

Metal

Metal
Thick field oxide
p+ n+ n+ p+ p+ n+

n well
p substrate

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 Top-Down View
 When drawing tens or hundreds of transistors, the
three-dimensional view quickly becomes cumbersome
to create and is really unnecessary.
 Instead, we can use a top-down two-dimensional
view, wherein we first assign a unique pattern to
represent each layer.

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Top-Down View

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Top-Down View

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Top-Down View

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Top-Down View

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Top-Down View

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Top-Down View

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Top-Down View

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IC Manufacturing Steps

Tape-out

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IC Manufacturing Steps
• During the Design Phase, a designer creates the structural design and
then generates a layout for that design.
• The designer provides the layout to the IC manufacturer or fabrication
plant (fab).
• Manufacturing consists of several steps.
• The first step is to create a set of mask corresponding to the layout.
• The second step is to use each of these masks to create the various
layers on the silicon surface, consisting of several sub-steps per mask.
• This layering process creates numerous ICs at once on a silicon wafer
(a thin polished circle sliced from a cylinder of silicon called “ingot”).
• The third step is to test the ICs on the wafer using device called
‘testers’ that use probes that contact the pads or input and output ports,
apply streams of input sequences and look for appropriate output
sequences.
• Finally the last step is to cut-out each IC and mount the good ones in
an IC package.
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 Photolithography
• Photolithography, also called optical lithography or UV
lithography, is a process used in microfabrication to
pattern parts on a thin film or the bulk of a substrate.
• It uses light to transfer a geometric pattern from a
photomask to a photosensitive chemical (photoresist)
on the substrate.

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Ten Basic Steps of Photolithography
1. Surface Preparation and
Barrier Formation (Oxidation)
2. Photoresist Application
3. Soft Bake
4. Align & Expose
5. Develop
6. Hard Bake
7. Develop Inspection
8. Etch
9. Resist Strip
10. Final Inspection

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1.Surface Preparation and Oxidation
• Clean and dry wafer
surface with Hexa- HMDS
methyldisilazane (HMDS)
• Grow SiO2 on top of Si
wafer
• 900 – 1200 C with H2O or
O2 in oxidation furnace

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 2. Photoresist Application
• Wafer held onto
vacuum chuck
photoresist
• Dispense photoresist dispenser
onto slow spinning
wafer

vacuum
chuck
to
vacuum spindle
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pump
 2. Photoresist Application
• There are two types of photoresist: positive and negative.
• For positive resists, the resist is exposed with UV light wherever
the underlying material is to be removed.
• In these resists, exposure to the UV light changes the chemical
structure of the resist so that it becomes more soluble in the
developer.
• The exposed resist is then washed away by the developer
solution, leaving windows of the bare underlying material. In other
words, "whatever shows, goes."
• The mask, therefore, contains an exact copy of the pattern which
is to remain on the wafer.

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 2. Photoresist Application
• Negative resists behave in just the opposite manner.
• Exposure to the UV light causes the negative resist to become
polymerized, and more difficult to dissolve.
• Therefore, the negative resist remains on the surface
wherever it is exposed, and the developer solution removes
only the unexposed portions.
• Masks used for negative photoresists, therefore, contain the
inverse (or photographic "negative") of the pattern to be
transferred.

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 3. Soft Bake
• Partial evaporation of photo-
resist solvents
• Improves adhesion and
uniformity
• Optimizes light absorbance
characteristics of photoresist

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 4. Alignment and Exposure
UV LightSource
• Transfers the mask image
to the resist- coated wafer
• Activates photo- sensitive Mask
components of photoresist

Resist

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 5. Develop
• Soluble areas of photoresist
are dissolved by developer developer
chemical dispenser

• Visible patterns appear on

vacuum
to
chuck
vacuum
pump spindle

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 6. Hard Bake
 Evaporate remaining
photoresist
 Improve adhesion
 Higher temperature than
soft bake

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 7. Develop Inspect

• Look for
– particles
– defects
– critical dimensions
– linewidth resolution
– overlay accuracy

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 8. Etch
• Etch Si-oxide with CF4
hydrofluoric acid (HF) or
CF4
• Only attacks oxide where
resist has been exposed
to UV (positive
photoresist)

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9. Photoresist Removal (strip)
• No need for photoresist
following etch process O2
• Two common methods:
– wet acid strip
– dry plasma containing
oxygen
• Followed by wet clean to
remove remaining resist
and strip byproducts

Plasma

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 10. Final Inspection
• Photoresist has been
completely removed
• Pattern on wafer
matches mask pattern
(positive resist)
• Quality issues:
– defects
– particles
– step height
– critical dimensions

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