International Journal of Engineering Trends and Technology Volume 71 Issue 12, 248-263, December 2023

ISSN: 2231–5381 / https://doi.org/10.14445/22315381/IJETT-V71I12P224 © 2023 Seventh Sense Research Group®

Original Article

Design of an Active-Loaded Differential Voltage-

Controlled Oscillator (VCO) Using Double-Gate
MOSFET
Suvashan Pillay1, Viranjay M. Srivastava1,2*
1
Department of Electronic Engineering, Howard College, University of Kwa-Zulu Natal, Durba, South Africa.
2
Department of Electronic Engineering, Birmingham City University, Birmingham, United Kingdom.

*Corresponding Author: [email protected]

Received: 12 August 2023 Revised: 15 November 2023 Accepted: 25 November 2023 Published: 06 December 2023

Abstract - A differential cross-coupled Voltage Controlled Oscillator (VCO) has been designed using the Double-Gate (DG)
MOSFET for VHF applications. The DG MOSFET exhibits superior noise immunity with its high noise figure and is suitable
for low-power, high-frequency applications. The proposed VCO has been designed using a differential topology with
improved power consumption, design flexibility, and noise reduction. This also improves the high-frequency performance of
existing differential amplifiers. Thereafter, the proposed VCO was compared with fabrication and design methods,
particularly Silicon-based CMOS and Single-Gate (SG) MOSFET VCOs, as possible alternatives. Various printed circuit
board (PCB) design practices were followed to minimise the noise and improve the overall efficiency of the circuitry. Key
parameters for the analysis of this VCO are the output power, phase noise, and figure of merit, which have been realised as
-2.91 dBm at peak and -69.79 dBc/Hz at 1 MHz, respectively. The power consumption of the designed VCO is 36 mW.

Keywords - MOSFET, Double-Gate MOSFET, Differential amplifier, Microelectronics, Nanotechnology, VLSI, VCO.

1. Introduction An oscillator uses a resonator (an LC or RC tank

A Voltage Controlled Oscillator (VCO) is a frequency circuit), which overcomes its losses electrically by
oscillator whose output frequency depends on the voltage at achieving stability depending on the characteristics and
a particular node in circuitry. This node is usually one that nonlinearities of the entire oscillator. For a single-transistor
is connected to a variable capacitor known as a varactor VCO, a start-up transconductance gm(START) must be
diode or variable inductor. As the reverse bias voltage across achieved, which will change to a new transconductance
the varactor diode changes, its capacitance varies. The gm(CURRENT). There is a given transconductance gm for a
capacitance forms a part of the Resistor-Capacitor (RC) or given resonant frequency.
Inductor-Capacitor (LC) tank circuit, effectively providing
gm(RESONATE). For sustained, stable oscillation to occur:
a variable frequency output [1]. Currently, there are three
gm(CURRENT) + gm(RESONATE) = 1 (1)
common forms of VCOs, which include the Hartley
oscillator (which uses inductive coupling), the Colpitts The stability of an oscillator can be affected by many
oscillator (which uses capacitive coupling) and the less- factors, which can be separated into three aspects:
popular Clapp oscillator (similar to the Colpitts oscillator • Start-up conditions not being met [3] – The LC-tank
but changes the capacitive coupling of the base or gate of
circuit must be provided with sufficient voltage to
the transistor to prevent cross-coupling from the emitter or
ensure sustained oscillations. The capacitor of the LC
source) [1, 2].
circuit typically requires this. Using a standard
capacitor with a fixed capacitance can ensure this, given
that it will charge accordingly and be able to maintain
oscillation. If the oscillator is not biased correctly and
cannot meet the initial start-up condition of the
resonator circuitry, the output will not be present;
• Frequency effects – the output frequency of the VCO
should not be affected by a shift in supply voltage,
which is known as frequency pushing [4]. This can be
avoided by utilising measures to control the supply
voltage, preventing any fluctuation (an increase or
Fig. 1 VCO architectures showing differences in output coupling decrease), and ensuring the control voltage of the

This is an open access article under the CC BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)

 Suvashan Pillay & Viranjay M. Srivastava / IJETT, 71(12), 248-263, 2023

resonator circuit is broad. Frequency pushing can cause built using a general-purpose Operational Amplifier (Op-
substantial degradation in phase noise, given that the Amp) or transistors (BJTs or MOSFETs). A cascode
circuit will also be easily affected by power-supply amplifier was used by Trotta et al. [12], and a Darlington-
noise [5]; based topology for the output stage was used by Han et al.
• Varactor-related effects – This component is essential [13]. From the analysis of the aforementioned literature, a
to the operation of the VCO. There must be careful list of parameters ought to be evaluated to characterise,
attention paid to the tuning gain (which should be compare and specify suitable applications for the proposed
reduced to reduce the phase noise of the oscillator) and VCO. These parameters include output power, phase noise,
tuning voltage (a reverse-biased varactor may become tuning voltage characterisation, and tuning characteristics.
forward-biased, but the tuning voltage should never be The output power can be used to determine the peak-to-peak
zero, which will seize oscillation) [6]. Design methods voltage of the output waveform/carrier Vpk-pk.
to improve the varactor’s behaviour in the resonator
circuit include a back-to-back varactor configuration For the design of the VCO, a differential topology will
[7], maintaining a high voltage (> 50% of the supply be used [14]. This has been reviewed as a possible
voltage) around the varactor output node to ensure a alternative to the Colpitts and Hartley oscillator. Kackar et
reverse-bias voltage can be maintained [8]. al. [16] have highlighted the expansiveness of this oscillator
model, showing the addition of multiple transistor stages
The variations in design from the literature are noted,
which could be added to achieve different functional
where VCOs, shown in Figure 1, may be designed and
specifications. These specifications may include a wider
include optimisations. Son et al. [8] have designed a widely
bandwidth, which uses a 7-stage Differential Voltage
tunable K-band voltage-controlled oscillator, which, by
Controlled Ring Oscillator (DRVCO), or a high-speed
definition, can be used in microwave frequencies, i.e. 18
design which uses a 10-stage DRVCO. The transistor stages
GHz – 27 GHz. The objective of this Silicon-based CMOS
play their respective roles in driving other transistors to
design was to provide three banks of capacitors in
achieve larger output swings for a larger bandwidth or better
conjunction with a varactor diode to increase the tuning
latch times for faster response times.
range of the LC-tank circuit. The capacitor banks equate to
approximately 352.5 fF to 526 fF, as the total equivalent
The proposed VCO of this work uses a two-stage
capacitance is 462.6 fF to 709.1 fF, with the varactor
differential architecture, where two DG MOSFETs, acting
capacitance being 110.1 fF to 183.1 fF. Considering the
as current sources, will be used to drive their successive
work of this paper, it is important to create a large tuning
signal-in DG MOSFETs in the signal chain, forming part of
range to maximise the tuning voltage and prevent saturation
a current mirror constructed using two general-purpose N-
of the resonator.
Channel MOSFETs. This can be seen in Figure 3, given the
differential amplifier designed on previous studies. The DG
An active-loaded configuration was used in the
MOSFET has shown to be a low-power, high-frequency
previous study, which makes it closely related to the push-
transistor, given its lower drain-source VDS to maintain an
pull configuration in Silicon-based CMOS and Field-Effect
adequate drain current. An output buffer would not be used
Transistor (FET) biasing by visual inspection. Designed by
in this design, as stand-alone power and frequency
Zhang [10], A VCO utilising the push-push dual band cross-
characteristics must be observed, which could be
coupled configuration exhibited an excellent phase noise of
manipulated by adding a buffer.
-108.57 dBc/Hz at 10 MHz. However, the design of this
VCO was considered carefully, as the tail current source is
The differential oscillator was investigated as an nMOS
known for readily introducing phase noise. Elevated levels
van-der-Pol differential oscillator by Buccoleri et al. [17],
of phase noise and the minimised tuning range are owed to
which was developed to overcome the Groszkowski effect,
the addition of the tail current source, which was helped by
which is the dependence of the oscillation frequency on the
extra capacitors in the LC resonator and low-pass filters
transistor current. This is undesirable, as this gives rise to
between the varactor and its voltage node, which is injected
jitter. Using the van-der-Pol differential oscillator, the
into the push-push transistor pair.
frequency shift of the oscillation frequency from the
resonant frequency is reduced.
Considering the differential amplifier being used in
VCO design, this has been investigated by Khatoon and
Authors would have to deliberate using a variable
Chandel [11], which exhibited substantial ability,
inductor or variable capacitor to design the tank circuit.
consuming 3.1 mW, at the maximum tuning voltage of 2.3
Mansour et al. [19] have incorporated a high-Q off-chip
V. This method of design also utilised operational amplifiers
inductor into the 130nm CMOS process, yielding a 166%
instead of FETs. This significantly affects the design
tuning range. However, the varactor diode has also been
process. A buffer circuit would be added at the output of a
used in high-frequency applications but provides a lower
VCO to provide a higher output power. The buffer may be
tuning range, as shown by [21].

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This work aims to achieve a sinusoidal output with a 2.1. Design of Resonator Circuit
maximum RMS value (VRMS) of 177 mV and peak-to- Considering a resonator tank circuit for a frequency
peak voltage (Vpk-pk) of 500 mV. This signal is large spectrum of 70 – 100 MHz, Equation 2 can be used to
enough to be used with a high-gain transmit (TX) amplifier determine the resonant frequency for an LC resonator [24]:
for applications in Frequency Modulation (FM) or aircraft 𝑓=
1
(2)
communications [22], which is the intended frequency band 2𝜋√𝐿𝐶

of operation. Since it will be an unmodulated signal, it can

2.2. Current Biasing of DG MOSFETs
also function as a carrier frequency in FM. Given a Vpk-pk
To utilise a large range of capacitance values of the
of 500 mV, the resulting transmit power will be varactor diode, a supply voltage of 9 V should be chosen.
approximately -2 dBm at peak. The load will be 50 Ω, which Given a maximum Vpk-pk of 500 mV, and VRMS of 177 mV,
will be seen by the VCO as a standard BNC output port. It the equivalent maximum transmit power PT is:
is also favourable to maintain a phase noise calculation of - 𝑉𝑅𝑀𝑆
50 dBm for the 70 – 100 MHz frequency range. This will be 𝑃𝑇 (𝑑𝐵𝑚) = 20 log10 ( 𝑍
) (3)
√
potentially achieved by reducing the effect of all noise 1000

sources (reduce thermal noise by keeping resistor values where Z is the impedance (Z = 50 Ω), thus by solving
low, employing noise minimisation techniques in printed PT ≈ -2 dBm. Converting PT to watts,
circuit board (PCB) design, utilise a hyper abrupt varactor 𝑃𝑇 (𝑑𝐵𝑚)
diode for its small tuning range and reducing bias voltage 10 10
[23]. The hyperabrupt diode is readily available and 𝑃𝑇 (𝑤𝑎𝑡𝑡𝑠) =
1000
provides good linearity, i.e. re-verse-bias voltage vs
Solving, PT(watts) ≈ 0.63 mW. Given this transmit
capacitance. power, and considering the VRMS of the output waveform,
the drain current ID can be calculated as:
The second harmonic is to be included by design. This
𝑃𝑇 (𝑤𝑎𝑡𝑡𝑠)
will result in the inclusion of the frequency range of 140 – 𝐼𝐷 =
𝑉𝑅𝑀𝑆
(4)
200 MHz in the analysis of the proposed VCO. A working
PCB design with schematic capture, while considering the 𝐼𝐷 ≈ 4 𝑚𝐴
above-mentioned specifications, i.e. reduction in noise, The drain current of 2 mA must be maintained through
power consumption and signal integrity, is to be included. U1 and U3, and U2 and U4 to equate to 4 mA. To bias the
current mirror for a drain current of 4 mA, R16 is the resistor
The DG MOSFET, as shown in Figure 2 [21], is the at the drain of the current mirror formed by M1 and M2 in
subject of this research as a continuation of the analysis, Figure 3 needs to be recalculated:
where the active-loaded differential amplifier was designed
using the DG MOSFET. The testing of this simulation 𝑃𝑜𝑠𝑖𝑡𝑖𝑣𝑒 𝑠𝑢𝑝𝑝𝑙𝑦−𝑁𝑒𝑔𝑎𝑡𝑖𝑣𝑒 𝑠𝑢𝑝𝑝𝑙𝑦
reveals low power consumption for a similar output power 𝑅16 = (5)
𝑑𝑒𝑠𝑖𝑟𝑒𝑑 𝑑𝑟𝑎𝑖𝑛 𝑐𝑢𝑟𝑟𝑒𝑛𝑡
compared to the cited works. The high-frequency behaviour
where the positive supply in this application is 9 V, and
is further investigated in the testing of the proposed VCO.
the negative supply is 0 V. Thus, R16 is 2.2 kΩ. It is required
The testing and evaluation of the proposed VCO will verify
to choose a specified gate-2 to source voltage VG2-S. For
if the DG MOSFET is a suitable replacement for the SG
design simplicity, VG2-S ≈ 4 V conveniently depicts the ID–
MOSFET and current CMOS designs in high-frequency,
VGS characteristics in the datasheet of the BF998 DG
low-power applications such as the VCO. This manuscript
MOSFET.
has been organised as follows: Section 2 outlines the design
process of the designed VCO, i.e. current and voltage
requirements, filtering, schematic capture and printed
circuit board (PCB) design and routing. Section 3 outlines
the testing of key parameters outlined by the literature study
and compares the designed VCO to the aforementioned
literature. Finally, Section 4 concludes the future work,
which would be recommended for the designed VCO.

2. Design and Implementation of VCO using

the DG MOSFET
Following the design of the active-loaded differential
amplifier, the model shown in Figure 3 dictates the
architecture of the VCO be designed in this literature, given
that the differential topology and its active-loading Fig. 2 Schematic of the Double-Gate MOSFET (S: Source, D: Drain,
principles were utilised in previous study. G1 and G2: gate-1 and gate-2, SiO2: Silicon dioxide).

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Fig. 3 Proposed active-loaded differential amplifier, which will be adapted for the proposed VCO

From Equation 1, the oscillating DG MOSFETs (U3 According to the datasheet [25], to maintain a drain
and U4, as seen in Figure 3) should maintain a similar current of 2 mA, with a VG2-S of 4 V, VG1-S must be -0.4 V.
transconductance gm. This can be achieved by biasing both The dc bias of VG1 for U3 and U4 are determined by R2 and
1
DG MOSFETs in an identical manner. The resulting R7, and R3 and R8, respectively, which is Vcc (equivalent
2
resonant circuits, including U3 and U4, are shown in Figure
to 4.5 V). Cstatic-1 and Cstatic-2 are sufficiently charged by this
4. Figure 4 includes additions to the resonator circuit, such
DC bias, thus resulting in a sustained start-up and
as R2 and R3, which introduce a DC bias. R1 and R4 provide
oscillation.
the required source voltage VS.

Fig. 4 Resonant circuit including loading DG MOSFETs

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Fig. 5 Complete VCO design using active-loading differential architecture

To maintain VS, given a drain current of 2 mA, VS can in the schematic while being connected to Vcc, to allow the
be calculated as: usage of one voltage source at each point in the schematic.
The C1 and C2 are DC-blocking capacitors to prevent any
𝑉𝑆 = 5 = 9 − (2 𝑥 10−3 )𝑥 (𝑅1 )
unwanted DC from being injected into gate-1 of U1 and U2.
Here, R1 = R4 = 2.5 kΩ (E12 value of 2.7 k to be used, R9 and R10 provide pull-up to 4.5 V, provided by the node
as shown in Figure 4). The R1 and R4 will be used to bias formed R13 and R14.
both active-loading DG MOSFETs, as shown by previous
study. Referring to Figure 3, the biasing of U1 and U2, is 2.3. Development of Schematic Capture and PCB Design
similar to the biasing of the designed VCO. Given the node Several design considerations were made since the
labels ‘To_U1’ and ‘To_U2’ in Figure 4, these nodes will proposed VCO is a low-power device operating at high
form the drain of both U1 and U2, respectively, as shown in frequency and susceptible to noise. The hardware design
Figure 5. (schematic capture, PCB layout, and routing) has been
performed. Specific design practices have been followed to
Since the resonant frequency at any point of operation preserve signal integrity, reduce power consumption and
is generated by U3 and U4, U1 and U2 should be adequately contribute to overall circuit robustness:
filtered from power supply noise and low–frequency noise
• A 9 V regulator (Component P1 shown in Figure 6(a)) is
from the current mirror. This will ensure odd harmonics are
used to provide a stable supply voltage to VCO. Other
not coupled into the output of the VCO or add phase noise
than good design practise, since there are voltage-
to the VCO by appearing on the tuning line of the varactors
sensitive components (varactors, potentiometers) and
[28]. Considering second-order harmonics, the highest
low-power capability is a design goal, this is essential.
second harmonic is 200 MHz (second harmonic of 100
With the chosen regulator, there are two filter capacitors
MHz). Thus, an RC Low-Pass Filter (LPF) can be used, with
at the input and output terminal, as advised by the device
values R = 470 Ω, C = 1.7 pF. This can be seen in R12 and
datasheet [29].
C3 in Figure 5. The L3 absorbs any unwanted DC voltage
• Capacitors C6, C7 and the inductor L4 (shown in Figure
from the current mirror.
6(b)) have been added to the schematic as an extra level
As shown in Figure 5, R5 and R6 simulate a of redundancy. While the PCB footprints are not limited
potentiometer, given the .param commands in SPICE. In the to being capacitors or inductors, 0805 PCB footprints
snapshot shown in Figure 5, R5 = 2.5 kΩ and R6 = 7.5 kΩ. were used so that a pi-filter may be added if required
The node shown as Power has been used at different points [30]. A pi-filter can attenuate or amplify an output signal

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while matching input and output loads. This would be impedance, routed from a single point node, with all
needed for varying loads (75 Ω coaxial connectors or RF required traces branching from the singular node. This
loads). In the application and testing of the proposed ensures maximum power transfer and reduction of
VCO, L4 will be populated with a 0 Ω resistor since the possible ripple current [32].
proposed VCO was designed for a 50 Ω load and will be • A double-sided copper clad was used to etch the PCB,
used with a 50 Ω BNC connector. where one side was used as the signal plane, and the
• Power traces were routed using star-topology power other side was used as a ground plane. This can be
distribution, i.e. thicker traces used to reduce trace observed in Figure 7.

(a)

(b)

(c)
Fig. 6 Schematic for proposed VCO showing (a) Power supply section given by a 9V regulator, (b) Diode configuration and nMos current-source
biasing, (c) DGMOSFET signal transistors

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Fig. 7 The PCB layout and routing for the proposed VCO

Rohde & Schwarz FS300

9V Power supply
Spectrum analyser

Designed VCO

Fig. 8 High-level block diagram of the measurement setup

Fig. 9 Measurement setup for analysis of the designed VCO

3. Testing and Analysis of the Designed VCO dBc/Hz at 10 kHz and a dynamic range of > 137 dB. In
The requirement for testing an oscillator involves seeing this, the FS300 is sufficient to conduct the testing
using a spectrum analyser, which should have a phase on the designed VCO. A high-level overview of the test
noise of at least 10 dB better and have a suitable dynamic setup can be seen in Figure 8, with the actual experimental
range [33, 34]. The FS300 exhibits a phase noise of < -90 setup shown in Figure 9.

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Fig. 10 Transmit power at 72.9 MHz Fig. 12 Peak output power of approximately -2 dBm

Fig. 11 Transmit power at 100 MHz Fig. 13 Transmit power vs frequency for tuning range

3.1. Output Power

The output power of a fully-fledged VCO from harmonic, these results are depicted in Figure 13. A clear
APITech [35] ranges from 7 – 10 dBm minimum. These degradation is observed for frequencies above the tuning
VCOs typically include amplifiers and buffer circuitry, range, i.e. frequencies greater than 100 MHz. This can be
increasing output power [36]. In the designed VCO, neither improved by adding an output buffer or using conventional
a buffer nor a Darlington configuration was used to drive the methods to improve the phase noise at these frequencies.
load. The transmit power was measured for the frequency These may include a decrease in the tuning voltage gain
range of 70 – 200 MHz (this includes the second harmonic KVCO. The tuning voltage gain is determined by the ratio of
of the tuning range, i.e. 70 – 100 MHz). The transmit power frequency to voltage. Reducing this would entail increasing
at 73 MHz can be seen in Figure 10, which is -7.69 dBm, the supply voltage, as shown by Hsu et al. [35], where an
shown by the blue marker. At the furthest end of the increase of power dissipation from 3 mW to 5 mW yields a
spectrum (excluding the second harmonic), the transmit phase-noise improvement of approximately 85 dBc/Hz.
power at 100 MHz is -5.48 dBm, as shown in Figure 11. The Replacement of the current mirror with a full cascode output
maximum output power of -2.91 dBm is shown in Figure 12. stage, as implemented by [13], will reduce the amount of
noise coupled into the output. Table 1 summarises the output
Following further results of the tuning range of 70 power in dBm and Vpk-pk, depicted in Figure 13.
– 100 MHz, which includes the transmit power of the second

Table 1. Frequency vs Power (dBm, Vpk-pk)

Frequency (MHz) Output Power (dBm) Output Voltage (Vpk-pk)
73 -7.74 0.26
85 - 2.91 0.45
100 -5.48 0.37
150 -16.2 0.098
175 -11.2 0.17
200 -21.5 0.053

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3.3.1. Frequency Offsets from a Single Oscillating

Frequency
The phase noise for a VCO can be assessed by specified
offsets to characterise the noise in the oscillating frequency.
Balogun et al. [38] have shown the degradation of optical
transmission systems, given carrier frequency offsets in
phase noise estimation.

Figure 15 shows the importance of measuring the phase

noise at different offsets, as the phase noise level should
ideally follow the profile shown, from an initial offset of 10
Hz to 10 MHz, which should resemble the noise floor of the
VCO. This form of phase noise is also known as discrete
Fig. 14 Tuning sensitivity for proposed VCO
phase noise [9] and is given by:
3.2. Tuning Sensitivity
Phase Noise (Discrete) = P(Carrier) - P(Carrier ± frequency offset) (7)
A VCO’s tuning range is determined by its resonant
circuit's collective inductance and capacitance. As designed
Where P(Carrier) is the power of the carrier signal in dBm,
in the proposed VCO, varactor diodes are used to provide a
and P(Carrier ± frequency offset) is the power of the carrier signal that
variable capacitance. The voltage of this resonant circuit
is shifted by an offset. The continuous phase noise of the
determines the efficiency, power consumption, and linearity
output signal can also be approximated using the discrete
of the VCO’s operation [37]. The formula to compute the
bandwidth, which is the phase noise per 1-Hz bandwidth and
tuning sensitivity for a tuning range is:
is dependent on the carrier’s resolution bandwidth (RBW)
⍵2 − ⍵1 and carrier offset.
𝐾𝑉𝐶𝑂 = (6)
𝑉2 − 𝑉1

Where ⍵1 and ⍵2 are oscillating frequencies, and V1

and V2 are the corresponding voltages of the resonant circuit
outputs/varactor diodes output junction. The tuning
sensitivity of the proposed VCO is depicted in Figure 14.

For the tuning range of 73 MHz – 85 MHz, given

Equation 6, the tuning sensitivity KVCO is approximately
10.23 MHz/V. For the tuning range of 85 MHz – 100 MHz,
KVCO is 2.3 MHz/V.
3.3. Oscillator Phase Noise (PN)
As discussed, the PN of a VCO determines its spectral
purity and immunity to noise coupled into the circuit for “x”
Hz away from the oscillating frequency, where “x” is a
frequency offset. The phase noise from a source can be
caused by a number of factors, e.g. internal noise of varactor
diodes, power supply noise, inherent noise of the
Fig. 15 Typical phase-noise profile for a VCO [15]
semiconductors used, etc. [37].

Fig. 16 Carrier ≈ 85 MHz, output power = - 2.21 dBm, RBW = 10 Fig. 17 Carrier ≈ 86 MHz, showing an output power = -72.0 dBm,
kHz RBW = 100 kHz, carrier offset = 1 MHz

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The RBW is proportional to the bandwidth of the Thus, for PN(Discrete), the continuous phase noise
signal. As shown in Figure 16 and Figure 17, the RBW of PN(Continuous) can be defined as the PN in a 1-Hz
the signal is 10 kHz and 1100 kHz, shown in the top-left of bandwidth at the same offset used to compute PN(Discrete).
the analyser’s screen. To compute the continuous phase The test results for the discrete (PN(D)) and continuous
noise: phase noise(PN(C)) measurements can be seen in Table 2
and Table 3, given the RBW used, output power Po and
Phase Noise (Continuous) = Phase Noise (Discrete) – 10log(RBW) carrier offset.
(8)
Table 2. Test results for discrete phase noise vs Carrier offset

fo + 10 kHz fo + 100 kHz fo + 1 MHz

fo Po Po PN(Discrete) Po PN(Discrete) Po PN(Discrete)
(MHz) (dBm) (dBm) (dBc/Hz) (dBm) (dBc/Hz) (dBm) (dBc/Hz)
85 (84.994) -2.21 -4.88 -2.67 -67.5 -65.29 -72 -69.79

170 (169.98) -10.2 -18.4 -8.2 -76.3 -66.1 -71.9 -61.7

Table 3. Test results for continuous phase noise vs Carrier offset

fo + 10 kHz fo + 100 kHz fo + 1 MHz
(RBW = 10 kHz) (RBW = 10 kHz) (RBW = 100 kHz)
fo Po PN(D) PN(C) PN(D) PN(C) PN(D) PN(C)
(MHz) (dBm) (dBc/Hz) (dBc/Hz) (dBc/Hz) (dBc/Hz) (dBc/Hz) (dBc/Hz)
85 (84.994) -2.21 -2.67 -42.67 -65.29 -105.29 -69.79 -119.79

170 (169.98) -10.2 -8.2 -48.2 -66.1 -106.1 -61.7 -111.7

*fo is the fundamental/oscillating frequency

Fig. 18 Graph showing continuous and discrete phase noise for a carrier frequency of 85 MHz

3.3.2. Singular Frequency Offset for the Entire Tuning VCO and the subsequent second harmonics. The phase
Range noise for 73.1 MHz – 200 kHz (which is 72.9 MHz) and 100
A singular frequency offset of 200 kHz was chosen for MHz + 200 kHz (100.2 kHz) was measured to be - 51.71
this measurement, and the phase noise was manually dBc/Hz and - 50.52 dBc/Hz, respectively. A summary of the
measured. The tuning range of the oscillator is 30 MHz (70 results can be seen in Table 4, and the comprehensive testing
– 100 MHz); thus, an offset < 1% of the tuning range was for phase noise vs carrier offset can be seen in Figure 18,
chosen for granularity. For a frequency offset of ±200 kHz, followed by the phase noise over the frequency range in
the phase noise was measured for the tuning range of the Figure 19.

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Table 4. Phase noise for the proposed VCO

fo – 200 kHz fo + 200 kHz
Fundamental Output power Output Power Phase Noise Output Power Phase Noise
Frequency fo (MHz) Po (dBm) (dBm) (dBc/Hz) (dBm) (dBc/Hz)
72 -7.69 -57.2 -49.51 -59.4 -51.71
85 -2.91 -56.6 -53.69 -55.6 -52.69
100 -5.48 -56.2 50.72 -56 -50.52
The second harmonic of the tuning range
150 -16.2 -61.1 -44.9 -57.3 -41.1
175 -11.2 -55.4 -44.2 -50.6 -39.4
200 -21.1 -59.2 -38.1 -60.4 -39.3

3.4. Figure of Merit (FOM) and Tuning Figure of Merit

(FOMT)
While considering all aspects (phase noise, bandwidth
of oscillating frequency, and power consumption), the
FOM provides a comprehensive performance index for
tuning oscillators. The FOM [26] can be approximated by:
𝑓 𝑃𝐷𝐶
FOM = PN - 20∙log10 ( 𝑐 ) + 10∙log10 ( ) (9)
∆𝑓 1 𝑚𝑊

where fc is the oscillating/centre frequency, ∆f is the

carrier offset, and PDC is the power consumption. It is
Fig. 19 Phase noise computation for the proposed VCO for the appropriate to evaluate the FOM at a centre frequency of
designed tuning range and second harmonic 85 MHz, given the power consumption is at its peak, as
peak output power is provided at this frequency. The
From the measurement of the phase noise of the FOM can be visualised in Figure 20 for similar carrier
VCO, observations can be made about its performance at offsets used to compute the phase noise in section 3.3.1.
high frequency and noise immunity. In section 3.3.1, the The FOMT is the resultant tuning FOM, which would
classical definition for the phase noise of a VCO was include the entire tuning range, using the FOM as a
followed, given by cited works, i.e. the power of a signal reference [27]. The FOMT can be given by:
at a carrier offset (typically each decade) was subtracted
from the power of the carrier itself. The computation was 𝑓 𝑇𝑅% 𝑃𝐷𝐶
FOMT = PN – 20∙log10 (( 𝑐 ) ∙ ) + 10∙log10 ( ) (10)
done manually using markers provided by the spectrum ∆𝑓 10 1 𝑚𝑊

analyser. Using a carrier offset of 1 MHz and the oscillating

Given the highest transmit power, the carrier Frequency of 85 MHz, PDC can be approximated as peak
frequency of 85 MHz should exhibit the lowest phase power consumption (36 mW). The TR = 35% is the
noise for the entire tuning range [15]. This is possibly percentage of the difference in voltage of varactor diode
attributed to a higher Q-factor occurring at this resonant junctions between 85 MHz and 86 MHz. Here, the FOMT
frequency [18] and the reduction in the overall on- is approximately -126.76 dBc/Hz for a 1 MHz carrier
resistance of U3 and U4, given the inductance and offset using Equation 10.
capacitance of the LC resonator circuit (shown in Figure
4) [20]. In section 3.3.2, a singular carrier offset of 200
kHz was used to allow computation of the phase noise for
the entire tuning range (70 – 100 MHz), which is provided
by the designed VCO, and not a single fundamental
frequency.

As expected, PN increases as the fundamental

frequency increases for the tuning range only. A high-
phase noise can be observed at the end of the tuning range
(for the fundamental frequency and its corresponding
second harmonic). Using Figure 15 as a reference, the
proposed VCO achieves -2 dBm/decade for a 10 kHz
offset, then < -60 dBc/Hz for a 100 kHz carrier and above
[40-43], as shown in Figure 18. This is favourable at high
frequencies, as the signal’s noise floor resides at a low Fig. 20 FOM vs Carrier frequency for a fundamental frequency of
power level. 85 MHz

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3.5. Summary of Proposed VCO Specifications and comparative summary is performed in Table 6, from all
Comparative Analysis noted literature. The comparison is done between common
The resultant specifications for the designed VCO and parameters of interest.
its HW implementation are shown in Table 5. A further
Table 5. Results of testing and analysis of the hardware implementation of the proposed VCO
Test Results of HW
Parameter
Implementation
Tuning range 73 – 100 MHz

Output power 36 mW

Voltage supply 9V
10.23 MHz/V (73 – 85 MHz);
Tuning gain
2.3 MHz/V (85 – 100 MHz)
Discrete Phase noise (best for tuning range, occurring at 85 MHz, 1 MHz offset) -69.79 dBc/Hz

Continuous Phase noise (best for tuning range occurring at 85 MHz, 1 MHz offset) -119.79 dBc/Hz

Phase noise (best for the second harmonic, occurring at 170 MHz, 100 kHz offset) -66.1 dBc/Hz

Continuous Phase noise (best for second harmonic occurring at 170 MHz, 1 MHz offset) -111.7 dBc/Hz

FOM -92.82 dBc/Hz

FOMT -126.76 dBc/Hz

Table 6. Comparison of the different design techniques with this work

VCO designed Tuning Range Output Power Phase Noise* FOM* Power Consumption
24 mW, given a supply
Widely Tunable K- 18.2 GHz – -179 dBc/Hz
- 1.35 dBm -105 dBc/Hz (1 MHz) current of 24 mA and
band [8] 23.28 GHz (1 MHz)
supply voltage of 1V
26.38 GHz- -108.57 dBc/Hz and - -108.57
90nm Push-push
28.15 GHz; 98.43 dBc/Hz for each dBc/Hz; -
Dual-band Cross- -37dBm -
52.76 GHz - tuning range, 98.43 dBc/Hz
coupled [10]
56.30 GHz respectively (10 MHz)
Low Power, High-
Speed Differential 87 – 910 MHz - - - 3.11 mW
Amplifier Ring [11]
Fundamental VCO
117.5 – 121.5 1.86 W (310 mA from
with integrated 3dBm at peak -93.3 dBc/Hz (1 MHz) -
GHz a 6 V power supply)
output buffer [12]

3.59 – 3.69 -130.1 to -129.1 -183.9 dBc/Hz 56 mW (11.2 mW at 5

Colpitts VCO [13] -5 to -5.1 dBm
GHz dBc/Hz (1 MHz) (1 MHz) V supply)

Noise-shifting 3.58 – 3.67 -2.5 to -3.5 - 132.4 to – 130.2 -186.3 dBc/Hz 54 mW (10.8 mA at 5
Colpitts [13] GHz dBm dBc/Hz (1 MHz) (1 MHz) V supply)

Fabricated
2.76 – 2.91 -3.06 dBm to - - 138.6 to- 135.9 -191.2 dBc/Hz 47.5 mW (9.5 mA at 5
Darlington-based
GHz 4.18 dBm dBc/Hz (1 MHz) (1MHz) V supply)
class-C [13]
-7.74 dBm to -
73 – 100 MHz; 2.91 dBm; - -69.79 dBc/Hz (1 -92.82 dBc/Hz 36 mW (4 mA at 9V
This Work
140 - 200 MHz 21.5 dBm to - MHz offset) (1 MHz) supply)
5.44 dBm

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Fig. 21 Analysis of the tuning range and phase noise

Given Table 6, Figure 21 denotes the analysis and the The oscillator’s phase noise was measured extensively,
graphical relationship between the tuning range and phase providing insight into the noise level at different oscillating
noise for the noted literature. The use of an output stage has frequencies and frequency offsets. The designed VCO
been shown to improve the phase noise for VCOs with a exhibits its best discrete PN of -69.79 dBc/Hz at 85 MHz, at
larger tuning range than the designed VCO, given that the a carrier offset of 1 MHz. The phase noise can be improved
referenced literature all exhibit a lower phase noise. given the cited works in Table 5. A method to improve the
However, the addition of such output stages degrades the phase noise is to include a low-noise buffer for the specified
output power relative to the power consumption and application.
resulting power efficiency (given by the radius of each
bubble in Figure 21). The buffer can prevent unnecessary current-sinking
from the oscillator’s output. Several considerations must be
4. Conclusion and Future Recommendations made when designing a buffer, such as impedance matching
The designed VCO and its design process have been (which provisions were made for in the schematic design for
defined to achieve the output power while employing the proposed VCO) and noise reduction techniques (filtering
measures for noise suppression, such as filtering and of low-frequency noise). To further reduce the phase noise,
optimal PCB design measures. As noted in the functional replacing the varactor diode can be considered to potentially
specifications, the output power was designed to be -2 dBm provide more capacitance in the resonator circuitry. Given a
at peak, which is approximately 500 mVpk-pk. This has been power supply voltage of 9 V and a nominal drain current of
achieved (as in Figure 12) at 85 MHz. The Q-factor of the 4 mA, the power consumption of the proposed VCO is 36
VCO is the highest at this frequency. For the tuning range mW. The output power produced by the VCO indicates
of 70 – 100 MHz, the output power ranges between -7.74 better power efficiency to cited works.
dBm and -2.91 dBm. This translates to an output of 200mVpk-
From the analysis of the designed VCO and design
pk – 500 mVpk-pk. This has met the functional specifications
outlined for the design of the VCO. Given this output power, constraints imposed, the VCO can maintain a better FOM of
the proposed VCO aligns with the relevant literature, as the -92.82 dBc/Hz, given a dual-band output and can be greatly
comparative study shows. improved by simple additions to the design. From the cited
works, which include the measures of providing low power
The tuning sensitivity of the proposed VCO can be consumption, the proposed VCO performs better in this
improved by choosing an alternative varactor diode. Given regard, with a larger supply voltage and lower power
hindsight, the need arises as the low tuning sensitivity of the consumption. This contributes to better power efficiency.
85 – 100 MHz tuning range can be improved. The varactor This shows that the active-loaded differential topology,
diode and resonant circuit are adequate for providing a full coupled with the DG MOSFET, can provide a high output
tuning range. An abrupt diode may be used to find an power for lower noise production.
alternative to the hyperabrupt diode used in the proposed Applications would be able to tailor the designed VCO
VCO. The abrupt diode provides a larger tuning range (0 – to their specification and improve their system, which has
60 V, compared to the tuning range of the hyperabrupt diode, also been made easier by adding the pi-filter in the PCB
which is approximately 0 – 20 V). An abrupt diode can design. In addition to this, in the future, various materials,
provide a higher Q, reducing the phase noise coupled to the such as high-k dielectrics material, can be used in addition
output by the varactor diode.

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 Suvashan Pillay & Viranjay M. Srivastava / IJETT, 71(12), 248-263, 2023

to different MOSFET structures, such as the CSDG Funding

MOSFET. This research work is funded by the Electricity Supply
Commission (Eskom), South Africa, dated 31 January 2020,
Frequency pushing and load pulling are further
under the Tertiary Education Support Programme (TESP).
investigations to be completed in this work, which requires
the schematic to be re-designed partially to accommodate
the absence of a 9 V regulator (this would be removed to Data Availability Statement
provide a comprehensive analysis, allowing the supply All data and materials used to prepare this manuscript
voltage to fluctuate naturally), addition of the pi filter and are available in this document.
output buffer. The designed VCO could also be improved
by using an abrupt varactor diode, further investigating the Acknowledgements
tuning characteristic and resulting phase noise. Authors are thankful to Mr. Logan Pillay, Chairperson
of TESP, Mr. Cecil Ramonotsi, CEO, Eskom Development
Author Contributions Foundation, South Africa and Mr. Tshidi Ramaboa, Eskom
Suvashan Pillay and Viranjay M. Srivastava conducted Academy of Learning, Human Resources, Midrand. The
this research; Suvashan Pillay designed and analyzed the authors are also thankful to Ms. Leena Rajpal, Public
model with data and wrote this article; Viranjay M. Relations Officer, University of KwaZulu-Natal, Durban,
Srivastava has verified the result with the designed model; South Africa, for providing various support to carry on this
all authors approved the final version. research work.

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Appendix 1
Bare PCB after etching of copper clad (before drilling of holes to the ground layer)

Populated PCB (soldered components, soldered vias to connect up-side to bottom-side GND)

263