A 18GHz Rotary Traveling Wave VCO in CMOS with I/Q outputs

G. Le Grand de Mercey
Student Member IEEE
Universität der Bundeswehr
Werner-Heisenberg Weg 39
D-85 577 Neubiberg
[email protected]

Abstract
A voltage controlled oscillator (VCO) based on the ro-
tary traveling wave principle is presented. Its advantages
are easy and accurate high frequency quadrature signal
generation, adiabatic operation, and good phase noise
properties. The VCO is realized with the commercially
available TSMC 0.13µm CMOS process. The 18-GHz
VCO has a tuning range of 1 GHz. The phase noise power
spectral density observed is -117 dBc/Hz at a 1-MHz off-
set from the carrier. The complete circuit including buffers Figure 1. View of the main devices composing the Ro-
consumes 24 mW from a 1.2V power supply. The die with- tary Traveling Wave VCO
out pads occupies 0.12µm2 .
regime, which is cross-connected to insure a reverse feed-
1. Introduction back. The reverse feed-back imposes a signal inversion
after one round delay τ , so that oscillations between the
CMOS technology offers now features which make it two polarization states of the line occurs with a period 2τ .
possible to implement strip-lines. One reason is that the Inverters play here a double role: they impose the odd-
distance between the substrate and the top thick metal mode operation for the differential line and sustain the os-
layer is sufficiently large. This yields a good enough cillations, replenishing the energy losses occurring in the
property for high speed applications, despites a low re- strip line. The round trip delay is given by the line proper-
sistivity substrate[1] [2]. Monolithic transmission line on ties and the devices loading it. The oscillation frequency
CMOS offers new design opportunities, among them, new is expressed as:
architecture of high speed oscillators. The rotary travel-
ing wave oscillator was first proposed by John Wood and 1
fosc = √ (1)
al.[3], it was however dedicated for clock generation and 2 LT CT
the tuning of the oscillation frequency was not of major where LT is the total inductance of the line and CT is the
concern. Other VCOs using integrated strip-lines have total capacitance. Total capacitance include the one of the
been published [4]. Although based on the same dis- line, of the inverters tapping the line and of the varactors.
tributed principle, they have a single-ended architecture Those varactors are required to tune the oscillator.
and are not able to generate I/Q output from one oscillator. Such an oscillator combines the advantages of both, the
The VCO proposed confirms the feasibility and demon- LC tank and the ring oscillator. The resonator has the LC
strates the advantages of the rotary structure at high fre- characteristics from the line properties, meaning it is able,
quency on a commercially available CMOS process. A like in conventional discrete LC tank, to store energy, but
brief review of the operation of the ”RTW-VCO” is first it is also a distributed medium, meaning it acts like a wave
described, followed by a review of each component. After resonator: the wave propagates on the strip-line and the
design and layout considerations, results are presented. phase depends on the location considered. Basically, in
a RTW-VCO, all phases are available. Depending on the
2. Rotary Traveling Wave, principle of output positions, true I/Q signal can be generated, prere-
operation quisite is they oppose each other.
The energy used to switch the inverters is part of the wave
Figure 1 depicts the VCO. The resonator is a ring com- energy circulating within the line, this energy is not di-
posed of a differential strip line working in odd mode rectly correlated to losses. This VCO is an adiabatic cir-
cuit since losses occur only in the line and device resis- where N is the number of stages and Gm the transcon-
tances. ductance of each gain stage. Maximizing Zo relaxes the
requirement on Gm to achieve a unity gain (A ≥ 1).
3. Strip-Line
4. Amplifier stage
In order to design the oscillator for a predetermined
frequency, a precise equivalent circuit from the strip-line For the realization of the inverter stages, we used
is required as shown figure 2. The equivalent circuit has the complementary cross-coupled inverter without current
two modes of propagation, the even mode corresponding source to maximize the signal swing. This topology of
to a common mode (same signal on both lines) and the
odd mode corresponding to the differential mode.
The differential structure offers several advantages com-

Figure 2. Model for the differential strip-line extracted

from a field simulator Figure 3. Complementary cross-coupled inverter used
including varactors
pared to singled ended distributed oscillator. First, the
resonator is a fully closed structure without problems of negative resistance in voltage-limited regime offers sev-
impedance termination over the bandwidth considered. eral advantages. The common mode on the strip-line is
Second, forwards and backwards traveling currents are de- set without any additive transistor for biasing, so a source
fined making it easier to determine the value of the induc- of noise is spared. Fast switching and symmetric rise- and
tance [3]. A not to underestimate advantage is the reduced fall- time [5] improves the phase noise properties and re-
influence of the substrate losses and capacitances. Indeed, sults in a lower 1/f 3 noise corner. Disadvantage of such
the dominant capacitor is the fringing capacitor between a structure is its high sensitivity to the power supply, a
the two line which has a doubled effect in the odd mode stable power-supply design is needed to avoid frequency
(Cf in the fig 2). pushing and noise injection. Another advantage in our
Even and odd mode propagation parameters of the line case for this topology over the all-NMOS inverter stage
are simulated with a 3D field simulator (HFSS) and from is the higher capacitance load to the line it provides. The
them, the equivalent circuit is derived. The results are: length of the line can be thus relatively short.
Table 1. Strip-line parameters
5. Varactors
Mode Impedance Propagation Constant
√
q
Even Ze ≈ Le
γe ≈ ±jω Le Cox Frequency tuning in distributed VCOs at high fre-
Cox
q p quency requires a way to decrease or increase the propaga-
Lo
Odd Zo ≈ Cox +2Cf
γo ≈ ±jω Lo (Cox + 2Cf ) tion delay. H. Wu proposed a way to shorten the electrical
Le = L(1 + k) Lo = L(1 − k) length at the cost of a more complicated circuit[4].
Another way to vary the delay is to have a variable ca-
pacitance loading the line. The varactor we considered
From a design point of view two aspects are of partic- are based on the MOS structure. At high frequencies, it
ular importance. appears that the only available varactor with acceptable
Since in a strip-line the power dissipation is governed by: properties is the NMOS structure biased between deple-
V2
Pdiss = Zdd2 .Rloop , it is obvious that a maximum Zo tion and inversion (fig 4).
o
impedance is of utmost importance for power reduction. Drawbacks of this varactor is its steep capacitance over
The open-loop gain of the oscillator represents the gain of tuning voltage characteristic. It implies a small tuning
a differential distributed amplifier and is equal to (without window with great sensitivity to Vtune . This means more
loss consideration): sensitivity to noise from Vtune and Vgate but also, since
Zo the transition is abrupt, a non-symmetrical output wave-
A = −N Gm (2) form leading to increased up-conversion of low-frequency
2
 where Rl is the equivalent resistance of the loading ele-
ments. Once the parameters from the line, the inverters,
and the varactors are known, one can determine the VCO
center frequency where n is the number of stages involved.
1
fosc = q (5)
Cl
2nl L(C + l )

Figure 4. NMOST varactor effect on the line, whereas

the normal varactor has a steep slope s the ”distributed”
equivalent varactor has a softer slope s/lv

noise. These remarks are valid for the varactor as discrete

device but as integrated device in the RTW-VCO, as far
as the distributed approximation is valid, the varactor is
distributed on the line. Its effect on the RTW-VCO are
slightly different. As depicted on the figure 4 the dis-
tributed varactor has a softer slope. By considering that
space between two varactors is lv , the slope of the equiv-
alent distributed small signal capacitance is inversely pro-
portional to lv . So that for this structure a ”steep” varactor Figure 5. Die
is compatible with reasonable value of VCO gain (Kvco ,
Fig 6). From the designer point of view the values of the The circuit (Fig. 5) is realized in a 0.13 µ m technol-
loading capacitor has to be large enough to be effective ogy. In order to minimize magnetic coupling, 90 degrees
but also small enough to be distributed. A compromise layout techniques is extensively used: all dc line are or-
has to be found knowing that the larger the transistor and thogonal to the high frequency line as far as it is possi-
the better its quality factor. ble. The whole length of the line is 1.6mm, with a thick-
ness of 4µm and width of 4µm. The spacing between
the lines is 10 µm. HFSS gives the following odd pa-
6. Design and layout Considerations rameters: Lodd = 305.4nH/m; Rodd = 2, 88kΩ/m;
To start with, the total dimension of the added ampli- Codd = 127.5pF/m. Inverters and varactors are multi-
fiers and varactors have to be determined first. This de- finger structures to minimize the gate resistance and are
termines the oscillation’s frequency. Then the number of in a deep-N-well process to avoid substrate coupling. On-
elements (amplifier plus varactors) has to be determined. chip decoupling capacitance between Vdd and Vss are also
The cutoff frequency of the resonator without loss consid- closed to the inverter and varactor-blocks. The loading ca-
eration is(Bragg frequency): pacitor from the cross-coupled inverter is simulated to be
Cinv = 462f F . The varactor for a zero tuning voltage
1 has a capacitor value of 100f F and a quality factor of
fbragg = q (3)
πl L(C + Cl Q = 12. Although the optimum Nmax ≤ 5, four stages
l )
oscillator is choosen for symmetrical and place availabi-
where L and C are the inductance and capacitance per lity reasons. The estimated oscillation frequency is equal
length of the strip line, Cl is the equivalent loading capaci- to: fosc = 17.7GHz for 0V tuning voltage which is in
tor from amplifier plus varactor, and l is the space between agreement with the measured performances, see Fig. 7.
two tapping elements. For a given frequency the product The two output, opposed in layout to obtain 90 degrees
n.l is constant, where n is the number of elements. The offset, have buffers at the end of their tapping differential
more elements are used, the highest the cutoff frequency line. Just one output is measured, the coplanar strip to the
since l decreases. This results in steep transitions for the pads is designed to have a 50Ω impedance.
oscillations and thus less phase noise for the VCO. How-
ever, losses in the tapping components have to be taken 7. Results
into consideration. It results from them a maximum num-
Measurements were performed on wafer with DC and
ber of loading components nmax [6]:
HF-probes. The measured power spectrum is shown fi-
2 gure 7. A 12dB insertion loss is due to the measurement
nmax ≤ (4) setup (from the probes to the spectrum analyzer). The
Rl ω 2 Cl2 Zo
va-ractor tuning achieves a tunig range of 5.6% (Fig. 6).
The phase noise of the oscillator (Fig. 8) is -117 dBc/Hz
at 1 MHz offset from a 17.99 GHz carrier with a total
current of 20 mA with output buffers and 14.4 mA with-
out buffers. The Figure of Merit as defined in [7] is:
FOM=-189 dBc/Hz. It is better than the reported values
so far (table 2). Moreover, the VCO compared are not able
to generate different output phases.

Table 2. Comparison of FOM and phase noise at 1

MHz offset from the carrier of recently published CMOS
integrated VCO

VCO Power Phase Noise FOM

Figure 8. Phase Noise from a 17.99 GHz carrier (worst
mW dBc/Hz dBc/Hz
case Vtune = 0, 3)
[8] 10.5 −108 −182
[4] 9 −84 −159
(This) 14.4 −117 −189 more than two phases, for example phase detector de-
manding four or height phases.

9. Aknowledgments
The author would like to thank C. Holuigue, F.Roger,
S. Mechnig, from Xignal Technologies, for their help and
support in the realization of the Chip. Special thanks to
Prof. Hoffmann and R. Kraus for their advices, F. Gold-
straße and A. Hörig for their assistance to measurements
at the Bundeswehr University.

[1] B. Kleveland, “ Exploiting CMOS Reverse Interconnect

Scaling in Multigigahertz Amplifier and Oscillator Design”,
Figure 6. Tuning Range and Kvco curve IEEE Journal of Solid-State Circuits, vol. 36 , pp. 1480-
1487.
[2] B. Razavi, “The Role of Monolithic Transmission Lines in
High-Speed Integrated Circuits”, IEEE 2002 Custom Inte-
grated Circuits Conferance, pp. 367-374.
[3] J. Wood, T.C. Edwards, and S. Lipa, “Rotary Traveling-
Wave Oscillator Arrays: A New Clock Technology”, IEEE
Journal of Solid-State Circuits, vol. 36 , pp. 1654-1665.
[4] H. Wu, and A. Hajimiri, “ Silicon-Based Distributed
Voltage-Controlled Oscillators”, IEEE Journal of Solid-
State Circuits, vol. 36 , pp. 493-501.
[5] A. Hajimiri, and H. Lee, “ Design Issues in CMOS Differen-
tial LC Oscillators ”, IEEE Journal of Solid-State Circuits,
vol. 34 , pp. 717-724.
[6] Y. Ayasli, “ A Monolithic GaAs 1-13-GHz Traveling Wave
Figure 7. Spectrum Amplifier”, IEEE Transactions on Microwave Theory and
Techniques, vol. MTT-30 , NO. 7 pp. 976-981.
[7] M. Tiebout, “ Low-Power Low-Phase-Noise Differentially
8. Conclusion Tuned Quadrature VCO Design in standard CMOS”, IEEE
Journal of Solid-State Circuits, vol. 36 , NO. 7 pp. 1018-
The paper shows the feasibility of the RTW-VCO 1024.
at high frequencies using standard NMOS transistor [8] R. C. Carl, “ A 0.25µm CMOS 17 GHz VCO”, IEEE ISSCC
as varactor. Advantages of this quadrature VCO rely 2001, pp. 370-371.
on its compactness, its good phase noise performances
(−117dB/Hz at 1M Hz offset) at relatively low power
consumption (14.4mW ). The RTW-VCO offers new op-
portunities of design demanding high-speed clock with