Last Lecture: Introduction To Sequential Logic and Systems

Overview
! Last lecture " Introduction to sequential logic and systems

# The basic concepts # A simple example
! Today " Latches " Flip-flops

# Edge-triggered D # Master-slave
" "
Timing diagrams T flip-flops and SR latches
CSE370, Lecture 14
The D latch
! Output depends on clock " Clock high: Input passes to output " Clock low: Latch holds its output ! Latch are level sensitive and
Input D Q Q CLK Output Output
transparent
CLK D Qlatch
CSE370, Lecture 14
The D flip-flop
! Input sampled at clock edge " Rising edge: Input passes to output " Otherwise: Flip-flop holds its output ! Flip-flops are rising-edge triggered,
Input D Q Q CLK Output Output
falling-edge triggered, or master-slave

CLK D Qff
CSE370, Lecture 14
Terminology & notation

Rising-edge triggered D flip-flop
Input D Q Q CLK Output Output CLK
Positive D latch
Input D Q Q Output Output
Falling-edge triggered D flip-flop

Input D Q Q CLK
CSE370, Lecture 14
Negative D latch
Input D Q Q CLK
4
Output Output
Output Output
Latches versus flip-flops

D Q Q
CLK D
CLK D Q Q CLK
Qff Qlatch
behavior is the same unless input changes while the clock is high
CSE370, Lecture 14
The master-slave D
Master D latch
Input D Q
Slave D latch
D Q Output
CLK
master-slave D flip-flop
Class example: Draw the timing diagram
CSE370, Lecture 14
Flip-flop timing
"
"
Setup time tsu: Amount of time the input must be stable before the clock transitions high (or low for negative-edge triggered FF) Hold time th: Amount of time the input must be stable after the clock transitions high (or low for negative-edge triggered FF)
data D Q D Q
data clock
tsu th
clock
There is a timing "window" around the clock edge during which the input must remain stable
CSE370, Lecture 14
stable data clock
changing
Flip-flop timing (contd)

! Timing constraints " Must meet setup and hold times " Must meet minimum clock width " Will have propagation delays (low to high & high to low)
tsu th 20ns 5ns
Q Q
tsu th 20ns 5ns tw 25ns
CLK
CLK
Q tplh 25nsmax, 13nstyp tphl 40nsmax, 25nstyp

8
CSE370, Lecture 14
Latches versus flip-flops

D Q Q
CLK D
CLK
Qff
Q Q
Qlatch
behavior is the same unless input changes while the clock is high
CLK
CSE370, Lecture 14
The master-slave D
Master D latch
Input D Q
Slave D latch
D Q Output
CLK
master-slave D flip-flop
Class example: Draw the timing diagram
CSE370, Lecture 14
10
How do we make a latch?

! Two inverters hold a bit " As long as power is applied
"1" "0" "stored bit"
! Storing a new memory " Temporarily break the feedback path

"remember" "data"
CSE370, Lecture 14
"load"
"stored bit"
11
How do we make a D F/F?

! Edge triggering is difficult " Label the internal nodes " Draw a timing diagram " Start with Clk=1
W X Q Clk Y D Z Q
CSE370, Lecture 14
12
T flip-flop
! Full name: Toggle flip-flop ! Output toggles when input is asserted " If T=1, then Q ! Q' when CLK " " If T=0, then Q ! Q when CLK "
Input
T Q >
Input(t) 0 0 1 1
Q(t) 0 1 0 1
Q(t + #t) 0 1 1 0
CLK
CSE370, Lecture 14
13
The SR latch
! Cross-coupled NOR gates " Can set (S=1, R=0) or reset (R=1, S=0) the output
R Q Q'
! Cross-coupled NAND gates " Can set (S=1, R=0) or reset (R=1, S=0) the output
S' Q Q'
14
R'
CSE370, Lecture 14
SR latch behavior
! Truth table and timing
R Q Q' Hold Set S 0 0 1 1 Reset Set R 0 1 0 1 Q hold 0 1 disallow Race
S Reset R S Q Q'
CSE370, Lecture 14
100
15
SR latch is glitch sensitive

! Static 0 hazards can set/reset latch " Glitch on S input sets latch " Glitch on R input resets latch
R S
Q Q'
CSE370, Lecture 14
16
Clear and preset in flip-flops

! Clear and Preset set flip-flop to a known state " Used at startup, reset ! Clear or Reset to a logic 0 " Synchronous: Q=0 when next clock edge arrives " Asynchronous: Q=0 when reset is asserted
# Doesn't wait for clock # Quick but dangerous
! Preset or Set the state to logic 1 " Synchronous: Q=1 when next clock edge arrives " Asynchronous: Q=1 when reset is asserted
# Doesn't wait for clock # Quick but dangerous
CSE370, Lecture 14
17

Last Lecture: Introduction To Sequential Logic and Systems

Uploaded by

Copyright:

Available Formats

Last Lecture: Introduction To Sequential Logic and Systems

Uploaded by

Document Information

Original Description:

Original Title

Copyright

Available Formats

Share this document

Share or Embed Document

Sharing Options

Did you find this document useful?

Is this content inappropriate?

Copyright:

Available Formats

Last Lecture: Introduction To Sequential Logic and Systems

Uploaded by

Copyright:

Available Formats

Overview

! Last lecture " Introduction to sequential logic and systems

! Today " Latches " Flip-flops

Timing diagrams T flip-flops and SR latches

falling-edge triggered, or master-slave

Terminology & notation

Falling-edge triggered D flip-flop

Latches versus flip-flops

Class example: Draw the timing diagram

stable data clock

Flip-flop timing (contd)

tsu th 20ns 5ns tw 25ns

Q tplh 25nsmax, 13nstyp tphl 40nsmax, 25nstyp

Latches versus flip-flops

Class example: Draw the timing diagram

How do we make a latch?

! Storing a new memory " Temporarily break the feedback path

How do we make a D F/F?

SR latch is glitch sensitive

Clear and preset in flip-flops

You might also like