230 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 39, NO.

1, JANUARY 2004

A 5.9-GHz Voltage-Controlled Ring Oscillator in 0.18-m CMOS

Yalcin Alper Eken, Student Member, IEEE, and John P. Uyemura, Senior Member, IEEE

Abstract—This paper presents the design of three- and

nine-stage voltage-controlled ring oscillators that were fabricated
in TSMC 0.18- m CMOS technology with oscillation frequencies
up to 5.9 GHz. The circuits use a multiple-pass loop architecture
and delay stages with cross-coupled FETs to aid in the switching
speed and to improve the noise parameters. Measurements show
that the oscillators have linear frequency-voltage characteristics
over a wide tuning range, with the three- and nine-stage rings
resulting in frequency ranges of 5.16–5.93 GHz and 1.1–1.86 GHz,
respectively. The measured phase noise of the nine-stage ring
oscillator was 105.5 dBc/Hz at a 1-MHz offset from a 1.81-GHz
center frequency, whereas the value for the three-stage ring
oscillator was simulated to be 99.5 dBc/Hz at a 1-MHz offset
from a 5.79-GHz center frequency.
Fig. 1. N -stage multiple-pass ring oscillator.
Index Terms—CMOS, LC oscillators, multiple-pass architec-
ture, phase-locked loop (PLL), phase noise, ring oscillators, VLSI, in Section III, along with a comparison of the results with other
voltage-controlled oscillators (VCOs). published circuits.

I. INTRODUCTION II. MULTIPLE-PASS RING OSCILLATORS

WITH SATURATED STAGES
T HE phase-locked loop (PLL) is a critical component in
many high-speed systems as it provides the timing basis
for functions such as clock control, data recovery, and synchro-
Because of the frequency limitations of a single-loop ring
oscillator, other architectural techniques are necessary to ex-
nization. The voltage-controlled-oscillator (VCO) is perhaps the plore the maximum frequency levels of ring oscillators. Some
most crucial element of the PLL because it directly provides of these techniques include the use of subfeedback loops [2],
the output signal of the PLL. A CMOS VCO can be built using output-interpolation methods [3], multiple-feedback loops [4],
ring structures, relaxation circuits, or an LC resonant circuit. The and dual-delay paths [5], [6].
LC design has the best noise and frequency performance owing The multiple-pass loop architecture, which is shown in Fig. 1
to the large quality factor Q achievable with resonant networks for an -stage ring, is the basic architecture chosen in this work.
[1]. However, adding high-quality inductors to a CMOS process This technique adds auxiliary feedforward loops that work in
flow increases the cost and complexity of the chip, and also in- conjunction with the main loop. The main idea is to reduce
troduces problems such as the control of eddy currents. the delay of the stages below the smallest delay that is pos-
Ring oscillators, on the other hand, can be built in any sible inside a simple ring oscillator loop. This is achieved by
standard CMOS process and may require less die area than LC adding a set of secondary inputs, and , to every stage
designs. The design is straightforward, and ring architectures and switching these earlier than the primary inputs during the
can be used to provide multiple output phases and wide tuning operation. Although the illustration is for an oscillator with an
ranges. In this brief, we present a design that improves the odd number of stages with the feedforward loops passing over
overall characteristics of CMOS ring oscillators to be com- a single stage, other configurations are possible to obtain a dif-
parable to those of LC designs. The prototype circuits were ferent frequency increase or decrease.
implemented in a standard TSMC 0.18- m non-epi CMOS It is important to note that the majority of the frequency-in-
process, and achieved maximum oscillation frequencies up to crease techniques discussed above [2], [4]–[6] depends on the
5.9 GHz with linear frequency–voltage characteristics. The use of intercoupled feedback loops to increase the maximum
architecture of multiple-pass ring oscillators and the use of frequency, similar to the multiple-pass loop architecture used
saturated gain stages to increase the frequency and voltage in this work. Basically, all of these methods are fundamentally
swing at the output are examined in Section II. Details of the same and they are based on a one-dimensional variation of the
design and measurement of the prototype circuits are presented coupled-oscillator structure introduced in [7] and discussed as
the look-ahead ring oscillator in [8].
Changing the architecture increases the oscillation frequency,
Manuscript received November 21, 2002; revised July 24, 2003. This work but phase noise and jitter are also important considerations.
was supported by Integrated Device Technology, Inc. Many ring oscillators use analog gain stages, but biasing
The authors are with the School of Electrical and Computer Engineering, the transistors into continuous conduction increases their
Georgia Institute of Technology, Atlanta, GA 30332-0250 USA (e-mail:
[email protected]). contribution to the total noise. To overcome this problem, the
Digital Object Identifier 10.1109/JSSC.2003.820869 gain transistors can be periodically switched in and out of
0018-9200/04$20.00 © 2004 IEEE
IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 39, NO. 1, JANUARY 2004 231

Fig. 2. Saturated gain stage with cross-coupled PMOS transistors.

conduction, which reduces the noise. The reduction of the noise

by switching is shown by [5] as
(1)
where is the output noise power of the oscil-
lator that incorporates switching, is the output
noise power if there was no switching, and is the conducting
time of the transistors in a period . Another problem with
using standard gain stages is the output signal amplitudes that
are much smaller than rail-to-rail values. Larger signal levels
correspond to better noise performance because the noise per-
formance of a system is expressed by using signal-to-noise-ratio
(SNR) values instead of the absolute noise power values. These Fig. 3. Frequency–voltage characteristics of (a) the three- and (b) the nine-
imply that the best characteristics are obtained with a full-rail stage ring oscillator.
output signal.
A design that provides both of these characteristics is the sat-
trolled by altering the strength of the latch using the control ter-
urated gain stage with regenerative cross-coupled PMOS tran-
minal that is connected to the NMOS switches M3 and
sistors as shown in Fig. 2 [5]. This provides for rail-to-rail output
M4. Higher control voltages result in a stronger coupling be-
signals and full switching of the FETs in the stage. From a qual-
tween M1 and M2, making it more difficult to switch the output
itative viewpoint, it can be seen that the feedback properties of
voltage, and hence decreasing the frequency. Hwang [9] uses a
the latching transistors M1 and M2 speed up the signal transi-
similar method to control the VCO frequency. Two pairs of in-
tions at the output. This improves both the oscillation frequency
puts are used to adapt the stage to a multiple-pass architecture.
and the noise performance of the VCO. The stage also avoids
To ease the requirements on the needed testing equipment,
the use of cascode connections and a tail current-source tran-
high-speed current-mode-logic (CML) buffers and frequency
sistor that would limit the signal swing and add more noise to
dividers were used to divide the frequency of the oscillators
the output.
from 1/2 to 1/64 of their actual value. The output of the divider
circuits is then fed to a high-speed driver chain to the output
III. PROTOTYPE OSCILLATOR DESIGNS pads for measurement.
A primary goal of the research was to explore the maximum The performance of the three-stage multiple-pass design
frequency limitations and noise performance levels of ring was simulated and measured with the results given in Fig. 3(a).
VCOs built in a standard CMOS process. To this end, three- Spectre simulations of the oscillator predicted an operation
and nine-stage multiple-pass ring oscillators were designed range of 5.18–6.11 GHz for control voltages of 0.3–1.8 V. The
and fabricated using a non-epi TSMC 0.18- m CMOS process measured silicon output was from 5.16 GHz up to 5.93 GHz,
with a power supply value of V. The circuits were indicating a maximum difference of 3.7% with the simulations.
designed with MOSIS SCMOS rules that required a minimum The peaking of the simulated characteristics is attributed to
drawn channel length of 0.20 m. The test chip also included the limitations of the simulator tool in the subthreshold region.
other circuits such as an integrated LC oscillator, charge pump Removing test circuitry and reducing the drawn channel length
prototypes, and phase-frequency detector networks, but these to 0.18 m predicts a maximum oscillation frequency of
are not discussed in this brief. 7.7 GHz as shown in the plot.
The prototype oscillators employ the saturated stage design The nine-stage multiple-pass ring oscillator employed the
given in Fig. 2 with the transistor ratios provided on the figure. same gain stage as that used in the three-stage design. The fre-
The delay of the stage, and thus, the VCO frequency, is con- quency–voltage curves shown in Fig. 3(b) were extracted from
232 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 39, NO. 1, JANUARY 2004

Fig. 5. Maximum frequencies versus minimum channel length.

Fig. 4. (a) Phase noise of the three- and nine-stage ring oscillators extracted
from Spectre RF simulations. (b) Power spectrum at the divide-by-two output
of the nine-stage oscillator. Fig. 6. Phase noise versus minimum channel length.

simulations and measurements and show good agreement with the thermal energy, is the power supply voltage, and is the
a maximum difference of 4%. When the control voltages were equivalent output resistance of a delay cell. Using this equation,
varied between 0.3 and 1.8 V, the measured and the simulated the phase noise of the three- and nine-stage multiple-pass ring
frequency ranges were 1.1–1.86 GHz and 1.16–1.93 GHz, oscillators was calculated to be 95.05 dBc/Hz and 120.99
respectively. It should be noted that the frequency range of dBc/Hz, respectively, at the same offset and center frequencies
a multiple-pass architecture does not scale linearly with the as given in the simulation results. The large difference for the
number of stages. nine-stage design is accounted to the additional noise sources
The phase noise values were estimated using SpectreRF because of the increase in the number of stages. This could
simulations and the published techniques that apply to this type of be compensated by using a larger excess noise factor in the
stage design. As illustrated in Fig. 4(a), simulations predicted the equations.
phase noise of the three-stage design as 99.5 dBc/Hz at a 1-MHz Fig. 4(b) shows the measured power spectrum at the di-
offset from a 5.79-GHz center frequency, whereas the value for vide-by-two output of the nine-stage design. The phase noise
the nine-stage design was 112.84 dBc/Hz at a 1-MHz offset of the nine-stage design was extracted as 105.5 dBc/Hz at
from a 1.82-GHz center frequency. Simulations also showed that a 1-MHz offset from a 1.81-GHz center frequency; this value
the dividers and buffers have negligible contribution to the output accounts for the bandwidth of the input low-pass filter of
phase noise. Dai’s equation [10] gives the single-sideband phase the spectrum analyzer and the division factor. Supply/ground
noise for oscillators with clipped signals as disturbances and flicker noise sources, which were ignored in
the calculations and simulations, are considered to be the main
sources of the difference between the measurements and the
estimations.
In an effort to compare the oscillators’ performance, two
scatter plots were created using designs published in the open
literature. Fig. 5 shows the maximum oscillator frequency as
where (2) a function of the minimum CMOS feature size, and Fig. 6
provides information on the phase noise. The points were
where is the single-sideband phase noise, is the excess measured, calculated/simulated, or taken from the referenced
noise factor, is the maximum output slew rate, is the papers. To provide consistency in the comparison, phase noise
angular frequency offset from the center frequency is data from the papers were scaled to a 1-MHz offset from the
IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 39, NO. 1, JANUARY 2004 233

center frequencies with an assumed 20-dB/decade drop. The REFERENCES

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