APL5606

Low Dropout 600mA Linear Regulator for DC Fan Control

Features General Description

• Low Dropout Voltage: 220mV (typical) @ 600mA The APL5606 is a low quiescent current, low dropout
• Low Quiescent Current: 140µA linear regulator which is designed with a P-channel pass
MOSFET to power a DC fan and delivers output current
• Selectable Adjustable/Full Speed Mode
up to 600mA. In adjustable mode, the output voltage fol-
• O/I Voltage Ratio in Adjustable Mode : 1.6 times lows the 1.6 times of the voltage on VSET pin to dynami-
• Stable with Low ESR Ceramic Capacitors cally adjust the DC fan speed; in full speed mode, the
• Over-Temperature Protection internal P-channel MOSFET fully turns on to drive the DC
• Current Limit Protection with Foldback Current fan with maximum supply voltage for full speed operation.
The APL5606 with low 140µA quiescent current is ideal
• Internal Soft-start
for battery-powered system appliances. It is also stable
• SOP-8 Package
with a low-ESR ceramic output capacitor (2.2µF typical)
• Lead Free Available (RoHS Compliant) to reduce total cost and minimize the PCB area required.
The APL5606 features current limit (with foldback current)
and over-temperature protections to protect the device
Simplified Application Circuit against current over-loads and over temperature. The
APL5606 is available in a SOP-8 package.

VOUT
VIN
VIN VOUT
C1 C2
2.2µF
Applications
1µF APL5606
Adjustable mode
• Notebook Fan Driver
FSM VSET
Full speed mode
GND Speed control
voltage (VSET) • Motherboards
• PC Peripherals
• Battery-Powered System

Ordering and Marking Information

APL5606 Package Code

K : SOP-8
Lead Free Code Operating Ambient Temperature Range
Handling Code I : -40 to 85 °C
Handling Code
Temperature Range TR : Tape & Reel
Lead Free Code
Package Code L : Lead Free Device

APL5606
APL5606 K : XXXXX - Date Code
XXXXX

Note: ANPEC lead-free products contain molding compounds/die attach materials and 100% matte tin plate termination finish; which are fully
compliant with RoHS and compatible with both SnPb and lead-free soldering operations. ANPEC lead-free products meet or exceed the lead-
free requirements of IPC/JEDEC J STD-020C for MSL classification at lead-free peak reflow temperature.

ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and
advise customers to obtain the latest version of relevant information to verify before placing orders.

Copyright  ANPEC Electronics Corp. 1 www.anpec.com.tw

Rev. A.2 - Jan., 2008
APL5606

Pin Configuration

SOP-8 Top View

FSM 1 8 GND
VIN 2 7 GND
VOUT 3 6 GND
VSET 4 5 GND

APL5606

Absolute Maximum Ratings (Note 1)

Symbol Parameter Rating Unit

VIN VIN to GND -0.3 ~ 6.5 V
VFSM FSM to GND -0.3 ~ VIN+0.3 V
VOUT VOUT to GND -0.3 ~ VIN+0.3 V
o
TJ Maximum Junction Temperature 150 C
PD Power Dissipation Internally Limited
o
TSTG Storage Temperature Range -65 ~ 150 C
o
TL Lead Temperature (Soldering, 10 sec) 260 C
Note 1: Stresses beyond the absolute maximum rating may damage the device and exposure to absolute maximum rating conditions for extended
periods may affect device reliability.

Thermal Characteristics
Symbol Parameter Rating Unit
Junction to Ambient Thermal Resistance
θJA 80 °C/W
SOP-8

Note 2: θJA is measured with the component mounted on a high effective thermal conductivity test board in free air.

Recommended Operating Conditions

Symbol Parameter Range Unit
VIN VIN to GND 4.5 ~ 6 V
VFSM FSM to GND 0 ~ VIN V
VOUT VOUT to GND 0 ~ VIN-VDROP V
VSET VSET to GND 0 ~ 3.3 V
IOUT Output Current 0 ~ 0.6 A
CIN Input Capacitor 0.82 ~ 470 µF
COUT Output Capacitor 1 ~ 330 µF
TJ Junction Temperature -40 ~ 125 °C
TA Ambient Temperature -40 ~ 85 °C

Copyright  ANPEC Electronics Corp. 2 www.anpec.com.tw

Rev. A.2 - Jan., 2008
 APL5606

Electrical Characteristics
Refer to the typical application circuit. VIN = 5V, VFSM = VIN, IOUT = 1mA~600mA, TJ = -40 to 125 °C, TA = -40 to 85°C,
unless otherwise specified. Typical values are at TA = 25 °C.

Symbol Parameter Test Conditions Min Typ Max Unit

SUPPLY CURRENT
VFSM = 0V - - 1 µA
IQ Quiescent Current
VFSM = 5V, IOUT = 0A - 140 200 µA
UNDER-VOLTAGE-LOCKOUT (UVLO)
VIN UVLO Threshold VIN rising 2.1 2.5 2.9 V
VIN UVLO Hysteresis - 0.15 - V
OUTPUT VOLTAGE
TJ = 25°C, VIN=5.5V, IOUT=1mA,
VOUT Voltage / VSET Voltage 1.552 1.6 1.648 V/V
VSET=3.3V
TJ = 40 ~ 125°C, VIN=5.5V, IOUT=1mA,
VOUT Voltage / VSET Voltage 1.504 1.6 1.696 V/V
VSET=1 ~ 3.3V
VSET pin Current VSET=5V - 0.05 1 µA
Line Regulation VIN = VOUT + 1V to 6V - 0.03 0.1 %/V
Load Regulation IOUT = 1mA to 600mA - 60 100 mV
IOUT = 600mA, VOUT=2.5V - 250 400 mV
VDROP Dropout Voltage IOUT = 600mA, VOUT=3.3V - 220 350 mV
IOUT = 600mA, VOUT=5V - 200 320 mV
PROTECTION and SOFT-START
ILIM Output Current Limit 700 - - mA
Thermal Shutdown Temperature - 150 - °C
Thermal Shutdown Hysteresis - 40 - °C
Foldback Current Limit VOUT < 0.6V - 250 - mA
TSS Soft-Start Time - 130 300 µs
VOUT Pull Low Resistance VFSM =0V, VOUT=0.5V - 60 - Ω
LOGIC INPUT
FSM Logic Input-High Level 1.6 - - V
FSM Logic Input-Low Level - - 0.4 V
FSM Pull-Low Resistance VFSM <3V - 2 - MΩ

Copyright  ANPEC Electronics Corp. 3 www.anpec.com.tw

Rev. A.2 - Jan., 2008
 APL5606

Typical Operating Characteristics

VIN=5V, VSET=2V, VOUT=3.2V, CIN=1µF, COUT=2.2µF, unless otherwise specified

FSM Voltage Threshold vs.

Quiescent Current vs. VSET Voltage
Input Voltage 180
1.6

160
1.5
IOUT=0mA
FSM Voltage Threshold (V)

Quiescent Current, IQ (μA)

140
1.4
120
1.3
100
1.2
80
1.1
60

1 40

0.9 20

0.8 0
3 3.5 4 4.5 5 5.5 6 6.5 0 0.5 1 1.5 2 2.5 3
Input Voltage (V) VSET Voltage (V)

VSET Voltage vs. Output Voltage Dropout vs. Junction Temperature

6 300
VOUT=5V
IOUT=10mA
5 250
In Adjustable Mode IOUT=600mA
Output Voltage (V)

Dropout Voltage (mV)

4 200

IOUT=400mA
3 150

2
IOUT=200mA
100

1 50

0 0
0 0.5 1 1.5 2 2.5 3 3.5 -50 0 50 100 150
VSET Voltage (V) Junction Temperature, TJ (°
C)

Dropout vs. Junction Temperature Power Supply Rejection Ratio

(PSRR)
350 0

VOUT=3.3V VIN=5, CIN=1µF, COUT=2.2µF,

-5
300 VSET=2V, VOUT=3.2V
-10
IOUT=600mA
Dropout Voltage (mV)

250 -15
PSRR (dB)

-20 IOUT=500mA
200
IOUT=400mA
-25
150
-30
IOUT=200mA
100 -35 IOUT=400mA

-40
50
-45

0 -50
-50 0 50 100 150 1000 10000 100000 1000000
Junction Temperature, TJ (°
C)
Frequency (Hz)

Copyright  ANPEC Electronics Corp. 4 www.anpec.com.tw

Rev. A.2 - Jan., 2008
 APL5606

Typical Operating Characteristics (Cont.)

VIN=5V, VSET=2V, VOUT=3.2V, CIN=1µF, COUT=2.2µF, unless otherwise specified

Quiescent Current vs. Input Voltage

200

IOUT=0mA
Quiescent Current (µA)

160

120

80

40

0
0 1 2 3 4 5 6
Input Voltage, VIN (V)

Operating Waveforms
VIN=5V, VSET=2V, VOUT=3.2V, CIN=1µF, COUT=2.2µF, unless otherwise specified

Power On Power Off

V SET
V IN

V IN
1 1 V OUT
V SET
2 2

I OUT V OUT
V OUT
3 3
I OUT
I OUT
4 4

CH1 : VIN , 2V/div CH1 : VIN , 2V/div

CH2 : VSET , 1V/div CH2 : VSET , 1V/div
CH3 : VOUT , 1V/div CH3 : VOUT , 1V/div
CH4 : IOUT , 500mA/div CH4 : IOUT , 500mA/div
Time : 1ms/div Time : 200ms/div

Copyright  ANPEC Electronics Corp. 5 www.anpec.com.tw

Rev. A.2 - Jan., 2008
 APL5606

Operating Waveforms (Cont.)

VIN=5V, VSET=2V, VOUT=3.2V, CIN=1µF, COUT=2.2µF, unless otherwise specified

Load Transient Line Transient

VIN=5V~6V~5V, VSET=2V ,
VIN=5V, VSET=2V , VOUT=3.2V VOUT=3.2V, CIN=1µF,
CIN=1µF, COUT=2.2µF COUT=2.2µF
1 V OUT
1 V IN

I OUT
2

V OUT

CH1 : VOUT , 100mV/div CH1 : VIN , 1V/div

CH2 : IOUT , 200mV/div CH2 : VOUT , 100mV/div
Time : 200µs/div Time : 1ms/div

Current Limit and Short Circuit

Thermal Shutdown Current Limit

VIN VIN
1 VOUT
1

2 VOUT

2
IOUT
IOUT

3 3

CH1 : VIN , 5V/div CH1 : VIN , 5V/div

CH2 : VOUT , 2V/div CH2 : VOUT , 2V/div
CH3 : IOUT , 500mA/div CH3 : IOUT , 1A/div
Time : 500ms/div Time : 2ms/div

Copyright  ANPEC Electronics Corp. 6 www.anpec.com.tw

Rev. A.2 - Jan., 2008
APL5606

Pin Descriptions
Pin
Function Descriptions
No. Name
Adjustable/Full Speed Mode Selection Input Pin. Output voltage follows 1.6 times of the voltage
1 FSM on VSET pin. If the FSM is at low level, the IC operates in full speed mode with the P-channel
MOSFET fully turned on. The FSM pin is pulled low by an internal resistor.
Supply Voltage Input Pin. Supply voltage can range from 4.5V to 6V. Bypass with a 1µF (typical)
2 VIN
capacitor to GND
Regulator Output. Sources up to 600mA. A small capacitor is needed and connected from this pin
3 VOUT
to ground to assure stability.
4 VSET Output Voltage-Set Input. The output voltage follows the 1.6 times of the VSET voltage.

Ground. These pins are internally connected with the internal leadframe. Connect these pins to a
5,6,7,8 GND
wide ground plane for good heat dissipation.

Block Diagram

VIN

Current Limit and

Foldback Current
Limit

UVLO and
FSM Soft-Start

VSET
VOUT
Thermal
Shutdown
0.6R

GND

Typical Application Circuit

APL5606
VIN VSET
VIN VSET
CIN
VOUT
1µF FSM VOUT
GND COUT
Adjustable mode 2.2µF
VFSM

Full speed mode

Copyright  ANPEC Electronics Corp. 7 www.anpec.com.tw

Rev. A.2 - Jan., 2008
 APL5606

Function Descriptions
Under-Voltage Lock-Out (UVLO) Thermal Shutdown

The APL5606 has a built-in under-voltage lock-out circuit A thermal shutdown circuit limits the junction temperature
to keep the output off until the internal circuitry is operat- of APL5606. When the junction temperature exceeds
ing properly. The UVLO function initiates a soft start pro- +150 ο C, the thermal shutdown circuitry disables the
cess after input voltage exceeds its rising UVLO thresh- output, allowing the device to cool down. The output
old during power on. Typical UVLO threshold is 2.5V with circuitry is enabled again after the junction tempera-
0.15V hysteresis. ture cools down by 40 ο C, resulting in a pulsed output
during continuous thermal overload conditions. The ther-
Soft-Start
mal protection is designed to protect the IC in the event
The APL5606 provides an internal soft-start circuitry to
of over temperature conditions. For reliable operation,
control rise rate of the output voltage and limit the cur-
the junction temperature cannot exceed TJ=+125οC.
rent surge during start-up. Approximate 20µs delay time
after the VIN is over the UVLO threshold, the IC starts a
soft-start. The typical soft-start interval is about 130µs.

Adjustable/Full Speed Mode Selection

The APL5606 features an input pin to select one of the

operation modes for DC fan speed control. In adjustable
mode, the output voltage follows the 1.6 times of the volt-
age on VSET pin to dynamically adjust the DC fan speed;
in full speed mode, the internal P-channel MOSFET fully
turns on to drive the DC fan with maximum supply voltage
(VIN-VDROP) for full speed operation. Driving the FSM volt-
age at high level(VFSM>1.6V) sets the IC to operate in ad-
justable mode; driving the FSM at low level(VFSM<0.4V)
sets the IC to operate in full speed mode. The FSM is
pulled low by an internal resistor.

Current Limit
The APL5606 provides a current limit circuitry, which
monitors the output current and controls P-MOS’s gate
voltage to limit the output current at 700mA (min.).

Foldback Current Limit

When the output voltage drops below 0.6V (typical), which
is caused by over load or short circuit, the foldback cur-
rent limit circuitry limits the output current to 250mA. The
foldback circuit current limit is used to reduce the power
dissipation during short circuit condition. The foldback
current limit is disabled for 0.6ms (typical) after the UVLO
threshold is reached, so that the IC has normal 700mA
(min.) current limit level during start-up.

Copyright  ANPEC Electronics Corp. 8 www.anpec.com.tw

Rev. A.2 - Jan., 2008
APL5606

Application Information
Input Capacitor PCB Layout Considerations
The APL5606 requires proper input capacitors to supply Figure 1 illustrates the layout. Below is a checklist for
surge current during stepping load transients to prevent your layout:
the input rail from dropping. Because the parasitic induc- 1. Please place the input capacitors close to the VIN
tor from the voltage sources or other bulk capacitors to 2. Ceramic capacitors for load must be placed near the
the VIN limits the slew rate of the surge current, place the load as close as possible
Input capacitors near VIN as close as possible. The in- 3. To place APL5606 and output capacitors near the load
put capacitors should be larger than 0.82µF. is good for performance.
4. Large current paths, the bold lines in figure 1, must
Output Capacitor have wide tracks.
APL5606
The APL5606 needs a proper output capacitor to main- VIN
tain circuit stability and to improve transient response VIN VSET VSET
over temperature and current. In order to insure the cir- CIN
cuit stability, the proper output capacitor value should be
VOUT
larger than 1µF. With X5R and X7R dielectrics, 2.2µF is FSM VOUT
sufficient at all operating temperatures. VFSM GND COUT

Operation Region and Power dissipation

The APL5606 maximum power dissipation depends on Figure 1

the thermal resistance and temperature difference be- Optimum performance can only be achieved when the
tween the die junction and ambient air. The power dissi- device is mounted on a PC board according to the SOP-8
pation PD across the device is: Board Layout diagram.
( TJ − TA ) For dissipating heat
PD =
θJA
GND
where (TJ-TA) is the temperature difference between the
junction and ambient air. θ JA is the thermal resistance SOP-8 COUT

between Junction and ambient air. Assuming the TA=25οC

and maximum TJ=150ο C (typical thermal limit threshold),
the maximum power dissipation is calculated as: VIN VOUT
CIN
PD(max)=(150-25)/80 GND
= 1.56 (W)
Figure 2
For normal operation, do not exceed the maximum junc-
tion temperature of TJ = 125 ο C. The calculated power Recommanded Minimum Footprint
0.024
dissipation should less than:
8 7 6 5
0.072

PD =(125-25)/80
= 1.25 (W)
0.212

1 2 3 4
0.050 Unit : Inch

Copyright  ANPEC Electronics Corp. 9 www.anpec.com.tw

Rev. A.2 - Jan., 2008
APL5606

Package Information
SOP-8
D

SEE VIEW A

E1

h X 45

e b c
A2

0.25
A

GAUGE PLANE
SEATING PLANE
A1

L
VIEW A

S SOP-8
Y
M MILLIMETERS INCHES
B
O
L MIN. MAX. MIN. MAX.

A 1.75 0.069
A1 0.10 0.25 0.004 0.010
A2 1.25 0.049
b 0.31 0.51 0.012 0.020
c 0.17 0.25 0.007 0.010
D 4.90 BSC 0.193 BSC
E 6.00 BSC 0.236 BSC
E1 3.90 BSC 0.154 BSC
e 1.27 BSC 0.050 BSC
h 0.25 0.50 0.010 0.020
L 0.40 1.27 0.016 0.050
0 0° 8° 0° 8°

Note: 1. Followed JEDEC MS-012 AA.

2. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion or gate burrs shall not exceed 6 mil per side.
3. Dimension “E” does not include inter-lead flash or protrusions.
Inter-lead flash and protrusions shall not exceed 10 mil per side.

Copyright  ANPEC Electronics Corp. 10 www.anpec.com.tw

Rev. A.2 - Jan., 2008
APL5606

Carrier Tape & Reel Dimensions

OD0 P0 P2 P1 A

E1
F

W
B0

K0 A0 OD1 A
B B
SECTION A-A

T
SECTION B-B

d
H
A

T1

Application A H
T1 C d D W E1 F
12.4+2.00 13.0+0.50
330.0±2.00 50 MIN. 1.5 MIN. 20.2 MIN. 12.0±0.30 1.75±0.10 5.5±0.05
-0.00 -0.20
SOP-8 P0 P1 P2 D0 D1 T A0 B0 K0
1.5+0.10 0.6+0.00
4.0±0.10 8.0±0.10 2.0±0.05 1.5 MIN. 6.40±0.20 5.20±0.20 2.10±0.20
-0.00 -0.40
(mm)

Devices Per Unit

Package Type Unit Quantity

SOP-8 Tape & Reel 2500

Copyright  ANPEC Electronics Corp. 11 www.anpec.com.tw

Rev. A.2 - Jan., 2008
 APL5606

Reflow Condition (IR/Convection or VPR Reflow)

TP tp
Critical Zone
TL to TP
Ramp-up

TL
tL
Temperature

Tsmax

Tsmin
Ramp-down
ts
Preheat

25
t 25°C to Peak

Time
Reliability Test Program
Test item Method Description
SOLDERABILITY MIL-STD-883D-2003 245°C, 5 sec
HOLT MIL-STD-883D-1005.7 1000 Hrs Bias @125°C
PCT JESD-22-B, A102 168 Hrs, 100%RH, 121°C
TST MIL-STD-883D-1011.9 -65°C~150°C, 200 Cycles
ESD MIL-STD-883D-3015.7 VHBM > 2KV, VMM > 200V
Latch-Up JESD 78 10ms, 1tr > 100mA

Classification Reflow Profiles

Profile Feature Sn-Pb Eutectic Assembly Pb-Free Assembly
Average ramp-up rate
3°C/second max. 3°C/second max.
(TL to TP)
Preheat
100°C 150°C
- Temperature Min (Tsmin)
150°C 200°C
- Temperature Max (Tsmax)
60-120 seconds 60-180 seconds
- Time (min to max) (ts)
Time maintained above:
183°C 217°C
- Temperature (TL)
60-150 seconds 60-150 seconds
- Time (tL)
Peak/Classification Temperature (Tp) See table 1 See table 2
Time within 5°C of actual
10-30 seconds 20-40 seconds
Peak Temperature (tp)
Ramp-down Rate 6°C/second max. 6°C/second max.
Time 25°C to Peak Temperature 6 minutes max. 8 minutes max.

Note: All temperatures refer to topside of the package. Measured on the body surface.

Copyright  ANPEC Electronics Corp. 12 www.anpec.com.tw

Rev. A.2 - Jan., 2008
APL5606

Classification Reflow Profiles (Cont.)

Table 1. SnPb Eutectic Process – Package Peak Reflow Temperatures
3 3
Volume mm Volume mm
Package Thickness
<350 ≥350
<2.5 mm 240 +0/-5°C 225 +0/-5°C
≥2.5 mm 225 +0/-5°C 225 +0/-5°C
Table 2. Pb-free Process – Package Classification Reflow Temperatures
3 3 3
Volume mm Volume mm Volume mm
Package Thickness
<350 350-2000 >2000
<1.6 mm 260 +0°C* 260 +0°C* 260 +0°C*
1.6 mm – 2.5 mm 260 +0°C* 250 +0°C* 245 +0°C*
≥2.5 mm 250 +0°C* 245 +0°C* 245 +0°C*
* Tolerance: The device manufacturer/supplier shall assure process compatibility up to and including the stated
classification temperature (this means Peak reflow temperature +0°C. For example 260°C+0°C) at the rated MSL
level.

Customer Service
Anpec Electronics Corp.
Head Office :
No.6, Dusing 1st Road, SBIP,
Hsin-Chu, Taiwan, R.O.C.
Tel : 886-3-5642000
Fax : 886-3-5642050

Taipei Branch :
2F, No. 11, Lane 218, Sec 2 Jhongsing Rd.,
Sindian City, Taipei County 23146, Taiwan
Tel : 886-2-2910-3838
Fax : 886-2-2917-3838

Copyright  ANPEC Electronics Corp. 13 www.anpec.com.tw

Rev. A.2 - Jan., 2008