uP1513

5V/12V Synchronous-Rectified Buck Controller

General Description Features
The uP1513 is a compact synchronous-rectified buck † Operate from 5V or 12V Supply Voltage
controller specifically designed to operate from 5V or 12V „ 3.3V to 12V VIN Input Range
supply voltage and to deliver high quality output voltage „ 0.6V VREF with 1.0% Accuracy
as low as 0.6V. This 8-pin device operates at fixed 300kHz
„ Output Range from VREF to 80% of VIN
frequency and provides an optimal level of integration to
reduce size and cost of the power supply. † Support Tracking Mode and Stand Alone Mode
Operation
The uP1513 supports both tracking mode and stand-alone
mode operation. The output voltage is tightly regulated to † Simple Voltage-Mode PWM Control Design
the external reference voltage from 0.4V to 3.0V at tracking „ 300 kHz Fixed Frequency Oscillator
mode or to internal 0.6V reference at stand-alone mode. „ Internal Compensation
The uP1513 integrates MOSFET drivers that support „ Fast Transient Response
12V+12V bootstrapped voltage for high efficiency power „ 0% to 80% Duty Cycle
conversion. The bootstrap diode is built-in to simplify the
† Internal Bootstrapped Gate Drivers
circuit design and minimize external part count.
„ Integrated Bootstrap Diode
The uP1513 supports diode emulation mode operation
„ Adaptive Shoot-Through Protection
that yields high efficiency over all the output current range.
Besides, an OCP/EN is used for chip disable and „ Upper MOSFET Short-Circuit Protection
continuous setting of over current protection level. † Lossless, Programmable Overcurrent Protection
Other features include under voltage lockout (UVLO), „ Uses Lower MOSFET RDS(ON)
internal softstart. With aforementioned functions, this part † Support Diode Emulation Mode Operation
provides customers a compact, high efficiency, well- † Internal Soft Start
protected and cost-effective solutions. This part is available
† RoHS Compliant and Halogen Free
in PSOP-8 package.

Applications Pin Configuration

† Power Supplies for Microprocessors or

BOOT 1 8 PH
Subsystem Power Supplies
† Cable Modems, Set Top Boxes, and xDSL UG 2 7 OCP/EN
9
Modems GND
REFIN 3 6 FB
† Industrial Power Supplies; General Purpose
Supplies LG 4 5 VCC
† 5V or 12V Input DC-DC Regulators
PSOP-8
† Low Voltage Distributed Power Supplies

Ordering Information
Order Number Package Type Remark Top Marking
uP1513PSU8 PSOP-8 With PSM uP1513P

Note: uPI products are compatible with the current IPC/

JEDEC J-STD-020 requirement. They are halogen-free,
RoHS compliant and 100% matte tin (Sn) plating that are
suitable for use in SnPb or Pb-free soldering processes.

uPI Semiconductor Corp., http://www.upi-semi.com 1

Rev. P00, File Name: uP1513-DS-P0000
 uP1513
Typical Application Circuit
5V/12V

VIN
VCC BOOT
5 1 3.3V/5V/12V

Reference REFIN UG
3 2

uP1513
Input
PH VOUT
8
GND OCP/EN
9 7

FB LG
6 4

Functional Pin Description

N o. Pin Name Pin Function
B ootstrap Supply for the upper gate dri ver. C onnect the bootstrap capaci tor C BOOT between
1 BOOT BOOT and PH pins to form a bootstrap circuit. The bootstrap capacitor provides the charge to
turn on the upper MOSFET.
Upper Gate Driver Output. Connect this pin to the gate of upper MOSFET. This pin is monitored
2 UG by the adaptive shoot-through protection circuitry to determine when the upper MOSFET has turned
off.
External Reference Input for Tracking Mode Operation. This pin receives a voltage with range
from 0.4V to 3.0V as the reference voltage at the non-inverting input of the error amplifier. Pulling
3 REFIN
this pin lower than 0.3V disables the controller and causes the oscillator to stop, the UGATE and
LGATE outputs to be held low. Let this pin open for internal 0.6V reference use.
Low er Gate Driver Output. Connect this pin to the gate of lower MOSFET. This pin is monitored
4 LG by the adaptive shoot-through protection circuitry to determine when the lower MOSFET has turn
off.
Supply Voltage. This pin provides the bias supply for the uP1513 and the lower gate driver. The
5 VC C supply voltage is internally regulated to 4VDD for internal control circuit. Connect a well-decoupled
4.5V to 13.2V supply voltage to this pin. Ensure that a decoupling capacitor is placed near the IC.
Feedback Voltage. This pin is the inverting input to the error amplifier. A resistor divider from the
6 FB
output to GND is used to set the regulation voltage.
OCP Setting and Chip Enable. Connect a resistor to PH pin to set the OCP level. Pulling this
7 OCP/EN
pin lower than 0.2V turns off the uP1513.
PHASE Sw itch Node. Connect this pin to the source of the upper MOSFET and the drain of the
8 PH lower MOSFET. This pin is used as the sink for the UG drive and is monitored by the adaptive
shoot-through protection circuitry to determine when the upper MOSFET has turned off.
Ground. The exposed pad should be well soldered to ground plane/island with lowest impedance
Exposed Pad
for best thermal performance.

uPI Semiconductor Corp., http://www.upi-semi.com 2

Rev. P00, File Name: uP1513-DS-P0000
 uP1513
Functional Block Diagram
VCC

BOOT
Soft Start
& POR
Fault Logic
4VDD Internal UG
Regulator
Oscillator

SS Gate
PWM
Control PH
FB Logic
Error
VCC
VREF Amplifier

Reference
LG
Selection

GND

0.6V 4VDD

0.4V
OCP

0.2V
REFIN Enable
0.3V
OCP/EN

uPI Semiconductor Corp., http://www.upi-semi.com 3

Rev. P00, File Name: uP1513-DS-P0000
 uP1513
Functional Description
The uP1513 is a compact synchronous-rectified buck state and is ready to accept chip enable command. The
controller specifically designed to operate from 5V or 12V rising POR threshold is typically 4.2V at VCC rising.
supply voltage and to deliver high quality output voltage The OCP/EN is a multi-functional pin: OCP level setting
as low as 0.8V. This 8-pin device operates at fixed 300kHz and chip enable. Pulling this pin by a small-signal transistor
frequency and provides an optimal level of integration to lower than 0.2V turns off the uP1513 as shown in the
reduce size and cost of the power supply. Typical Application Circuit. (Please refer to related sections
The uP1513 integrates MOSFET drivers that support for OCP setting.)
12V+12V bootstrapped voltage for high efficiency power When released, an internal 40uA flows through the external
conversion. The bootstrap diode is built-in to simplify the circuit and pulls the VOCP/EN high. The uP1513 is enabled if
circuit design and minimize external part count. the VOCP/EN is higher than 0.2V. Make sure VOCP/EN is always
The uP1513 supports diode emulation mode operation higher than 0.2V during normal operation.
that yields high efficiency over all the output current range. Tracking Mode and Stand Alone Mode Operation
Besides, an OCP/EN is used for chip disable and
continuous setting of over current protection level. The REFIN is a multifunctional pin: external reference
input and chip enable as shown in Figure 1. To Select
Other features include under voltage lockout (UVLO), Internal 0.6V Reference Voltage, just let the REFIN open.
internal softstart, under voltage protection, over voltage A 30uA current source tries to pull high the REFIN voltage
protection. With aforementioned functions, this part after POR that is monitored by the Enable Comparator
provides customers a compact, high efficiency, well- monitors for chip enable. A signal level transistor is
protected and cost-effective solutions. This part is available adequate to pull this pin down to ground and shut down
in SOP-8 or PSOP-8 packages. the uP1513. As the REFIN voltage acrosses 0.3V threshold
Supply Voltage level, the Enable Comparator initiates the operation of the
The VCC pin receives a well-decoupled 4.5V to 13.2V uP1513. The REFIN voltage is compared with 3.0V
supply voltage to power the uP1513 control circuit, the voltage to select the reference voltage with 1ms time delay
lower gate driver and the bootstrap circuit for the higher after chip enabling. The internal 0.6V reference voltage is
gate driver. A minimum 0.1uF ceramic capacitor is selected as the REFIN pulled high to internal 4VDD. The
recommended to bypass the supply voltage. Place the softstart cycle is initiated after reference selection is
bypassing capacitor physically near the IC. completed.

An internal linear regulator regulates supply voltage into To Select External Reference Voltage, connect REFIN
a 4.0V voltage 4VDD for internal control logic circuit. No to a voltage source range from 0.4V to 3V. As the REFIN
external bypass capacitor is required for filtering the 4VDD voltage acrosses 0.3V threshold level, the Enable
voltage. Comparator initiates the operation of the uP1513. The
REFIN voltage is compared with 3.0V voltage to select
The uP1513 integrates MOSFET gate drives that are the reference voltage with 1ms time delay after chip
powered from the VCC pin and support 12V+12V driving enabling. The external reference input is selected as the
capability. A bootstrap diode is embedded to facilitate PCB REFIN voltage is lower than 3.0V. The 30uA current source
design and reduce the total BOM cost. No external is turn off if the external reference input is select to
Schottky diode is required. Converters that consist of eliminate the load effect on the reference input. The
uP1513 feature high efficiency without special softstart cycle is initiated after reference selection is
consideration on the selection of MOSFETs. completed.
Note: The embedded bootstrap diode is not a Schottky Note that the 30uA current source will induces load
diode having a 0.8V forward voltage. External effect on the external reference input and causes the
Schottky diode is highly recommended if the VCC REFIN voltage slightly higher than the external
voltage is expected to be lower than 5.0V. Otherwise reference input during the reference selection. Make
the bootstrap diode may be too low for the device to sure that the external reference input is strong enough
work normally. so that REFIN voltage will not be higher than 3.0V.
Power On Reset and Chip Enable
A power on reset (POR) circuitry continuously monitors
the supply voltage at VCC pin. Once the rising POR
threshold is exceeded, the uP1513 sets itself to active

uPI Semiconductor Corp., http://www.upi-semi.com 4

Rev. P00, File Name: uP1513-DS-P0000
 uP1513
Functional Description
Power Input Detection
uP1513
4VDD The uP1513 detects PH voltage for the present of power
Reference input when the UG turns on the first time. If the PH voltage
Voltage Reference
Selection
does not exceed 3.0V when the UG turns on, the uP1513
30uA
asserts that power input in not ready and stops the softstart
cycle. However, the internal SS continues ramping up to
VREF
(0.6V) 4VDD. Another softstart is initiated after SS ramps up to
Reference REFIN 4VDD. The hiccup period is about 3ms.
Input 3

3.0V

1ms
Chip Delay V IN
0.3V Enable 5V/Div

V OUT
Figure 1. Reference Selection Function 500mV/Div

Soft Start
A built-in Soft Start is used to prevent surge current from
power supply input during turn on (referring to the LGATE
10V/Div
Functional Block Diagram). The error amplifier is a three-
input device. Reference voltage VREF or the internal soft
start voltage SS whichever is smaller dominates the
behavior of the non-inverting inputs of the error amplifier. Time 4ms/ Div

SS internally ramps up to VDD with a fixed slew rate 1.5ms, Figure 3. Softstart where VIN does not Present Initially
no matter the VREF voltage. Overcurrent Protection (OCP)
The SS signal keeps ramping up after it exceeds the A resistor connected from OCP/EN to PH node programs
reference voltage VREF. However, the reference voltage the over current protection level as shown in Figure 2.
VREF takes over the behavior of error amplifier after SS > When the lower MOSFET turns on, the PH node voltage
VREF. When the SS signal climb to 1.6 x VREF, the uP1513 can be expressed as:
claims the end of softstart cycle, enables the under voltage
VPH = −IL × RDS(ON)
protection of the output voltage.
where IL is the inductor current and RDS(ON) is on-resistance
of lower MOSFET.

V IN
5V/Div 4VDD
40uA
V OUT 0.4V
500mV/Div OCP
OCP/EN PH

LGATE
10V/Div 10pF
IL
5A/Div

Figure 4. Over Current Protection

Time 1ms/ Div
Figure 2. Softstart Behavior of uP1513 Consequently, the stablized OCP/EN voltage VOCP/EN can
be expressed as:

VOCP / EN = 40uA × R OCSET − IL × RDS(ON)

The OCP is triggered and turns off the uP1513 if VOCP/EN

uPI Semiconductor Corp., http://www.upi-semi.com 5

Rev. P00, File Name: uP1513-DS-P0000
 uP1513
Functional Description
is lower than 0.4V with about 5us time delay. The OCP
level is calculated as:

40uA × R OCSET − 0.4 V

IL _ OCP =
RDS( ON)

Note that ROCSET and parasitic capacitance to OCP/EN pin

form a RC low-pass filter. Therefore, the OCP level is very
sensitive to the RC time constant. Select external
components so that external parasitic capacitance is lower
than 10pF for accurate OCP level setting.
When programming the OCP level, take into consideration
the conditions that affect RDS(ON) of the lower MOSFET,
including operation junction temperature, gate driving
voltage and distribution. Consider the RDS(ON) at maximum
operation temperature and lowest gate driving voltage.
Another factor should taken into consideration is the ripple
of the inductor current. The current near the valley of the
ripple current is used for OCP, resulting the averaged OCP
level a little higher than the calculated value.
Note: For application that uses unity feedback, no
voltage divider could sink the IOCSET.A minimum
load higher than 50uA is necessary to prevent
abnormal output voltage.
Diode Emulation Mode
The uP1513 supports diode emulation mode that yields
high efficiency at light load conditions.
The PH voltage is monitored for inductor zero current
detection when the lower MOSFET turns on. When zero
current crossing is detected, the uP1513 turns off lower
MOSFET and runs the converter as conventional
asynchronous buck converter, enabling discontinusous
conduction mode operation (DCM). The converter will
enter pulse skiping mode at extremely light load and yield
high effeciency over all the output load conditions.

uPI Semiconductor Corp., http://www.upi-semi.com 6

Rev. P00, File Name: uP1513-DS-P0000
 uP1513
Absolute Maximum Rating
Supply Input Voltage, VCC (Note 1) -------------------------------------------------------------------------------------- -0.3V to +15V
PH to GND
DC ---------------------------------------------------------------------------------------------------------------------------- -5V to 15V
< 200ns ------------------------------------------------------------------------------------------------------------------- -10V to 30V
BOOT to GND
DC -------------------------------------------------------------------------------------------------------------------- -0.3V to PH +15V
< 200ns ----------------------------------------------------------------------------------------------------------------- -0.3V to 42V
LG to GND
DC ---------------------------------------------------------------------------------------------------------------------------- -1V to 15V
< 200ns --------------------------------------------------------------------------------------------------------------------- -5V to 30V
UG to PH
DC ------------------------------------------------------------------------------------------------------------------------- -0.3V to 15V
< 200ns --------------------------------------------------------------------------------------------------------------------- -2V to 20V
Input, Output or I/O Voltage -------------------------------------------------------------------------------------------------- -0.3V to +6V
Storage Temperature Range ----------------------------------------------------------------------------------------------- -65OC to +150OC
Junction Temperature --------------------------------------------------------------------------------------------------------------------- 150OC
Lead Temperature (Soldering, 10 sec) ------------------------------------------------------------------------------------------------ 260OC
ESD Rating (Note 2)
HBM (Human Body Mode) -------------------------------------------------------------------------------------------------------- 2kV
MM (Machine Mode) ---------------------------------------------------------------------------------------------------------------- 200V

Thermal Information
Package Thermal Resistance (Note 3)
SOP-8 θJA -------------------------------------------------------------------------------------------------------------------- 160°C/W
PSOP-8 θJA ------------------------------------------------------------------------------------------------------------------- 50°C/W
SOP-8 θJC --------------------------------------------------------------------------------------------------------------------- 39°C/W
PSOP-8 θJC -------------------------------------------------------------------------------------------------------------------- 5°C/W
Power Dissipation, PD @ TA = 25°C
SOP-8 ------------------------------------------------------------------------------------------------------------------------------- 0.625W
PSOP-8 -------------------------------------------------------------------------------------------------------------------------------- 2.0W

Recommended Operation Conditions

Operating Junction Temperature Range (Note 4)--------------------------------------------------------------------- -40°C to +125°C
Operating Ambient Temperature Range ---------------------------------------------------------------------------------- -40°C to +85°C
Supply Input Voltage, VCC ----------------------------------------------------------------------------------------------------- +4.5V to 13.2V

Note 1. Stresses listed as the above “Absolute Maximum Ratings” may cause permanent damage to the device.
These are for stress ratings. Functional operation of the device at these or any other conditions beyond
those indicated in the operational sections of the specifications is not implied. Exposure to absolute
maximum rating conditions for extended periods may remain possibility to affect device reliability.
Note 2. Devices are ESD sensitive. Handling precaution recommended.
Note 3. θJA is measured in the natural convection at TA = 25°C on a low effective thermal conductivity test board of
JEDEC 51-3 thermal measurement standard.
Note 4. The device is not guaranteed to function outside its operating conditions.

uPI Semiconductor Corp., http://www.upi-semi.com 7

Rev. P00, File Name: uP1513-DS-P0000
 uP1513
Electrical Characteristics
(VCC = 12V, TA = 25OC, unless otherwise specified)

Parameter Symbol Test Conditions Min Typ Max Units

Supply Input
Supply Voltage VCC 4.5 -- 13.2 V
Supply Current ICC UG, LG Open; Switching -- 2 -- mA
Quiescent Supply Current ICC_Q VFB = 0.9V, No Switching -- 1.5 -- mA
Power Input Voltage VIN 3.0 -- 13.2 V
POR Threshold VCCRTH VCC rising 4.0 4.2 4.4 V
POR Hysteresis VCCHYS -- 0.5 -- V
Oscillator
Free Running Frequency fOSC 270 300 330 kHz
Ramp Amplitude ΔVOSC VIN = 12V, VOUT = 1.2V -- 3.0 -- VP-P
Maximum Duty Cycle 80 -- -- %
Minimum On Time -- 200 -- ns
Reference Voltage
Nominal Feedback Voltage VFB Stand Alone Mode 0.591 0.6 0.609 V
| VFB - VREFIN |, VREFIN = 0.4V ~ 1.0V,
-- -- 15 mV
Tracking Mode
Output Voltage Accuracy
| VFB - VREFIN | / VREFIN, VREFIN = 1.0V ~
-- -- 1.5 %
3.0V, Tracking Mode
REFIN Enable Threshold VREFIN -- 0.3 0.35 V
Error Amplifier
Open Loop DC Gain AO Guaranteed by Design 55 70 -- dB
Gain-Bandwidth Product GBW Guaranteed by Design -- 10 -- MHz
Slew Rate SR Guaranteed by Design 3 6 -- V/us
Transconductance Guaranteed by Design -- -- 0.2 mS
PWM Controller Gate Drivers
Upper Gate Sourcing Resistance RUG_SRC IUG = 100mA sourcing -- 2 4 Ω
Upper Gate Sinking Resistance RUG_SNK IUG = 100mA sinking -- 1 2 Ω
Lower Gate Sourcing Resistance RLG_SRC ILG = 100mA sourcing -- 1.5 3 Ω
Lower Gate Sinking Resistance RLG_SNK ILG = 100mA sinking -- 1 4 Ω
PH Falling to LG Rising Delay VPH < 1.2V to VLG > 1.2V -- 30 -- ns
LG Falling to UG Rising Delay VLG < 1.2V to (VUG - VPH ) > 1.2V -- 30 -- ns

uPI Semiconductor Corp., http://www.upi-semi.com 8

Rev. P00, File Name: uP1513-DS-P0000
 uP1513
Electrical Characteristics
Parameter Symbol Test Conditions Min Typ Max Units
OCP/EN
OCP/EN Current Source IOCSET VOCP/EN = 0.5V. 36 40 44 uA
Over Current Protection Level VOCP 0.38 0.40 0.42 V
OCP Delay Time -- 5 -- us
Disable Threshold Level VDIS VOCP/EN falling. 0.15 0.20 0.25 V
Disable Delay Time -- 5 -- us
Protection

Soft-Start Interval TSS 1 1.5 2 ms

Zero Current Corsing VZC VPH falling -2 -1 0 mV

uPI Semiconductor Corp., http://www.upi-semi.com 9

Rev. P00, File Name: uP1513-DS-P0000
 uP1513
Typical Operation Characteristics
Power On Waveforms Turn On from EN

VIN EN 5V/Div
5V/Div
VOUT
500mV/Div
VOUT
500mV/Div
LGATE
10V/Div
LGATE
10V/Div

IL IL 10A/Div
5A/Div

1ms/Div 2ms/Div
VIN = VCC = 12V, VOUT = 1.2V, COUT = 1400uF, No Load VIN = VCC = 12V, VOUT = 1.2V, COUT = 1400uF, No Load

Turn Off from EN Switching Waveforms: UGATE Trun On

VOUT
500mV/Div
UGATE
5V/Div
LGATE
10V/Div

PHASE
EN 5V/Div
2V/Div

IL UGATE - PHASE LGATE

10A/Div 5A/Div 5V/Div

20us/Div 40ns/Div
VIN = VCC = 12V, VOUT = 1.2V, COUT = 1400uF, IOUT = 6A VIN = VCC = 12V, IOUT = 10A

Switching Waveforms: UGATE Trun Off REFIN Operation

PHASE 10V/Div

UGATE
5V/Div
LGATE 10V/Div

PHASE
5V/Div

UGATE - PHASE REFIN

5A/Div 1V/Div VOUT
1V/Div

LGATE 5V/Div

40ns/Div 10ms/Div
VIN = VCC = 12V, IOUT = 10A VIN = VCC = 12V, COUT = 1400uF, IOUT = 6A

uPI Semiconductor Corp., http://www.upi-semi.com 10

Rev. P00, File Name: uP1513-DS-P0000
 uP1513
Typical Operation Characteristics
Power Sequencing Operation Load Transient Response

VOUT
100mV/Div

VIN
5V/Div
PHASE
10V/Div
VOUT
500mV/Div

LGATE IOUT
10V/Div 20A/Div

2ms/Div 10us/Div
VIN = VCC = 12V, VOUT = 1.2V, COUT = 1400uF, No Load VIN = VCC = 12V, VOUT = 1.2V, COUT = 1400uF

Over Current Protection Over Current Pretection

VOUT VOUT
500mV/Div 500mV/Div

PHASE
PHASE 10V/Div
10V/Div

IL IL
50A/Div 10V/Div

40us/Div 400us/Div
VIN = VCC = 12V, VOUT = 1.2V, COUT = 1400uF VIN = VCC = 12V, VOUT = 1.2V, COUT = 1400uF
Power On D Short VOUT to GND Short VOUT D Power On
Load Regulation Line Regulation
3 0.5
0.4
Output Voltage Deviation (%)

Output Voltage Deviation (%)

2
0.3
0.2
1
0.1
0 0.0
-0.1
-1
-0.2
-0.3
-2
-0.4
-3 -0.5
0 5 10 15 20 25 30 4 6 8 10 12 14
Output Current (A) Input Voltage (A)
VIN = VCC = 12V, IOUT = 0A ~ 30A, COUT = 1400uF VIN = VCC = 4.5V ~ 13.2V, IOUT = 0A, COUT = 1400uF

uPI Semiconductor Corp., http://www.upi-semi.com 11

Rev. P00, File Name: uP1513-DS-P0000
 uP1513
Typical Operation Characteristics
Switching Frequency vs. Input Voltage Switching Frequency vs. Junction Temperature
340 340

330 330
Switching Frequency (kHz)

Switching Frequency (kHz)

320 320

310 310

300 300

290 290

280 280

270 270
4 6 8 10 12 14 -50 -25 0 25 50 75 100 125
Input Voltage (V) Junction Temperature (OC)
VIN = VCC = 4.5V ~ 13.2V, IOUT = 3A, COUT = 1400uF VIN = VCC = 12V, IOUT = 3A, COUT = 1400uF

Output Voltage vs. Junction Temperature

3
Output Voltage Deviation (%)

-1

-2

-3
-50 -25 0 25 50 75 100 125
Junction Temperature (OC)
VIN = VCC = 12V, IOUT = 0A, COUT = 1400uF

uPI Semiconductor Corp., http://www.upi-semi.com 12

Rev. P00, File Name: uP1513-DS-P0000
 uP1513
Application Information
Power MOSFET Selection Both MOSFETs have I2R losses and the top MOSFET
External component selection is primarily determined by includes an additional term for switching losses, which
the maximum load current and begins with the selection are largest at high input voltages. The bottom MOSFET
of power MOSFET switches. The uP1513 requires two losses reach the greatest when the bottom duty cycle is
external N-channel power MOSFETs for upper (controlled) near 100%, during a short-circuit or at high input voltage.
and lower (synchronous) switches. Important parameters These equations assume linear voltage current transitions
for the power MOSFETs are the breakdown voltage and do not adequately model power loss due the reverse-
V (BR)DSS , on-resistance R DS(ON) , reverse transfer recovery of the lower MOSFET’s body diode. Ensure that
capacitance CRSS, maximum current IDS(MAX), gate supply both MOSFETs are within their maximum junction
requirements, and thermal management requirements. temperature at high ambient temperature by calculating
the temperature rise according to package thermal-
The gate drive voltage is powered by VCC pin that receives resistance specifications. A separate heatsink may be
4.5V~13.2V supply voltage. When operating with a 12V necessary depending upon MOSFET power, package
power supply for VCC (or down to a minimum supply type, ambient temperature and air flow.
voltage of 8V), a wide variety of NMOSFETs can be used.
Logic-level threshold MOSFET should be used if the input The gate-charge losses are dissipated by the uP1513 and
voltage is expected to drop below 8V. Since the lower don’t heat the MOSFETs. However, large gate charge
MOSFET is used as the current sensing element, increases the switching interval, TSW that increases the
particular attention must be paid to its on-resistance. Look MOSFET switching losses. The gate-charge losses are
for RDS(ON) ratings at lowest gate driving voltage. calculated as:

Special cautions should be exercised on the lower switch PG = VCC × ( VCC × (CISS _ UP + CISS _ LO ) + VIN × CRSS ) × fOSC
exhibiting very low threshold voltage VGS(TH). The shoot-
where CISS_UP is the input capacitance of the upper
through protection present aboard the uP1513 may be
MOSFET, CISS_LO is the input capacitance of the lower
circumvented by these MOSFETs if they have large
parasitic impedances and/or capacitances that would MOSFET, and CRSS_UP is the reverse transfer capacitance
of the upper MOSFET. Make sure that the gate-charge
inhibit the gate of the MOSFET from being discharged
loss will not cause over temperature at uP1513, especially
below its threshold level before the complementary
MOSFET is turned on. Also avoid MOSFETs with with large gate capacitance and high supply voltage.
excessive switching times; the circuitry is expecting Output Inductor Selection
transitions to occur in under 50 nsec or so. Output inductor selection usually is based on the
In high-current applications, the MOSFET power considerations of inductance, rated current, size
dissipation, package selection and heatsink are the requirement, and DC resistance (DC)
dominant design factors. The power dissipation includes Given the desired input and output voltages, the inductor
two loss components; conduction loss and switching loss. value and operating frequency determine the ripple
The conduction losses are the largest component of power current:
dissipation for both the upper and the lower MOSFETs.
These losses are distributed between the two MOSFETs 1 V
ΔIL = × VOUT × (1 − OUT )
according to duty cycle. Since the uP1513 is operating in fOSC × L OUT VIN
continuous conduction mode, the duty cycles for the Lower ripple current reduces core losses in the inductor,
MOSFETs are: ESR losses in the output capacitors and output voltage
ripple. Highest efficiency operation is obtained at low
VOUT VIN − VOUT
DUP = DLO = frequency with small ripple current. However, achieving
VIN VIN
; this requires a large inductor. There is a tradeoff between
The resulting power dissipation in the MOSFETs at component size, efficiency and operating frequency. A
maximum output current are: reasonable starting point is to choose a ripple current that
is about 40% of IOUT(MAX).
2
PUP = IOUT × RDS(ON) × DUP + 0.5 × IOUT × VIN × TSW × fOSC
There is another tradeoff between output ripple current/
2 voltage and response time to a transient load. Increasing
PLO = IOUT × RDS(ON) × DLO
the value of inductance reduces the output ripple current
where TSW is the combined switch ON and OFF time. and voltage. However, the large inductance values reduce
the converter’s response time to a load transient.

uPI Semiconductor Corp., http://www.upi-semi.com 13

Rev. P00, File Name: uP1513-DS-P0000
 uP1513
Application Information
Maximum current ratings of the inductor are generally deviations do not offer much relief. Note that the capacitor
specified in two methods: permissible DC current and manufacturer’s ripple current ratings are often based on
saturation current. Permissible DC current is the allowable 2000 hours of life. This makes it advisable to further derate
DC current that causes 40OC temperature raise. The the capacitor, or choose a capacitor rated at a higher
saturation current is the allowable current that causes 10% temperature than required. Always consult the
inductance loss. Make sure that the inductor will not manufacturer if there is any question.
saturate over the operation conditions including For a through-hole design, several electrolytic capacitors
temperature range, input voltage range, and maximum may be needed. For surface mount designs, solid tantalum
output current. capacitors can also be used, but caution must be exercised
The size requirements refer to the area and height with regard to the capacitor surge current rating. These
requirement for a particular design. For better efficiency, capacitors must be capable of handling the surge-current
choose a low DC resistance inductor. DCR is usually at power-up. Some capacitor series available from
inversely proportional to size. reputable manufacturers are surge current tested.
Different core materials and shapes will change the size/ Output Capacitor Selection
current and price/current relationship of an inductor. Toroid An output capacitor is required to filter the output and
or shielded pot cores in ferrite or permalloy materials are supply the load transient current. The selection of COUT
small and don’t radiate much energy, but generally cost is primarily determined by the ESR required to minimize
more than powdered iron core inductors with similar voltage ripple and load step transients. The output ripple
electrical characteristics. The choice of which style ΔVOUT is approximately bounded by:
inductor to use often depends more on the price vs. size
requirements and any radiated field/EMI requirements. 1
ΔVOUT ≤ ΔIL (ESR + )
Input Capacitor Selection 8 × fOSC × C OUT

The synchronous-rectified buck converter draws pulsed Since ΔIL increases with input voltage, the output ripple is
current with sharp edges from the input capacitor resulting highest at maximum input voltage. Typically, once the ESR
in ripples and spikes at the input supply voltage. Use a requirement is satisfied, the capacitance is adequate for
mix of input bypass capacitors to control the voltage filtering and has the necessary RMS current rating. Multiple
overshoot across the MOSFETs. Use small ceramic capacitors placed in parallel may be needed to meet the
capacitors for high frequency decoupling and bulk ESR and RMS current handling requirements. Dry
capacitors to supply the current needed each time upper tantalum, special polymer, aluminum electrolytic and
MOSFET turns on. Place the small ceramic capacitors ceramic capacitors are all available in surface mount
physically close to the MOSFETs and between the drain packages. Special polymer capacitors offer very low ESR
of upper MOSET and the source of lower MOSFET to but have lower capacitance density than other types.
avoid the stray inductance along the connection trace. The load transient requirements are a function of the slew
The important parameters for the bulk input capacitor are rate (di/dt) and the magnitude of the transient load current.
the voltage rating and the RMS current rating. For reliable These requirements are generally met with a mix of
operation, select the bulk capacitor with voltage and current capacitors and careful layout. Modern components and
ratings above the maximum input voltage and largest RMS loads are capable of producing transient load rates above
1A/ns. High frequency capacitors initially supply the
current required by the circuit. The capacitor voltage rating
transient and slow the current load rate seen by the bulk
should be at least 1.25 times greater than the maximum
capacitors. The bulk filter capacitor values are generally
input voltage and a voltage rating of 1.5 times is a
determined by the ESR (Effective Series Resistance) and
conservative guideline. The RMS current rating
voltage rating requirements rather than actual capacitance
requirement for the input capacitor of a buck converter is
requirements.
calculated as:
High frequency decoupling capacitors should be placed
VOUT ( VIN − VOUT ) as close to the power pins of the load as physically
IIN(RMS) = IOUT(MAX ) possible. Be careful not to add inductance in the circuit
VIN
board wiring that could cancel the usefulness of these
This formula has a maximum at VIN = 2VOUT, where low inductance components. Consult with the
IIN(RMS) = IOUT(RMS)/2. This simple worst-case condition manufacturer of the load on specific decoupling
is commonly used for design because even significant requirements.

uPI Semiconductor Corp., http://www.upi-semi.com 14

Rev. P00, File Name: uP1513-DS-P0000
 uP1513
Application Information
Use only specialized low-ESR capacitors intended for 2 Place the power components as physically close as
switching-regulator applications for the bulk capacitors. possible.
The bulk capacitor’s ESR will determine the output ripple 2.1 Place the input capacitors, especially the high-
voltage and the initial voltage drop after a high slew-rate frequency ceramic decoupling capacitors, directly
transient. An aluminum electrolytic capacitor’s ESR value to the drain of upper MOSFET ad the source of
is related to the case size with lower ESR available in the lower MOSFET. To reduce the ESR replace
larger case sizes. the single input capacitor with two parallel units
However, the Equivalent Series Inductance (ESL) of these 2.2 Place the output capacitor between the converter
capacitors increases with case size and can reduce the and load.
usefulness of the capacitor to high slew-rate transient
loading. 3 Place the uP1513 near the upper and lower MOSFETs
with pins 1 to 4 facing the power components. Keep
Unfortunately, ESL is not a specified parameter. Work with the components connected to pins 4 to 8 close to the
your capacitor supplier and measure the capacitor’s uP1513 and away from the inductor and other noise
impedance with frequency to select a suitable component. sources (noise sensitive components).
In most cases, multiple electrolytic capacitors of small case
size perform better than a single large case capacitor. 4 Use a dedicated grounding plane and use vias to
ground all critical components to this layer. The ground
Bootstrap Capacitor Selection plane layer should not have any traces and it should
An external bootstrap capacitor CBOOT connected to the be as close as possible to the layer with power
BOOT pin supplies the gate drive voltage for the upper MOSFETs. Use an immediate via to connect the
MOSFET. This capacitor is charged through the internal components to ground plane including GND of uP1513
diode when the PHASE node is low. When the upper Use several bigger vias for power components.
MOSFET turns on, the PHASE node rises to VIN and the 5 Apply another solid layer as a power plane and cut
BOOT pin rises to approximately VIN + VCC. The boot this plane into smaller islands of common voltage
capacitor needs to store about 100 times the gate charge levels. The power plane should support the input power
required by the upper MOSFET. In most applications 0.1uF and output power nodes to maintain good voltage
to 0.47uF, X5R or X7R dielectric capacitor is adequate. filtering and to keep power losses low. Also, for higher
PCB Layout Considerations currents, it is recommended to use a multilayer board
High speed switching and relatively large peak currents to help with heat sinking power components.
in a synchronous-rectified buck converter make the PCB 6 The PHASE node is subject to very high dV/dt
layout a very important part of design. Fast current voltages. Stray capacitance between this island and
switching from one device to another in a synchronous- the surrounding circuitry tend to induce current spike
rectified buck converter causes voltage spikes across the and capacitive noise coupling. Keep the sensitive
interconnecting impedances and parasitic circuit elements. circuit away from the PHASE node and keep the PCB
The voltage spikes can degrade efficiency and radiate area small to limit the capacitive coupling. However,
noise that result in overvoltage stress on devices. Careful the PCB area should be kept moderate since it also
component placement layout and printed circuit design acts as main heat convection path of the lower
minimizes the voltage spikes induced in the converter. MOSFET.
Follow the layout guidelines for optimal performance of 7 uP1513 sources/sinks impulse current with 2A peak
uP1513 to turn on/off the upper and lower MOSFETs. The
1 The upper and lower MOSFETs turn on/off and connecting trance between the controller and gate/
conduct pulsed current alternatively with high slew rate source of the MOSFET should be wide and short to
transition. Any inductance in the switched current path minimize the parasitic inductance along the traces.
generates a large voltage spike during the switching. 8 Flood all unused areas on all layers with copper.
The interconnecting wires indicated by red heavy lines Flooding with copper will reduce the temperature rise
conduct pulsed current with sharp transient and should of power component.
be part of a ground or power plane in a printed circuit 9 Provide local VCC decoupling between VCC and GND
board to minimize the voltage spike. Make all the pins. Locate the capacitor, CBOOT as close as practical
connection the top layer with wide, copper filled areas. to the BOOT and PH pins.

uPI Semiconductor Corp., http://www.upi-semi.com 15

Rev. P00, File Name: uP1513-DS-P0000
 uP1513
Package Information
PSOP-8L Package

0.70 ± 0. 10 4.80 - 5.00

1.27 ± 0.10
1.80 - 2.30

1.50 ± 0. 10
2.20 ± 0. 10

4.00 ± 0. 10
2.20 ± 0. 10
7.00 ± 0.10
5.50 ± 0.10

5.80 - 6.20
3.80 - 4.00

1.80 - 2.30
1.27 BSC 0.32 - 0.52

Recommended Solder Pad Layout

1.45 - 1.60

0.18 - 0.25 1.75 MAX

0.05 - 0.25

0.40 - 0.90 3.81 BSC

Note
1.Package Outline Unit Description:
BSC: Basic. Represents theoretical exact dimension or dimension target
MIN: Minimum dimension specified.
MAX: Maximum dimension specified.
REF: Reference. Represents dimension for reference use only. This value is not a device specification.
TYP. Typical. Provided as a general value. This value is not a device specification.
2.Dimensions in Millimeters.
3.Drawing not to scale.
4.These dimensions no not include mold flash or protrusions. Mold flash or protrusions shell not exceed 0.15mm.

uPI Semiconductor Corp., http://www.upi-semi.com 16

Rev. P00, File Name: uP1513-DS-P0000