APL3523A

Ultra-Low On-Resistance, 6A Dual Load Switch with Soft Start

Features General Description

• 16mΩ(Typical) On-resistance per Channel The APL3523A is an ultra-low on-resistance, dual power-
• 6A Continuous Current distribution switch with external soft start control. It inte-
grates two N-channel MOSFETs that can deliver 6A con-
• Soft Start Time Programmable by External
tinuous load current each.
Capacitor
The device integrates over-temperature protection. The
• Wide Input Voltage Range (VIN): 0.8V to 5.5V
over temperature protection function shuts down the N-
• Supply Voltage Range (VBIAS): 3V to 5.5V channel MOSFET power switch when the junction tem-
• Output Discharge when Switch Disabled perature rises beyond 160oC and will automatically turns
• Reverse Current Blocking when Switch Disabled on the power switch when the temperature drops by 40oC.
• Over-Temperature Protection The device is available in lead free TDFN2x3-14
• Enable Input packages.

• Lead Free and Green Devices Available (RoHS

Compliant)

Applications
• Notebook
• AIO PC
Simplified Application Circuit

Pin Configurations VBIAS

BIAS

APL3523A
VIN1
VOUT1
VIN1 1 14 VOUT1 VIN1 VOUT1
VIN1 2 13 VOUT1
EN1 3 12 SS1 APL3523A
VIN2
BIAS 4 11 GND VIN2
EN2 5 10 SS2
VIN2 6 9 VOUT2 VOUT2 VOUT2
VIN2 7 8 VOUT2
On EN1
TDFN2x3-14
Off
(Top View) EN2

SS1 SS2 GND

= Exposed Pad

ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and
advise customers to obtain the latest version of relevant information to verify before placing orders.

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Rev. A.6 - May., 2017
APL3523A

Ordering and Marking Information

APL3523A Package Code
QB : TDFN2x3-14
Assembly Material Operating Ambient Temperature Range
I : -40 to 85oC
Handling Code Handling Code
TemperatureRange TR : Tape & Reel
Assembly Material
Package Code G : Halogen and Lead Free Device

3523A XXXXX-Date Code

APL3523A QB: XXXXX

Note : ANPEC lead-free products contain molding compounds/die attach materials and 100% matte tin plate termination finish; which
are fully compliant with RoHS. ANPEC lead-free products meet or exceed the lead-free requirements of IPC/JEDEC J-STD-020D for
MSL classification at lead-free peak reflow temperature. ANPEC defines “Green” to mean lead-free (RoHS compliant)and halogen
free (Br or Cl does not exceed 900ppm by weight in homogeneous material and total of Br and Cl does not exceed 1500ppm by
weight).

Absolute Maximum Ratings (Note 1)

Symbol Parameter Rating Unit
VBIAS BAIS to GND Voltage -0.3 ~ 6 V
VIN1, VIN2 VIN1, VIN2 to GND Voltage -0.3 ~ 6 V
VOUT1, VOUT2 VOUT1, VOUT2 to GND Voltage -0.3 ~ 6 V
VEN1, VEN2 EN1, EN2 to GND Voltage -0.3 ~ 6 V
o
TJ Maximum Junction Temperature -40 ~ 150 C
o
TSTG Storage Temperature -65 ~ 150 C
o
TSDR Maximum Lead Soldering Temperature (10 Seconds) 260 C
Note1: Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are
stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under "recom-
mended operating conditions" is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device
reliability.

Thermal Characteristics
S ymbol Pa ram eter Typica l Value Unit
(No te 2 ) o
θJA Jun ction- to- Ambient Re sistance in Fr ee Ai r 80 C/W
o
θJC Jun ction- to- Ca se Resistan ce in Free A ir 15 C/W

Note 2: θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. The exposed pad
of TDFN2x3-14 is soldered directly on the PCB.

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Rev. A.6 - May., 2017
APL3523A

Recommended Operating Conditions (Note 3)

Symbol Param eter Range Unit

VBIAS BIAS Inp ut Voltage (V BIAS>V IN ) 3.0 ~ 5.5 V
VIN VIN Inp ut Voltage 0.8 ~ 5.5 V
VOUT Ou tpu t Curren t (Single Chan nel) 0~6
I OUT Maximum Pulsed S witch Curren t, P ulse<300µs, 1% Duty Cycle A
8
(Single Cha nnel)
o (Note4 )
PD Maximum Power Dissipation, T A=50 C 0.9 4 W
VIH EN/ENB Lo gic Hig h Inpu t Voltage 0.8 ~ 5.5 V
V IL EN/ENB Lo gic L ow Inpu t Voltage 0 ~ 0.4 V
o
TA Amb ient Temp erature -4 0 ~ 85 C
o
TJ Junction Tempera tu re -40 ~ 12 5 C
Note 3 : Refer to the typical application circuit.
Note 4 : Refer to the thermal consideration on page 15.

Electrical Characteristics
Unless otherwise specified, these specifications apply over VIN1= VIN2= 0.8V~5.5V, VEN1= VEN2=VBIAS =5V and TA= -40~85oC.
Typical values are at TA=25oC.

APL3523A
Symbol Parameter Test Conditions Unit
Min. Typ. Max.
SUPPLY CURRENT
BIAS Supply Current (both
No load, VBIAS=5V =VEN1,2=5V - 60 90 µA
channels)
IBIAS
BIAS Supply Current (single
No load, VBIAS=5V, VEN1=5V, VEN2=0V - 50 - µA
channel)
BIAS Supply Current at
ISD No load, VBIAS=5V, VEN1,2=0V - - 2 µA
Shutdown
No load, VBIAS=5V, VEN1,2=0V, VIN1,2=5V - 0.1 8 µA
No load, VBIAS=5V, VEN1,2=0V, VIN1,2=3.3V - 0.1 3 µA
VIN Off-State Supply Current
IOFF No load, VBIAS=5V, VEN1,2=0V, VIN1,2=1.8V - 0.1 2 µA
(per channel)

No load, VBIAS=5V, VEN1,2=0V, VIN1,2=0.8V - 0.1 1 µA

Reverse Leakage Current (per
VEN1,2=0V, VIN1,2=0V - 0.1 16 µA
channel)
UNDER-VOLTAGE LOCKOUT (UVLO)
Rising BIAS UVLO Threshold VBIAS rising 1.9 2.4 2.9 V
BIAS UVLO Hysteresis - 0.1 - V
POWER SWITCH

IOUT=200mA, TJ= 25oC - 16 18 mΩ

Channel 1
o
RDS(ON) Power Switch On Resistance IOUT=200mA, TJ= -40~125 C - - 24 mΩ
o
IOUT=200mA, TJ= 25 C - 16 18 mΩ
Channel 2
IOUT=200mA, TJ= -40~125oC - - 24 mΩ
VOUT Discharge Resistance VEN1,2=0V, VOUT1 or VOUT2 force 1V - 150 180 Ω

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Rev. A.6 - May., 2017
 APL3523A

Electrical Characteristics
Unless otherwise specified, these specifications apply over VIN1= VIN2= 0.8V~5.5V, VEN1= VEN2=VBIAS =5V and TA= -40~85oC.
Typical values are at TA=25oC.

APL3523A
Symbol Parameter Test Conditions Unit
Min. Typ. Max.
SOFT-START CONTROL PIN
VSS1,2=6V, VEN1,2=0V, EN2=low, measured at
SS Discharge Current - 560 - µA
SS1 or SS2
EN INPUT PIN
Input Logic High 1.2 - - V
Input Logic Low - - 0.4 V
Input Current - - 1 µA
OVERT-TEMPERATURE PROTECTION (OTP)
Over-Temperature Threshold TJ rising - 160 - °C
Over-Temperature Hysteresis - 40 - °C

Timing Chart

50% 50%
tR tF
VEN

tON tOFF
90% 90%

50% 50%
VOUT VOUT
10% 10%

tD

Figure 1. tON/tOFF, tR/tF Waveforms

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Rev. A.6 - May., 2017
APL3523A

Typical Operating Characteristics

Quiescent Current vs. BIAS Quiescent Current vs. BIAS Supply
Supply Voltage (Both Channels ) Voltage (Single Channel )
100 60
VBIAS = V IN -40 -40
VBIAS = VIN
25 25
Quiescent Current, IBIAS (µA)

90

Quiescent Current, IBIAS (µA)

55
85 85
80 125 50 125

70
45

60 40

50
35

40 30
3 3.5 4 4.5 5 5.5
3 3.5 4 4.5 5 5.5
BIAS Supply Voltage, V BIAS (V) BIAS Supply Voltage, V BIAS (V)
Shutdown Current vs . BIAS Off-Stage Supply Current vs. VIN
Supply Voltage (Both Channels) Supply Voltage (SINGLE CHANNEL)
0.5 14
-40 -40
V BIAS = VIN V BIAS = 5.5V
Off-Stage Supply Current, IOFF (µA)

25 12 25
Quiescent Current, ISD (µA)

0.4
85 85
10
125 125
0.3
8

6
0.2

4
0.1
2

0 0
3 3.5 4 4.5 5 5.5 3 3.5 4 4.5 5 5.5
BIAS Supply Voltage, V BIAS (V) VIN Supply Voltage, VIN (V)

Switch On Resistance vs. VIN Switch On Resistance vs. VIN

Supply Voltage Supply Voltage
32 24
-40 -40
VBIAS = 3 V VBIAS = 5.5V
Switch On Resistance, RDS(ON) (mΩ)
Switch On Resistance, RDS(ON) (mΩ)

23
30 0 0
22
28 25 25
21
50 50
26 20
75 75
24 19
100 100
22 18
125 125
17
20
16
18
15
16
14
14 13
12 12
0 .5 1 1.5 2 2.5 3 0 0 .5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5
VIN Supply Voltage, VIN (V) VIN Supply Voltage, VIN (V)

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Rev. A.6 - May., 2017
APL3523A

Typical Operating Characteristics

Switch On Resistance vs. VIN Switch On Resistance vs. Output
Supply Voltage Current
24 20
TJ =25 °C VBIAS=5 V
Switch On Resistance, RDS(ON) (mΩ)

VBIAS = 5V, VIN = 5V , TJ = 25°C

Switch On Resistance, RDS(ON) (mΩ)

23
VBIAS=3 .3V 19
22

21
18
20

19 17
18

17 16

16
15
15

14 14
0.5 1.5 2.5 3.5 4.5 5 .5 0 1 2 3 4 5 6

VIN Supply Voltage, VIN (V) Output Current, IOUT (A)

Turn On Delay Time vs . VIN Turn On Delay Time vs . VIN Supply
Supply Voltage Voltage
500 500
-40 -40
VBIAS = 3V, RL = 10 Ω VBIAS = 5.5V, CSS = 1nF,
450 450
C SS = 1nF, C OUT = 0.1µF 25 ROUT = 10Ω, C OUT = 0.1 µF 25
Turn On Delay Time, tD (µs)

Turn On Delay Time, tD (µs)

400 85 400 85
350 125 350 125

300 300

250 250

200 200

150 150

100 100

50 50
0 .8 1.0 1.2 1.4 1.6 1 .8 2.0 2.2 2.4 2 .6 2.8 3.0 0.5 1 .5 2.5 3.5 4.5 5.5
VIN Supply Voltage, VIN (V) VIN Supply Voltage, VIN (V)

Falling Time vs . VIN Supply Voltage Falling Time vs . VIN Supply Voltage
5 5
-40 -40
VBIAS = 3V, RL = 10 Ω VBIAS = 5.5V, Css = 1nF,
C SS = 1nF, C OUT = 0.1µ F 25 R OUT = 10 Ω, C OUT = 0.1 µF 25
4 85
85 4
Falling Time, tF (µs)
Falling Time, tF (µs)

125 125
3

2
1

0 1
0.8 1.0 1.2 1.4 1.6 1.8 2 .0 2.2 2.4 2.6 2.8 3 .0 0.5 1 1.5 2 2 .5 3 3.5 4 4.5 5 5.5
VIN Supply Voltage, VIN (V) VIN Supply Voltage, VIN (V)

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Rev. A.6 - May., 2017
APL3523A

Typical Operating Characteristics

Turn Off Time vs . VIN Supply Turn Off Time vs . VIN Supply
Voltage Voltage
5 5
-40 -40
VBIAS = 3V, R L = 10 Ω VBIAS = 5.5V, R L = 10Ω
C SS = 1 nF, COUT = 0.1µF 25 C SS = 1nF, C OUT = 0.1µF 25
4 4

Turn Off Time, tOFF (µs)

Turn Off Time, tOFF (µs)

85 85

125 125
3 3

2 2

1 1

0 0
0.8 1 .0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 0.8 1.0 1.2 1.4 1 .6 1.8 2.0 2.2 2.4 2.6 2.8 3.0
VIN Supply Voltage, VIN (V) VIN Supply Voltage, VIN (V)

Turn On Time vs . VIN Supply Turn On Time vs . VIN Supply

Voltage Voltage
1200 2000
VBIAS = 3 V, R L = 10Ω -40 -40
VBIAS = 5.5V, RL = 10 Ω
CSS = 1nF, C OUT = 0.1 µF 1800 CSS = 1nF, C OUT = 0.1 µF
25 25
1000
1600
Turn On Time, tON (µs)

Turn On Time, tON (µs)

85 85
1400
800 125 125
1200

600 1000

800
400
600

400
200
200

0 0
0.5 1.0 1 .5 2.0 2.5 3.0 0.5 1 .0 1.5 2.0 2.5 3.0 3 .5 4.0 4.5 5.0 5.5
VIN Supply Voltage, VIN (V) VIN Supply Voltage, VIN (V)

Rising Time vs. VIN Supply Voltage Rising Time vs. VIN Supply Voltage
1400 3000
VBIAS = 3V, R L = 10Ω -40 V BIAS = 5.5V, R L = 10 Ω - 40
C SS = 1 nF, COUT = 0.1µF C SS = 1nF, C OUT = 0 .1µ F
1200 25 25
2500
85 85
Rising Time, tR (µs)
Rising Time, tR (µs)

1000
125 2000 125

800
1500
600

1000
400

500
200

0 0
0.5 1.0 1.5 2.0 2.5 3 .0 0.5 1.0 1 .5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5 .5
VIN Supply Voltage, VIN (V) VIN Supply Voltage, VIN (V)

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Rev. A.6 - May., 2017
APL3523A

Typical Operating Characteristics

Rising Time vs . BIAS Supply
Voltage
1600
- 40
1400 25

85
Rising Time, tR (µs)

1200
125
1000

800

600

400 VIN = 3V, R L = 10 Ω

C SS = 1 nF, COUT = 0.1µF
200
3 3.5 4 4.5 5 5 .5
BIAS Supply Voltage, V BIAS (V)

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Rev. A.6 - May., 2017
APL3523A

Operating Waveforms
Refer to the typical application circuit. TA= 25oC unless otherwise specified.

Enable Shutdown

VEN VEN
1 1

2
VOUT VOUT
2
I OUT
IOUT
3 3

VBIAS=5V, VIN=0.8V VBIAS=5V, VIN=0.8V

COUT =0.1µF, CSS=1nF, RL=10Ω COUT =0.1µF, CSS=1nF, RL=10Ω
CH1: VEN, 2V/Div, DC CH1: VEN, 2V/Div, DC
CH2: VOUT , 200mV/Div, DC CH2: VOUT, 200mV/Div, DC
CH3: IOUT , 50mA/Div, DC CH3: IOUT , 50mA/Div, DC
TIME: 200µs/Div TIME: 1µs/Div

Enable Shutdown

VEN VEN

1 1

VOUT
VOUT
2 2
IOUT I OUT
3 3

VBIAS=3V, VIN=0.8V VBIAS=3V, VIN=0.8V

COUT =0.1µF, CSS=1nF, RL=10Ω COUT=0.1µF, CSS=1nF, RL=10Ω
CH1: V EN, 2V/Div, DC CH1: VEN, 2V/Div, DC
CH2: V OUT, 200mV/Div, DC CH2: VOUT , 200mV/Div, DC
CH3: IOUT , 50mA/Div, DC CH3: IOUT , 50mA/Div, DC
TIME: 200µs/Div TIME: 1µs/Div

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Rev. A.6 - May., 2017
APL3523A

Operating Waveforms
Refer to the typical application circuit. TA= 25oC unless otherwise specified.

Enable Shutdown

VEN
VEN
1 1

VOUT
V OUT
2 2
IOUT IOUT
3 3

VBIAS=5V, VIN=5V VBIAS=5V, VIN=5V

COUT =0.1µF, CSS=1nF, RL=10Ω COUT =0.1µF, CSS=1nF, RL=10Ω
CH1: VEN, 2V/Div, DC CH1: VEN, 2V/Div, DC
CH2: VOUT , 1V/Div, DC CH2: VOUT , 1V/Div, DC
CH3: IOUT, 200mA/Div, DC CH3: IOUT, 200mA/Div, DC
TIME: 500µs/Div

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APL3523A

Pin Description
PIN
FUNCTION
NO. NAME
1 VIN1
Power supply Input of switch 1. Connect this pin to an external DC supply.
2 VIN1
3 EN1 Enable input of switch 1. Logic high turns on switch 1. The EN1 pin cannot be left floating.
4 BIAS Bias voltage input pin for internal control circuitry.
5 EN2 Enable input of switch 2. Logic high turns on switch 2. The EN2 pin cannot be left floating.
6 VIN2
Power supply Input of switch 2. Connect this pin to an external DC supply.
7 VIN2
8 VOUT2
Switch 2 output.
9 VOUT2

Soft start control of switch 2. A capacitor from this pin to ground sets the VOUT2’s rise slew
10 SS2
rate.

11 GND Ground pin of the circuitry. All voltage levels are measured with respect to this pin.
Soft start control of switch 1. A capacitor from this pin to ground sets the VOUT1’s rise slew
12 SS1
rate.
13 VOUT1
Switch 1 output.
14 VOUT1
Exposed Pad - Connect the exposed pad to the system ground plan.

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Rev. A.6 - May., 2017
APL3523A

Block Diagram

Bulk
Select
VIN1 VOUT1

UVLO Charge
BIAS
Pump

SS1

Control OTP1
EN1 Logic
OTP2

EN2

Bulk
Select

VIN2 VOUT2

Charge
Pump

SS2

GND

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Rev. A.6 - May., 2017
APL3523A

Typical Application Circuit

VBIAS
4
BIAS
C BIAS
0.1µF

V IN1 1, 2
VIN1 VOUT1 13 , 14
C IN1 C OUT1 C L1
1µ F RLOAD1
0.1µF 150 µ F
VIN2
APL3523A
6, 7
VIN2
CIN2
1µF 8 ,9
VOUT2
C OUT2 CL 2 R LOAD2
3 0.1 µF 150 µF
On EN1

Off 5
EN2

SS1 SS2 GND

12 10 11

C SS1 C SS2

Soft-Start Time (µs) 10% to 90%, VBIAS=5V, CL=0.1µF, CIN=1µF, RL=10Ω, Typical values are at TA=25°C
CSS(pF)
VIN=5V VIN=3.3V VIN=1.8V VIN=1.5V VIN=1.2V VIN=1.05V VIN=0.8V
0 112 73 53 49 45 42 38
220 492 322 197 170 146 132 128
330 685 450 270 230 198 180 145
470 911 598 355 307 263 233 188
1000 2030 1280 749 635 538 470 388
2200 4360 2740 1574 1336 1118 1014 797
4700 8780 5540 3218 2696 2289 2037 1624
10000 19060 12011 6862 5700 4806 4301 3410

Note: The table Contains soft-start time values measured on a typical device. The soft-start times shown are only valid for the power-
up sequence where VIN and VBIAS are already in steady state condition, and EN pin is asserted high.

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Rev. A.6 - May., 2017
APL3523A

Function Description
VIN Under-voltage Lockout (UVLO)

A under-voltage lockout (UVLO) circuit monitors the VBIAS

pins voltage to prevent wrong logic controls. The UVLO
function initiates a soft-start process after the BIAS sup-
ply voltages exceed rising UVLO voltage threshold dur-
ing powering on.

Power Switch

The power switch is an N-channel MOSFET with a ultra-

low RDS(ON). When IC is in shutdown state (VEN1,2=0V), the
MOSFET prevents a reverse current flowing from the VOUT
back to VIN. When IC is in UVLO state, the internal para-
sitic diodes connected from VOUT to VIN will be forward
biased.

Soft-start

The APL3523A Provides an adjustable soft-start circuitry

to control rise rate of the output voltage and limit the cur-
rent surge during start-up. The soft-start time is set with a
capacitor from the SS pin to the ground.

Enable Control

The APL3523A has a dedicated enable pin (EN). A logic

low signal applied to this pin shuts down the output. Fol-
lowing a shutdown, a logic high signal re-enables the
output through initiation of a new soft-start cycle.

Over-Temperature Protection (OTP)

When the junction temperature exceeds 160oC, the inter-
nal thermal sense circuit turns off the power FET and
allows the device to cool down. When the device’s junc-
tion temperature cools by 40 oC, the internal thermal
sense circuit will enable the device, resulting in a pulsed
output during continuous thermal protection. Thermal
protection is designed to protect the IC in the event of
over temperature conditions. For normal operation, the
junction temperature cannot exceed TJ=+125oC.

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Rev. A.6 - May., 2017
APL3523A

Application Information
Power Sequencing A bulk output capacitor, placed close to the load, is rec-
VBIAS ommended to support load transient current.

VIN1, VIN2 Soft-Start Capacitor

The soft-start capacitor on SS pin can reduce the inrush
VEN1, VEN2
current and overshoot of output voltage. The soft-start
VOUT1, VOUT2 time is set with a capacitor from the SS pin to the ground.
Thermal Consideration

The APL3523A maximum power dissipation depends on

VEN1, VEN2 the differences of the thermal resistance and tempera-
ture between junction and ambient air. The power dissi-
VOUT1, VOUT2
pation PD across the device is:
VIN1, VIN2 PD = (TJ - TA) / θJA
where (TJ-TA) is the temperature difference between the
VBIAS
junction and ambient air. θJA is the thermal resistance
Figure 2. APL3523A Power Sequencing Diagram between junction and ambient air. Assuming the TA=25°C
and maximum TJ=160°C (typical thermal limit threshold),
The APL3523A has a built-in reverse current blocking cir-
the maximum power dissipation is calculated as:
cuit to prevent a reverse current flowing through the body
diode of power switch from the VOUT back VIN pin when PD(max)=(160-25)/80
power switch disabled. The reverse current blocking cir- = 1.68(W)
cuit is not active before VBIAS is ready. When IC is in UVLO For normal operation, do not exceed the maximum oper-
state, the internal parasitic diodes of power switch con- ating junction temperature of TJ = 125°C. The calculated
nected from VOUT to VIN will be forward biased. power dissipation should be less than:
Otherwise, VOUT should not be higher than VBIAS, and PD =(125-25)/80
VBIAS must be higher than the voltage of any other input
= 1.25(W)....................................................TA=25oC
pin, the reason is that the internal parasitic diodes con-
PD =(125-85)/80
nected from VOUT to VBIAS will be forward biased.
= 0.5(W)......................................................TA=85oC
Capacitor Selection
The power dissipation depends on operating ambient
The APL3523A requires proper input capacitors to supply temperature for fixed TJ=125oC and thermal resistance
current surge during stepping load transients to prevent θJA. For APL3523A packages, the Figure 3~4 of derating
the input voltage rail from dropping. Because the para- curves allows the designer to see the effect of rising
sitic inductor from the voltage sources or other bulk ca- ambient temperature on the maximum power allowed.
pacitors to the VIN pin limit the slew rate of the surge
currents, more parasitic inductance needs more input
capacitance. PD = (IOUT
2
1 + IOUT 2 ) ⋅ RDS,ON
2

For normal applications (except OTP or output short cir- RDS,ON = 0.024 Ω LLLLLLLLTJ = 125° C
cuit has occurred), the recommended input capacitance IOUT 2 = k ⋅ IOUT1 LLLLLLLLk ≤ 1
of VIN is 1µF. Additional input capacitance may be needed
or
on the input to reduce voltage overshoot from exceeding
IOUT1 = k ⋅ IOUT 2 LLLLLLLLk ≤ 1
the absolute maximum voltage of the device during load
transient conditions. The output capacitance of VOUT is IOUT1,2(MAX) = 6A
0.1µF at least. Please place the capacitors near the
APL3523A as close as possible.

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Rev. A.6 - May., 2017
APL3523A

Application Information
1.3
TDFN2x3-14
Layout Consideration
1.2
Power Dissipation (W)

The PCB layout should be carefully performed to maxi-

1.1
mize thermal dissipation and to minimize voltage drop,
1.0
0.9
droop and EMI. The following guidelines must be
0.8
considered:
0.7 1. Please place the input capacitors near the VIN pin as
0.6 close as possible.
0.5 2. Output decoupling capacitors for load must be placed
-40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90
near the load as close as possible for decoupling high
Ambient Temperature (oC)
frequency ripples.
Figure 3. Derating Curves for APL3523A Package
3. Locate APL3523A and output capacitors near the load
12
TDFN2x3-14
to reduce parasitic resistance and inductance for excel-
Output Current, IOUT1+IOUT2 (A)

11 VBIAS=5V
10 lent load transient performance.
9
8 4. The negative pins of the input and output capacitors
7
6
and the GND pin must be connected to the ground plane
5
4
of the load.
3
k=1 k=0.5 5. Keep VIN and VOUT traces as wide and short as
2
1 k=0 k=0.2 possible.
0
-40 -35 -30 -25-20 -15 -10 -5 0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 85 Recommended Minimum Footprint
Ambient Temperature (oC)
The Via Diameter = 0.305, (0.012)
12
VBIAS=5V, TDFN2x3-14 Hole Size = 0.203, (0.008)
11 IOUT1=IOUT2 (k=1)
0.48
Output Current, IOUT1+IOUT2 (A)

10 1.3
(0.0192) (0.051)
9
8
0.25
7
(0.01)
6
5
4 100% On Time
3 90% On Time
2 70% On Time
1 50% On Time
0
-40 -35 -30 -25 -20 -15 -10 -5 0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 85
(0.098)
2.5

Ambient Temperature (oC)

0.4
Figure 4. Safe Operating Area for APL3523A Package (0.016)

0.9
(0.035)
0.2
(0.008) 0.2
(0.008)
TDFN2x3-14 Unit: mm, (Inch)

Copyright  ANPEC Electronics Corp. 16 www.anpec.com.tw

Rev. A.6 - May., 2017
APL3523A

Package Information
TDFN2x3-14
D A

Pin 1

b
E

A1
D2
A3

NX
aaa c
SEATING PLANE
Pin 1 Cornar

E2
e

K L

S TDFN2x3-14
Y
M MILLIMETERS INCHES
B
O
L MIN. MAX. MIN. MAX.
A 0.70 0.80 0.028 0.031

A1 0.00 0.05 0.000 0.002

A3 0.11 REF 0.004 REF

b 0.15 0.25 0.006 0.010

D 1.90 2.10 0.075 0.083

D2 0.80 1.00 0.031 0.039

E 2.90 3.10 0.114 0.122

E2 2.40 2.60 0.094 0.102

e 0.40 BSC 0.016 BSC

L 0.30 0.40 0.012 0.016

K 0.20 0.008

aaa 0.08 0.003

Copyright  ANPEC Electronics Corp. 17 www.anpec.com.tw

Rev. A.6 - May., 2017
APL3523A

Carrier Tape & Reel Dimensions

OD0 P0 P2 P1 A

E1
F

W
B0

K0 A0 A
OD1 B
B

SECTION A-A

T
SECTION B-B

d
H
A

T1

Application A H T1 C d D W E1 F
8.4+2.00 13.0+0.50
178.0±2.00 50 MIN. 1.5 MIN. 20.2 MIN. 8.0±0.20 1.75±0.10 3.50±0.05
-0.00 -0.20
TDFN2x3-14 P0 P1 P2 D0 D1 T A0 B0 K0
1.5+0.10
4.0±0.10 4.0±0.10 2.0±0.05 1.5 MIN. 0.25±0.05 2.30±0.20 3.30±0.20 1.00±0.20
-0.00

(mm)

Devices Per Unit

Package Type Unit Quantity
TDFN2x3-14 Tape & Reel 3000

Copyright  ANPEC Electronics Corp. 18 www.anpec.com.tw

Rev. A.6 - May., 2017
APL3523A

Taping Direction Information

TDFN2x3-14

USER DIRECTION OF FEED

Classification Profile

Copyright  ANPEC Electronics Corp. 19 www.anpec.com.tw

Rev. A.6 - May., 2017
APL3523A

Classification Reflow Profiles

Profile Feature Sn-Pb Eutectic Assembly Pb-Free Assembly
Preheat & Soak
100 °C 150 °C
Temperature min (Tsmin)
150 °C 200 °C
Temperature max (Tsmax)
60-120 seconds 60-120 seconds
Time (Tsmin to Tsmax) (ts)

Average ramp-up rate

3 °C/second max. 3°C/second max.
(Tsmax to TP)
Liquidous temperature (TL) 183 °C 217 °C
Time at liquidous (tL) 60-150 seconds 60-150 seconds
Peak package body Temperature
See Classification Temp in table 1 See Classification Temp in table 2
(Tp)*
Time (tP)** within 5°C of the specified
20** seconds 30** seconds
classification temperature (Tc)
Average ramp-down rate (Tp to Tsmax) 6 °C/second max. 6 °C/second max.

Time 25°C to peak temperature 6 minutes max. 8 minutes max.

* Tolerance for peak profile Temperature (Tp) is defined as a supplier minimum and a user maximum.
** Tolerance for time at peak profile temperature (tp) is defined as a supplier minimum and a user maximum.

Table 1. SnPb Eutectic Process – Classification Temperatures (Tc)

3 3
Package Volume mm Volume mm
Thickness <350 ≥350
<2.5 mm 235 °C 220 °C
≥2.5 mm 220 °C 220 °C
Table 2. Pb-free Process – Classification Temperatures (Tc)
3 3 3
Package Volume mm Volume mm Volume mm
Thickness <350 350-2000 >2000
<1.6 mm 260 °C 260 °C 260 °C
1.6 mm – 2.5 mm 260 °C 250 °C 245 °C
≥2.5 mm 250 °C 245 °C 245 °C

Reliability Test Program

Test item Method Description
SOLDERABILITY JESD-22, B102 5 Sec, 245°C
HOLT JESD-22, A108 1000 Hrs, Bias @ Tj=125°C
PCT JESD-22, A102 168 Hrs, 100%RH, 2atm, 121°C
TCT JESD-22, A104 500 Cycles, -65°C~150°C
HBM MIL-STD-883-3015.7 VHBM≧2KV
MM JESD-22, A115 VMM≧200V
Latch-Up JESD 78 10ms, 1tr≧100mA

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Rev. A.6 - May., 2017
APL3523A

Customer Service

Anpec Electronics Corp.

Head Office :
No.6, Dusing 1st Road, SBIP,
Hsin-Chu, Taiwan, R.O.C.
Tel : 886-3-5642000
Fax : 886-3-5642050

Taipei Branch :
2F, No. 11, Lane 218, Sec 2 Jhongsing Rd.,
Sindian City, Taipei County 23146, Taiwan
Tel : 886-2-2910-3838
Fax : 886-2-2917-3838

Copyright  ANPEC Electronics Corp. 21 www.anpec.com.tw

Rev. A.6 - May., 2017