Apl5325 Anpec

APL5325
Adjustable Low Dropout 300mA Linear Regulator
Features General Description
• Wide Operating Voltage: 3~6V The APL5325 is a P-channel low dropout linear regulator
• Low Dropout Voltage:

which needs only one input voltage from 3 to 6V, and
delivers current up to 300mA to set output voltage. It also
300mV(Typical) @ 300mA can work with low ESR ceramic capacitors and is ideal for
• Guaranteed 300mA Output Current using in the battery-powered applications such as note-
• Adjustable Output Voltage: 0.8~5.5V

book computers and cellular phones. Typical dropout volt-
age is only 300mV at 300mA loading.
• Current-Limit Protection with Foldback Current Current limit with current foldback and thermal shutdown
• Over-Temperature Protection functions protect the device against current over-loads
• Stable with Low ESR Ceramic Capacitor and over temperature. The APL5325 is available in a SOT-
23-5 package.
• SOT-23-5 Package
• Lead Free and Green Devices Available
(RoHS Compliant)
Pin Configuration
Applications SHDN 1 5 SET

GND 2
VIN 3 4 VOUT
• Cellular Phones
SOT-23-5
• Portable and Battery-Powered Equipment
• Notebook and Personal Computers
Simplified Application Circuit
APL5325
VIN VOUT
3 VIN VOUT 4
CIN 1 COUT
SHDN SET 5
GND
2
ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and
advise customers to obtain the latest version of relevant information to verify before placing orders.
Copyright  ANPEC Electronics Corp. 1 www.anpec.com.tw

Rev. A.1 - Nov., 2008
APL5325
Ordering and Marking Information

Package Code
APL5325 B: SOT-23-5
Operating Ambient Temperature Range
Assembly Material
I : -40 to 85 oC
Handling Code Handling Code
Temperature Range TR : Tape & Reel
Assembly Material
Package Code L : Lead Free Device
G : Halogen and Lead Free Device
APL5325 B: 25RX XXXXXX - Date Code
Note: ANPEC lead-free products contain molding compounds/die attach materials and 100% matte tin plate termination finish; which
are fully compliant with RoHS. ANPEC lead-free products meet or exceed the lead-free requirements of IPC/JEDEC J-STD-020C for
MSL classification at lead-free peak reflow temperature. ANPEC defines “Green” to mean lead-free (RoHS compliant) and halogen
free (Br or Cl does not exceed 900ppm by weight in homogeneous material and total of Br and Cl does not exceed 1500ppm by
weight).
Absolute Maximum Ratings (Note 1)
Symbol Parameter Rating Unit

VIN VIN Supply Voltage (VIN to GND) -0.3 ~ 6.5 V
VSHDN SHDN Input Voltage (SHDN to GND) -0.3 ~ 6.5 V
PD Power Dissipation Internally Limited W
o
TJ Junction Temperature -40 ~ 150 C
o
TSTG Storage Temperature -65 ~ 150 C
o
TSDR Maximum Lead Soldering Temperature, 10 Seconds 260 C
Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
Thermal Characteristics
Symbol Parameter Typical Value Unit
(Note 2)
Thermal Resistance-Junction to Ambient
θJA
o
240 C/W
SOT-23-5
Thermal Resistance-Junction to Case
θJC
o
130 C/W
SOT-23-5
Note 2 : θJA is measured with the component mounted on a high effective thermal conductivity test board in free air.
Recommended Operating Conditions

Symbol Parameter Range Unit
VIN VIN Supply Voltage 3~6 V
VOUT Output Voltage 0.8 ~ 5.5 V
IOUT VOUT Output Current 0 ~ 300 mA
CIN Input Capacitor 0.22 ~ 100 µF
COUT Output Capacitor 1.5 ~ 100 µF
o
TJ Junction Temperature -40 ~ 125 C

Rev. A.1 - Nov., 2008
APL5325
Electrical Characteristics
Unless otherwise specified, these specifications apply over VIN = VOUT+1V, IOUT=0~300mA, CIN = 1µF, COUT = 2.2µF, TA = -40 to 85oC.
Typical values are at TA = 25oC.
APL5325
Symbol Parameter Test Conditions Unit
Min. Typ. Max.
VIN Input Voltage 3 - 6 V
VOUT Output Voltage Range 0.8 - 5.5 V
IQ Quiescent Current IOUT =10mA ~300mA - 135 160 µA
VREF Reference Voltage Measured on SET, VIN=3V, IOUT=10mA - 0.8 - V
Output Voltage Accuracy IOUT=10mA -2 - +2 %
REGLINE Line Regulation ∆VOUT%/∆VIN, IOUT=10mA -0.06 - +0.06 %/V
REGLOAD Load Regulation ∆VOUT%/∆IOUT -0.2 - +0.2 %/A
VOUT = 2.5V, IOUT = 300mA - 500 650

VDROP Dropout Voltage mV
VOUT = 3.3V, IOUT = 300mA - 300 400
PSRR Power Supply Ripple Rejection Ratio f = 10kHz, IOUT = 300mA - 45 - dB
Noise f = 80Hz to 100kHz, IOUT = 300mA - 160 - µVRMS
ILIMIT Current Limit 450 550 - mA
ISHORT Foldback Current VOUT = 0V - 80 - mA
SHDN Input Voltage High 1.6 - -

V
SHDN Input Voltage Low - - 0.4
VOUT Discharge MOSFET RDS(ON) SHDN = Low - 60 - Ω
Shutdown VIN Supply Current SHDN = Low, VIN = 6V - 0.1 1 µA
SHDN Pull Low Resistance - 3 - MΩ

o
Over Temperature Threshold - 160 - C
o
Over Temperature Hysteresis - 40 - C
SET Input Bias Current VSET=0.8V -100 - 100 nA

Rev. A.1 - Nov., 2008
APL5325
Typical Operating Characteristics
Quiescent Current vs. Supply Voltage Quiescent Current vs. Junction Temperature
160 138
140 IOUT= 0mV

136
Quiescent Current, IQ (µA)
Quiescent Current, IQ (µA)

120
134
100
80 132
60
130
40
128
20
0 126
0 1 2 3 4 5 6 7 -50 -25 0 25 50 75 100 125
Supply Voltage, V IN (V) Junction Temperature, T J (o C)
PSRR vs. Frequency Dropout Voltage vs. Output Current

0 400
VIN=3.3V, VOUT=1.2V, 350 VOUT=3.3V
-10
Dropout Voltage, VDROP(mV)
COUT=2.2µF,IOUT=300mA
o
300 TJ=125oC TJ=75 C
-20
-30 250
PSRR(dB)
-40 200
-50 150
-60 100
TJ=-50oC
-70 50
TJ=25oC
-80 0
1000 10000 100000 0 100 200 300
Frequency(Hz) Output Current, I OUT(mA)
Dropout Voltage vs. Output Current Current Limit vs. Junction Temperature
700 600
VOUT=2.5V VIN=5V
600
Dropout Voltage, VDROP(mV)
TJ=75oC
Current Limit, ILIMIT(mA)
550
500 TJ=125oC
400
500
300
VIN=3.3V
200 o 450
TJ=-50 C
100 TJ=25oC
0 400
0 100 200 300 -50 -25 0 25 50 75 100 125
Output Current, IOUT(mA) Junction Temperature, T J(oC)

Rev. A.1 - Nov., 2008
APL5325
Typical Operating Characteristics (Cont.)
Loop Gain vs. Frequency Phase vs. Frequency

50 160
VIN=3.3V, VOUT=1.2V, VIN=3.3V, VOUT=1.2V,
40 CIN=1µF, COUT=2.2µF 140 CIN=1µF, COUT=2.2µF
30 IOUT=100mA IOUT=300mA
120
Phase (degree)
20 100
Loop Gain (dB)
10
80
0
60
-10
40 IOUT=100mA
-20 IOUT=300mA
20
-30
-40 0
1000 10000 100000 1000000 1000 10000 100000 1000000
Frequency (Hz)
Frequency (Hz)

Rev. A.1 - Nov., 2008
APL5325
Operating Waveforms
Enable Shutdown
SHDN SHDN
CH1 CH1
VIN VIN
CH2 CH2
VOUT VOUT
CH3 CH3
IOUT I OUT
CH4 CH4
CH1 : SHDN , 5V/div CH1 : SHDN , 5V/div

CH2 : VIN , 5V/div CH2 : VIN , 5V/div
CH3 : VOUT , 2V/div CH3 : VOUT , 2V/div
CH4 : IOUT , 100mA/div CH4 : IOUT , 100mA/div
Time : 200µs/div Time : 10µs/div
Load Transient Line Transient
V IN=5V ; C I N=1µF ; C IN=1 µF ; C OUT =2.2µF ;

C OUT =2.2µF ; T R =1µs T R =5µs ; I OUT =10mA
VOUT
CH1
V IN
I OUT VOUT
CH2
CH2 CH1
CH1 : VOUT , 50mV/div AC CH1 : VIN , 1V/div DC

CH2 : IOUT , 100mA/div CH2 : VOUT , 50mV/div AC
Time : 20µs/div Time : 20µs/div

Rev. A.1 - Nov., 2008
APL5325
Operating Waveforms (Cont.)
Power On Power Off
VIN VIN
CH1 CH1
VOUT VOUT
CH2 CH2
I OUT IOUT
CH3 CH3
CH1 : VIN , 2V/div CH1 : VIN , 2V/div

CH2 : VOUT , 2V/div CH2 : VOUT , 2V/div
CH3 : IOUT , 100mA/div CH3 : IOUT , 100mA/div
Time : 2ms/div Time : 10ms/div
Pin Description
PIN
FUNCTION
NO. NAME
1 SHDN Shutdown control pin, logic high: enable; logic low: shutdown.
2 GND Ground pin.
3 VIN Voltage supply input pin.
4 VOUT Regulator output pin.
5 SET Connect this pin to an external resistor divider to adjust output voltage.

Rev. A.1 - Nov., 2008
APL5325
Block Diagram
SHDN UVLO &

VIN
Shutdown
Logic
Thermal
Foldback
Shutdown - Current
+ Limit
0.8V
3MΩ
VOUT
SET
GND
Typical Application Circuit
VIN VOUT
3 4
VIN VOUT
1 5
CIN SHDN SET R1
COUT
1µF GND
2.2µF
2
Enable R2
Shutdown
 R1 
VOUT = 0.8 ⋅  1 + 
 R2 
Designation Supplier Part Number Specification

CIN Murata GRM185R61A105KE36 0603, X5R, 10V, 1µF
CIN Murata GRM188R71A105KA61 0603, X7R, 10V, 1µF
COUT Murata GRM188R61A225KE34 0603, X5R, 10V, 2.2µF
COUT Murata GRM188R71A225KE15 0603, X7R, 10V, 2.2µF
Reference: www.murata.com

Rev. A.1 - Nov., 2008
APL5325
Function Description
Output Voltage Regulation
The APL5325 is an adjustable low dropout linear

regulator. The output voltage set by the resistor-divider is
determined by:
 R1 
VOUT = 0.8 ⋅  1 + 
 R2 
Where R1 is connected from VOUT to SET with Kelvin

sensing and R2 is connected from SET to GND. The rec-
ommended value of R2 is in the range of 100 to100kΩ.
An error amplifier works with a temperature compensated
0.8V reference and an output PMOS regulates the output
to the presetting voltage. The error amplifier is designed
with high bandwidth and DC gain provides very fast tran-
sient response and less load regulation. It compares the
reference with the feedback voltage and amplifies the dif-
ference to drive the output PMOS which provides load
current from VIN to VOUT.
Thermal Shutdown
A thermal shutdown circuit limits the junction tempera-

ture of APL5325. When the junction temperature exceeds
+160οC, a thermal sensor turns off the output PMOS, al-
lowing the device to cool down. The regulator regulates
the output again through initiation of a new soft-start cycle
after the junction temperature is cooled down by 40oC.
The thermal shutdown is designed with a 40oC hyster-
esis to lower the average junction temperature during
continuous thermal overload conditions, extending life-
time of the device.
For normal operation, device power dissipation should
be externally limited so that junction temperature will not
exceed 125oC.
Shutdown Control
The APL5325 has an active-low shutdown function. Force

SHDN high (>1.6V) enables the VOUT; force SHDN low
(<0.4V) disables the VOUT. SHDN is internally pulled low
by a resistor (3mΩ typical). If it is not used, connect to VIN
for normal operation.

Rev. A.1 - Nov., 2008
APL5325
Application Information
Input Capacitor Operation Region and Power Dissipation
The APL5325 requires proper input capacitors to supply The APL5325 maximum power dissipation depends on
surge current during stepping load transients to prevent the thermal resistance and temperature difference be-
the input rail from dropping . Because the parasitic induc- tween the die junction and ambient air. The power dissi-
tor from the voltage sources or other bulk capacitors to pation PD across the device is:
the VIN limit the slew rate of the surge current, place the PD = (TJ - TA) / θJA
Input capacitors near VIN as close as possible. Input ca-
where (TJ-TA) is the temperature difference between the
pacitors should be larger than 1µF and a minimum ce-
junction and ambient air. θ JA is the thermal resistance
ramic capacitor of 1µF is necessary.
between Junction and ambient air. Assuming the
Output Capacitor TA=25 oC and maximum TJ=160 oC (typical thermal limit
The APL5325 needs a proper output capacitor to main- threshold), the maximum power dissipation is calcu-
tain circuit stability and to improve transient response over lated as:
temperature and current. In order to insure the circuit PD(max)=(160-25)/240
stability, the proper output capacitor value should be larger = 0.56(W)
than 2.2µF. With X5R and X7R dielectrics, 2.2µF is suffi- For normal operation, do not exceed the maximum junc-
cient at all operating temperatures. Large output capaci- tion temperature rating of TJ = 125 oC. The calculated power
tor value can reduce noise and improve load-transient dissipation should less than:
response and PSRR, however, it also affects power on PD =(125-25)/240
issue. Equation (1) shows the relationship between the = 0.41(W)
maximum COUT value and the VOUT. The GND provides an electrical connection to the ground
19.5
and channels heat away. Connect the GND to the ground
C OUT(max) = 101 −
VOUT by using a large pad or a ground plane.
Layout Consideration
Where the unit of COUT is µF and VOUT is V. Figure 1 shows
the curve of maximum output capacitor over the output Figure 2 illustrates the layout. Below is a checklist for
voltage. The output voltage range is from 0.8 to 5.5V and your layout:
the output capacitor value should under the line. Output 1. Please place the input capacitors close to the VIN.
capacitors must be placed at the load and the ground pin 2. Ceramic capacitors for load must be placed near the
as close as possible and the impedance of the layout load as close as possible.
must be minimized. 3. To place APL5325 and output capacitors near the load
is good for performance.
120
4. Large current paths, the bold lines in figure 2, must
110 have wide tracks.
Output Capacitor (µF)
100 5. Divider resistor R1 and R2 must be placed near the

SET as close as possible.
90
80
70
60
0 1 2 3 4 5 6
Output Voltage (V)
Figure 1

Rev. A.1 - Nov., 2008
APL5325
Application Information (Cont.)

Layout Consideration (Cont.)
CIN
APL5325
VIN
3
VIN
VOUT
4
VOUT
5
SET R1 COUT
GND
2 LOAD
R2
Figure 2
Recommended Minimum Footprint
SOT-23-5
0.076
0.1
0.05
0.038 0.02
Unit : Inch

Rev. A.1 - Nov., 2008
APL5325
Package Information
SOT-23-5
D
e
SEE
E1 VIEW A
E
b c
e1
0.25
A2
GAUGE PLANE
SEATING PLANE
A1
L
0
VIEW A
S SOT-23-5
Y
M MILLIMETERS INCHES
B
O
L MIN. MAX. MIN. MAX.
A 1.45 0.057
A1 0.00 0.15 0.000 0.006
A2 0.90 1.30 0.035 0.051
b 0.30 0.50 0.012 0.020
c 0.08 0.22 0.003 0.009
D 2.70 3.10 0.106 0.122
E 2.60 3.00 0.102 0.118
E1 1.40 1.80 0.055 0.071
e 0.95 BSC 0.037 BSC
e1 1.90 BSC 0.075 BSC
L 0.30 0.60 0.012 0.024
0 0° 8° 0° 8°
Note : 1. Follow JEDEC TO-178 AA.
2. Dimension D and E1 do not include mold flash, protrusions or gate
burrs. Mold flash, protrusion or gate burrs shall not exceed 10 mil
per side.

Rev. A.1 - Nov., 2008
APL5325
Carrier Tape & Reel Dimensions
OD0 P0 P2 P1 A
E1
F
W
B0
K0 A0 OD1 B A
B
SECTION A-A
T
SECTION B-B
d
H
A
T1
Application A H T1 C d D W E1 F
8.4+2.00 13.0+0.50
178.0±2.00 50 MIN. 1.5 MIN. 20.2 MIN. 8.0±0.30 1.75±0.10 3.5±0.05
-0.00 -0.20
SOT-23-5 P0 P1 P2 D0 D1 T A0 B0 K0
1.5+0.10 0.6+0.00
4.0±0.10 4.0±0.10 2.0±0.05 1.0 MIN. 3.20±0.20 3.10±0.20 1.50±0.20
-0.00 -0.40
(mm)
Devices Per Unit
Package Type Unit Quantity

SOT-23-5 Tape & Reel 3000

Rev. A.1 - Nov., 2008
APL5325
Taping Direction Information

SOT-23-5
USER DIRECTION OF FEED
Reflow Condition (IR/Convection or VPR Reflow)
TP tp
Critical Zone
TL to TP
Ramp-up
TL
tL
Temperature
Tsmax
Tsmin
Ramp-down
ts
Preheat
25
t 25°C to Peak
Time
Reliability Test Program
Test item Method Description
SOLDERABILITY MIL-STD-883D-2003 245°C, 5 sec
HOLT MIL-STD-883D-1005.7 1000 Hrs Bias @125°C
PCT JESD-22-B, A102 168 Hrs, 100%RH, 121°C
TST MIL-STD-883D-1011.9 -65°C~150°C, 200 Cycles
ESD MIL-STD-883D-3015.7 VHBM > 2KV, VMM > 200V
Latch-Up JESD 78 10ms, 1tr > 100mA

Rev. A.1 - Nov., 2008
APL5325
Classification Reflow Profiles

Profile Feature Sn-Pb Eutectic Assembly Pb-Free Assembly
Average ramp-up rate
3°C/second max. 3°C/second max.
(TL to TP)
Preheat
100°C 150°C
- Temperature Min (Tsmin)
150°C 200°C
- Temperature Max (Tsmax)
60-120 seconds 60-180 seconds
- Time (min to max) (ts)
Time maintained above:
183°C 217°C
- Temperature (TL)
- Time (tL)
Peak/Classification Temperature (Tp) See table 1 See table 2
Time within 5°C of actual
Peak Temperature (tp)
Ramp-down Rate 6°C/second max. 6°C/second max.
Time 25°C to Peak Temperature 6 minutes max. 8 minutes max.
Note: All temperatures refer to topside of the package. Measured on the body surface.
Table 1. SnPb Eutectic Process – Package Peak Reflow Temperatures
3 3
Volume mm Volume mm
Package Thickness
<350 ≥350
<2.5 mm 240 +0/-5°C 225 +0/-5°C
≥2.5 mm 225 +0/-5°C 225 +0/-5°C
Table 2. Pb-free Process – Package Classification Reflow Temperatures
3 3 3
Volume mm Volume mm Volume mm
Package Thickness
<350 350-2000 >2000
<1.6 mm 260 +0°C* 260 +0°C* 260 +0°C*
1.6 mm – 2.5 mm 260 +0°C* 250 +0°C* 245 +0°C*
≥2.5 mm 250 +0°C* 245 +0°C* 245 +0°C*
* Tolerance: The device manufacturer/supplier shall assure process compatibility up to and including the stated
classification temperature (this means Peak reflow temperature +0°C. For example 260°C+0°C) at the rated MSL
level.
Customer Service
Anpec Electronics Corp.

Head Office :
No.6, Dusing 1st Road, SBIP,
Hsin-Chu, Taiwan, R.O.C.
Tel : 886-3-5642000
Fax : 886-3-5642050
Taipei Branch :
2F, No. 11, Lane 218, Sec 2 Jhongsing Rd.,
Sindian City, Taipei County 23146, Taiwan
Tel : 886-2-2910-3838
Fax : 886-2-2917-3838

Rev. A.1 - Nov., 2008

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APL5325

Adjustable Low Dropout 300mA Linear Regulator

Features General Description

• Low Dropout Voltage:

• Adjustable Output Voltage: 0.8~5.5V

Applications SHDN 1 5 SET

Simplified Application Circuit

Copyright  ANPEC Electronics Corp. 1 www.anpec.com.tw

Ordering and Marking Information

APL5325 B: 25RX XXXXXX - Date Code

Absolute Maximum Ratings (Note 1)

Symbol Parameter Rating Unit

Recommended Operating Conditions

Copyright  ANPEC Electronics Corp. 2 www.anpec.com.tw

VIN Input Voltage 3 - 6 V

VOUT Output Voltage Range 0.8 - 5.5 V

IQ Quiescent Current IOUT =10mA ~300mA - 135 160 µA

VREF Reference Voltage Measured on SET, VIN=3V, IOUT=10mA - 0.8 - V

Output Voltage Accuracy IOUT=10mA -2 - +2 %

REGLINE Line Regulation ∆VOUT%/∆VIN, IOUT=10mA -0.06 - +0.06 %/V

REGLOAD Load Regulation ∆VOUT%/∆IOUT -0.2 - +0.2 %/A

VOUT = 2.5V, IOUT = 300mA - 500 650

PSRR Power Supply Ripple Rejection Ratio f = 10kHz, IOUT = 300mA - 45 - dB

Noise f = 80Hz to 100kHz, IOUT = 300mA - 160 - µVRMS

ILIMIT Current Limit 450 550 - mA

ISHORT Foldback Current VOUT = 0V - 80 - mA

SHDN Input Voltage High 1.6 - -

VOUT Discharge MOSFET RDS(ON) SHDN = Low - 60 - Ω

Shutdown VIN Supply Current SHDN = Low, VIN = 6V - 0.1 1 µA

SHDN Pull Low Resistance - 3 - MΩ

Copyright  ANPEC Electronics Corp. 3 www.anpec.com.tw

Typical Operating Characteristics

140 IOUT= 0mV

Quiescent Current, IQ (µA)

PSRR vs. Frequency Dropout Voltage vs. Output Current

Copyright  ANPEC Electronics Corp. 4 www.anpec.com.tw

Typical Operating Characteristics (Cont.)

Loop Gain vs. Frequency Phase vs. Frequency

Copyright  ANPEC Electronics Corp. 5 www.anpec.com.tw

CH1 : SHDN , 5V/div CH1 : SHDN , 5V/div

Load Transient Line Transient

V IN=5V ; C I N=1µF ; C IN=1 µF ; C OUT =2.2µF ;

CH1 : VOUT , 50mV/div AC CH1 : VIN , 1V/div DC

Copyright  ANPEC Electronics Corp. 6 www.anpec.com.tw

Operating Waveforms (Cont.)

Power On Power Off

CH1 : VIN , 2V/div CH1 : VIN , 2V/div

Copyright  ANPEC Electronics Corp. 7 www.anpec.com.tw

SHDN UVLO &

Typical Application Circuit

Designation Supplier Part Number Specification

Copyright  ANPEC Electronics Corp. 8 www.anpec.com.tw

Output Voltage Regulation

The APL5325 is an adjustable low dropout linear

Where R1 is connected from VOUT to SET with Kelvin

A thermal shutdown circuit limits the junction tempera-

The APL5325 has an active-low shutdown function. Force

Copyright  ANPEC Electronics Corp. 9 www.anpec.com.tw

Input Capacitor Operation Region and Power Dissipation