Colegio de Sta, Teresa de Avila Foundation Inc.: ITEC008 (Computer Hardware Servicing)

Colegio De Sta, Teresa de Avila Foundation Inc.
6 Kingfisher Corner Skylark Streets, Zabarte Subdivision

Novaliches, Quezon City 1123 Philippines
Telephone : 939-6983 / 939-91-36 Telefax : 930-57-85
COURSE SYLLABUS
I. Course Code : ITEC006
II. Course Title : Computer Organization
III. No. of Units : 3
IV. Pre-requisite: ITEC004 (Advance Programming), ITEC008 (Computer Hardware

Servicing)
V. Course Description:
This course provides an overview of the architecture and organization of a

computer. It deals with the general microprocessor organization, implementation of
arithmetic algorithms, input- output peripherals, memory organization, and basic
interfacing of these devices. Assembly language programming will be covered, as well, in
the laboratory.
VI. Objective:
1. Discuss the characteristics of low-level and high-level languages.
2. Describe the basic operational concepts of the CPU.
3. Differentiate logical memory and physical memory.
4. Identify the different addressing modes.
5. Identify and apply the different data transfer, arithmetic, shift, rotate, conditional jump,
and loop instructions.
6. Apply the programming techniques.
7. Write assembly programs using the different techniques.
VII. Course Outline:
Week Hours Topics Methodology

1 3 Course Orientation  Discussion
Basic Structure of Computer  Demonstration
Hardware and Software  Laboratory Exercises
 What is a Digital Computer
 Types of Computers
 Basic Functional Units of a
Computer System
 Input Unit
 Memory Unit - Primary
 Memory Divisions
 Memory Unit - Secondary
 Processing Unit
 Output Unit
 Basic Concepts of Computer
Architecture
 Types of Programming
Languages Characteristics of
Low-Level and High-Level
Languages
2 3  How to Fetch/Read Data or  Discussion
Instruction from MM  Demonstration
 How to Write/Store Data or  Laboratory Exercises
Instruction into MM
 Connections Between the MM
and the CPU
 Operating Steps
Basic Operational Concepts
 Bus Structures
 Single Bus Structure
 Two-Bus Structure
 Memory Locations and
Addresses Parts of an Instruction
 Main Memory Operations
 Instructions and Instructions
Sequencing
 Address Notations
 Two-Phase Procedure in
Instruction Execution
3 3 8088/8086 Architecture  Discussion
 History of the Intel  Demonstration
Microprocessors  Laboratory Exercises
 8086/8088 CPU Architecture
8086/8088 Bus Structure
 Logical and Physical Memory
 Register Structure of the
8086/8088
 General Purpose Registers
 Pointer and Index Registers
 Status Register or Processor
Status Word Conditional Flags
 Examples
 Control Flags
 Memory Segmentation
 Generating a Memory Address
4 3 Memory Segments  Discussion
 Type of Segments  Demonstration
Stack  Laboratory Exercises
 Pushing a Data onto the Stack
 Popping a Data onto the Stack
 Exercise on Stack Operation
 Addressing Modes
 Register Addressing
 Immediate Addressing
 Direct Addressing
 Register Indirect Addressing
 Register Relative Addressing or
 Base Addressing
 Base-Plus-Index Addressing
 Base-Relative-Plus-Index
Addressing
 Exercise on Addressing Models
5 3 PRELIM EXAMINATIONS
6 3 Data Transfer Instructions  Discussion
 Classification of Instructions  Demonstration
 MOV Instruction  Laboratory Exercises
 XCHG Instruction
 Exercise 1
 Quiz 1
 PUSH Instruction
 Exercise 2
 POP Instruction
 Exercise 3
 Quiz 2
 LEA Instruction
 Exercise 4
 Data Transfer Instruction
Exercise
7 3 Arithmetic Instructions  Discussion
 Review of Some Concepts  Demonstration
Regarding the Binary Number  Laboratory Exercises
System
 The ADD Instruction
 Exercise 1
 ADC Instruction
 Exercise 2
 The INC Instruction
 The DAA Instruction
 The AAA Instruction
 The SUB Instruction
 The SBB Instruction
 The DEC Instruction
 The DAS Instruction
 The AAS Instruction
8 3 Arithmetic Instructions (cont.)  Discussion
Logic Instructions  Demonstration
 The NEG Instruction  Laboratory Exercises
 The CMP Instruction
 Program Tracing Example 1
 The AND Instruction
 The OR Instruction
 The XOR Instruction
 The NOT Instruction
 The TEST Instruction
 Logic Instruction Program
 Tracing Example
 Program Tracing Exercise 1
9 3 Shift Instructions  Discussion
 The SHL/SAL Instructions  Demonstration
 Exercise – SHL/SAL  Laboratory Exercises
 The SHR Instruction
 Exercise – SHR Instruction
 The SAR Instruction
 Exercise – SAR Instruction
 Shift Instruction Exercise
 Quiz – Shift Instructions
 Program Tracing Example
 Program Tracing Exercise
10 3 MIDTERM EXAM
11 3 Rotate Instructions  Discussion
 The ROL Instruction  Demonstration
 The ROR Instruction Exercise  Laboratory Exercises
 The RCL Instruction
 The RCR Instruction
 Quiz - Rotate Instructions
 Program Tracing Exercise
12 3 Flag Control and Jump  Discussion
Instructions  Demonstration
 Control Transfer Instructions  Laboratory Exercises
 The JMP Instruction
 JMP Instruction Example
13 3 Conditional Jump and Loop  Discussion
Instructions  Demonstration
 The Jcc Instructions  Laboratory Exercises
 Jcc Instruction Example
 The JCXZ Instruction
 The Loop Instruction
 The LOOPE/LOOPZ Instruction
 The LOOPNE/LOOPNZ
Instruction
14 3 PREFINAL EXAMINATIONS
15 3 String Instructions  Discussion
 String Prefix  Demonstration
 Data Movement String  Laboratory Exercises
Instructions
 Data Movement String
Instructions (cont)
 Data Scanning and Comparison
 Sample Program on Strings
16 3  Assembly Language  Discussion
Programming Techniques  Demonstration
 Assembly Language  Laboratory Exercises
Programming Techniques cont…
 Assembly Language
Programming Techniques cont…
17 3  Assembly Language  Discussion
Programming Techniques  Demonstration
 Assembly Language  Laboratory Exercises
Programming Techniques
Other 8088/8086 Instructions cont…
18 3 FINAL EXAMINATIONS
VIII. Grading System:
The following percentage distribution shall be followed :
Prelims - 25%
Midterm - 25%
Prefinals - 25%
Finals - 25%
------------------------
100%
The following are the required periodic grade components for this course
Lecture
Class Participation 20%

Quizzes 30%
Periodical Examinations 50%
------------------------
100%
Laboratory
Laboratory Exercises 100%
IX. Course Requirements
1. Class Participation
2. Laboratory Exercises
3. Quizzes
4. Major Examinations
X. References
1. Linda Null & Julia Cobur, Computer Organization and Architecture, 2006
2. John D. Carpinelli, Computer Systems Organization and Architecture, 2001
3. V. Carl Hamacher, Zvonko G. Vrabesic, Sakwat G. Zaky, Computer Organization,

1990
Prepared by:
HAROLD R. LUCERO, MIT

Program Chair – IT Department
Approved by:
REMEDIOS C. ROSAL, ED.D.

College Dean

Colegio de Sta, Teresa de Avila Foundation Inc.: ITEC008 (Computer Hardware Servicing)

Uploaded by

Copyright:

Available Formats

Colegio de Sta, Teresa de Avila Foundation Inc.: ITEC008 (Computer Hardware Servicing)

Uploaded by

Document Information

Original Title

Copyright

Available Formats

Share this document

Share or Embed Document

Sharing Options

Did you find this document useful?

Is this content inappropriate?

Copyright:

Available Formats

Colegio de Sta, Teresa de Avila Foundation Inc.: ITEC008 (Computer Hardware Servicing)

Uploaded by

Copyright:

Available Formats

Colegio De Sta, Teresa de Avila Foundation Inc.

6 Kingfisher Corner Skylark Streets, Zabarte Subdivision

I. Course Code : ITEC006

II. Course Title : Computer Organization

III. No. of Units : 3

IV. Pre-requisite: ITEC004 (Advance Programming), ITEC008 (Computer Hardware

This course provides an overview of the architecture and organization of a

VII. Course Outline:

Week Hours Topics Methodology

VIII. Grading System:

The following percentage distribution shall be followed :

Class Participation 20%

Laboratory Exercises 100%

IX. Course Requirements

2. John D. Carpinelli, Computer Systems Organization and Architecture, 2001

3. V. Carl Hamacher, Zvonko G. Vrabesic, Sakwat G. Zaky, Computer Organization,

HAROLD R. LUCERO, MIT

REMEDIOS C. ROSAL, ED.D.

You might also like