Xilinx

Abstract: - As innovation shrink, the force scattered by the connections of a network-on-chip (NoC) begins to imitate with the force dispersed by alternate components like as switches and the network interfaces (NIs).In this venture Cartesian switch is outlined keeping in mind the end goal to diminish the force dissipation. Cartesian switch is a composite of gatherer and arterials. A gatherer is a 'horizontal network' connecting authority switches, while a blood vessel is a 'vertical network' that divide gatherers. Authority switches has an east and a west port, connecting the switch to its gatherer, while blood vessel switches have sufficient ports to permit connection to its authorities and its arterials. To guarantee connectivity, a blood vessel is not allowed to diversion a gatherer. Every switch is given a location that indicate its location in Cartesian space (spoke to, for instance, utilizing scope and longitude); inside an authority, all gatherer switches offer common scope. At last we choose that the port transition of double information between the ports are proficient in NOC application for exchange the information rates in effective way and it additionally lessened Area of the switch. At long last the Cartesian switch will be actualized by utilizing FPGA Kit.

Réaliser des programmes en  VHDL  d’un  multiplexeur  4  vers  1  en  utilisant  les  deux instructions  conditionnelle  et  sélective,  ainsi  décrire  en  VHDL  une  bascule  D, puis  une  unité  arithmétique  et  logique  (UAL)  puis  un  Compteur  synchrone  et asynchrone.

This paper presents an efficient approach for the implementation of typical communication structures studied in class. This scheme is beneficial where the objective is to implement the physical working of complex DSP or communication structures or algorithms without requiring detailed knowledge of hardware design and hardware description languages. The approach is based on the Xilinx System Generator for DSP tool, which integrates itself with the MATLAB, based Simulink Graphics environment and relieves the user of the textual HDL programming. The purposed design is the QPSK modulator which is then simulated using Matlab/ Simulink environment and System Generator, FPGA design as well as implemented on a Spartan 3 (xc3s-5ft256) Spartan3 starter kit board. The modulator algorithm has been implemented on FPGA using the VHDL language on Xilinx ISE Design suite 13.2.

The sensing of water level in various places (like water tank and boilers in the thermal plants) is done for safety purpose and for domestic use. The sensor is used to measure the water level. The output of sensor is then given to FPGA board to convert the physical data (AC or DC voltage) to digital data to do further processing on the board, then the water level is indicated on the board and based on the water level the pump is turned on or off. This system can be implemented in the river, boiler and in the thermal plants in such a way that the sensor will able to detect the water level at any time. The main motive behind the design of the system are indigenous system, low cost, low power consumption, easy installation process, highly reliable.

Pipelining is a technique that exploits parallelism, among the instructions in a sequential instruction stream to get increased throughput, and it lessens the total time to complete the work.. The major objective of this architecture is to design a low power high performance structure which fulfils all the requirements of the design. The critical factors like power, frequency, area, propagation delay are analysed using Spartan 3E XC3E 1600e device with Xilinx tool. In this paper, the 32-bit MIPS RISC processor is used in 6-stage pipelining to optimize the critical performance factors. The fundamental functional blocks of the processor include Input/Output blocks, configurable logic blocks, Block RAM, and Digital clock Manager and each block permits to connect to multiple sources for the routing. The Auxiliary units enhance the performance of the processor. The comparative study elevates the designed model in terms of Area, Power and Frequency. MATLAB2D/3D graphs represents the relationship among various parameters of this pipelining. In this pipeline model, it consumes very less power (0.129 W),path delay (11.180 ns) and low LUT utilization (421). Similarly, the proposed model achieves better frequency increase (285.583 Mhz.), which obtained better results compared to other models.

This paper presents the methods to reduce dynamic
power consumption of a digital Finite Imppulse Respanse (FIR)
filter these mrthods include low power serial multiplier and
serial adder, combinational booth multiplier, shift/add
multipliers, folding transformation in linear pheas
architecture and applied to fir filters to power consumption
reduced thus reduce power consumption due to glitching is
also reduced. The minimum power achieved is 110mw in fir
filter based on shift/add multiplier in 100MHZ to 8taps and
8bits inputs and 8bits coefficions. The proposed FIR filters
were synthesized implemented using Xilinx ISE Virtex IV

The UART (universal asynchronous receiver and transmitter) module provides asynchronous serial communication with external devices such as modems and other computers. The UART can be used to control the process of breaking parallel data from the PC down into serial data that can be transmitted and vice versa for receiving data. The UART allows the devices to communicate without the need to be synchronized. In the proposed design the communication is done securely by introducing DES Cryptography module by performing both s the encryption and decryption process for providing the security for the data which should be transmitted. So by this project we are able to transmit the data with low cost and with high security. Modern applications of DES cover a wide variety of applications, such as secure internet (ssl), electronic financial transactions, remote access servers, cable modems, secure video surveillance and encrypted data storage. The functionality is verified through ISE simulator and the synthesis is carried out by XILINX ISE 12.3i using verilog HDL.

Tez çalışması, uydu haberleşme sistemleri aracılığıyla yapılan sayısal video yayınlarının alıcı tarafında kulanılan ileri hata düzeltme birimi tasarımı ve gerçeklemesini kapsamaktadır. Bu kapsamda Avrupa Telekominikasyon Standardı Enstitüsü (ETSI) tarafından İkinci Nesil Sayısal Video Yayını (DVB-S2) için belirtilen standartlar göz önüne alınmıştır. Alıcı tarafı DVB-S2 ileri hata kod çözücü birimi standartlar incelenerek ve daha önceki çalışmalar dikkate alınarak tasarlanmış ve VHDL kodları yazılarak donanımsal olarak gerçeklenmiş MODELSIM yardımıyla benzetimleri yapılmış ve MATLAB yardımıyla da doğrulanmıştır.
BCH kod çözücüsü tasarımında hızlı aynı zamanda kapladığı alan açısından da az ve esnek bir yapı oluşturulmuştur. Dışarıdan set edilebilen parametrelerle değişik veri uzunluklarına uyumlu bir tasarım yapılmıştır. Hata belirteci(syndrome) hesaplamada paralel GF çarpıcıları kullanılırak hızlı olması sağlanmıştır. Anahtar eşitlik çözücüde gecikmenin ve kritik yol beklemesinin(Critical path delay) en az olması için RiBM (Reformulated inverse-free Berlekamp-Massey) algoritması kullanılmıştır. Fifo büyüklükleri dışarıdan set edilebilecek şekilde esnek yapılmıştır.
LDPC kod çözücü yapısında hızlı haberleşme sistemleri için ideal olan belief propagation yöntemi seçilmiş literatürden farklı olarak karmaşıklığı ve kapladığı alanı azaltmak amacıyla min-sum algoritması kullanılmıştır. Tekrar hız açısından verimli olması amacıyla düzenli H matrisi güvenilir bir kaynaktan kenar tablosu alınarak oluşturulmuştur. İterasyon sayısı, mod kodu, veri uzunlukları dışarıdan girilebilecek şekilde yapılarak hertürlü(yer ya da hız) kısıt için optimum ayarlanabilecek bir tasarım oluşturulmuştur. Gerek hız gerek yer açısından bit ve kontrol noktaları RAM leri 360 bitlik gruplara ayrılarak kısmi paralel bir yapı oluşturulmuştur. Hesaplanan LLR değerlerinden sadece 2 si tutularak literatürdekilere göre yerden kazanç sağlanmıştır. Yumuşak karar LDPC kodu kullanılarak yerden tasarruf sağlanmış kodlama performansı artırılmıştır.

The top module or sub-module of a project in the Vivado Design Suite can be packaged as an IP and it is available in the IP repository of the Vivado IP catalog for reuse. This paper exhibit how chosen modules in an RTL project can be packaged as IP for reuse. IP packaging is IP-XACT-compliant, where IP-XACT is a XML format that defines and describes electronic components and their designs. IP packaging also allows for different file sets to be part of the package. These file sets include simulation, test bench, example design, XDC constraints, and documents. Objectives  Select a sub module in an RTL project and begin IP packaging  Select a repository location to create the new IP designation  State basic options for IP packaging  Define IP interfaces from the ports  Specify IP customization parameters  Add or remove files to/from many of the possible file groups throughout during packaging I. INTRODUCTION The Vivado Design Suite provides an IP-centric design flow that helps you to quickly turn the designs and algorithms into reusable IP. The Vivado IP Catalog is a united IP repository that provides the framework for the IP-centric design flow. This catalog consolidates IP's from all sources including Xilinx® IP, thirdparty IP, and end-user designs targeted for reuse as IP into a single environment. The Vivado IP packager tool is a unique design reuse feature, which is based upon the IP-XACT standard. The IP packager tool provides you with the facility to package a design at any phase of the design flow and deploy the core as system-level IP. In this paper, I define a new custom IP from an active Vivado project, using the Create and Package IP wizard. Start with an existing design project in the Vivado IDE, define identification information for the new IP, add documentation to support its use, and add the IP to the IP Catalog. After packaging, you verify the new IP through synthesis in a separate design project. The project contains Verilog source files for a simple UART interface. The existing design includes timing constraints defined in an XDC file (uart_top.xdc). These constraints were defined for the UART design as a standalone design. However, when packaged as an IP, the design inherits some of the needed constraints from the parent design. In this case, you must modify the XDC file to separate constraints the IP requires when used in the context of a parent design, and the constraints the IP requires when used out-of-context (OOC) in a standalone capacity. This requires splitting the current XDC file. We should prepare the design constraints prior to packaging the design for inclusion in the IP catalog; however, we can also perform these steps after packaging the IP.

The huge datacenters in the world - used in the social networks, researching and computing centers, and storage devices - have faced fundamental problem reflected in the need for high throughput to switch between the large numbers of virtual machines installed in these datacenters. The increased use of cloud applications will increase the need for greater numbers of virtual machines. In order to meet the requirements of this increase, it must be increased the hardware capabilities in the datacenters, through increasing the number of cores in the servers. Therefore, there is a need to provide network architecture that can connect all of these cores and chips very quickly. Consequently, it is necessary to enhance the virtual switching system to achieve the maximum integration and efficiency between the network segments, and analysis the scheduling and virtual queuing algorithms depending on the decisions from the experiences implemented using high-level source code and hardware description scheme with Xilinx platform.

This paper proposes a low power architecture for second order digital phase-locked loop (DPLL). High power consumption of DPLL results from using a look-up table (LUT) in implementing the numerically controlled oscillator (NCO). A new design for NCO is presented in which no LUT is used. Proposed architecture implemented using field programmable gate array (FPGA) consumed 15.44 mw at 100 MHz clock frequency which means a more than 25% saving in power consumption compared to traditional NCO. Furthermore, proposed method also saves FPGA resources and works at faster clock frequency.

The digital Finite-Impulse-Response (FIR) filters are mainly employed in digital signal processing applications. The main components of digital FIR filters designed on FPGAs are the register bank to save the samples of signals, adder to implement sum operations and multiplier for multiplication of filter coefficients to signal samples. Although, design and implementation of digital FIR filters seem simple but the design bottleneck is multiplier block for speed, power consumption and FPGA chip area occupation. The multipliers are an integral part in FIR structures and these use a large part of the chip area. This limits the number of processing elements (PE) available on the chip to realize a higher order of filter. A model is developed in the Matlab/Simulink environment to investigate the performance of the desired higher order FIR filter. An equivalent FIR filter representation is designed by the Xilinx FIR Compiler by using the exported FIR filter coefficients. The Xilinx implementation flow is completed with the help of Xilinx ISE 14.5. It is observed how the use of higher order FIR filter impacts the resource utilization of the FPGA and it's the maximum operating frequency. Keyword: Fir filter FPGA Higher order fir filter Xilinx

The addition of two binary numbers is the most fundamental and widely used
arithmetic operation. This operation is used in microprocessors, digital signal
processors, data processing application specific integrated circuits and many more.
ETA (Error Tolerant Adder) is an efficient adder which speeds up binary addition.
There is a huge improvement in the power and speed when we use an ETA. For
increasing the speed and decreasing the power dissipation, we use the logic that in an
adder circuit the delay appears mainly because of the carry propagation and also
there is a lot of power dissipation. Design of ETA is done using backend tool under
real time simulation conditions and then compares the performance of the ETA in
terms of accuracy, delay and power consumption with that of conventional adders.
The proposed architecture is then implemented using FPGA.

Error correction is an integral part of any communication system and for this purpose, the convolution codes are widely used as forward error correction codes. For decoding of convolution codes, at the receiver end Viterbi Decoder is being employed. The parameters of Viterbi algorithm can be changed to suit a specific application. The high speed and small area are two important design parameters in today’s wireless technology. In this paper, a high speed feed forward viterbi decoder has been designed using hybrid track back and register exchange architecture and embedded BRAM of target FPGA. The proposed viterbi decoder has been designed with Matlab, simulated with Xilinx ISE 8.1i Tool, synthesized with Xilinx Synthesis Tool (XST), and implemented on Xilinx Virtex4 based xc4vlx15 FPGA device. The results show that the proposed design can operate at an estimated frequency of 107.7 MHz by consuming considerably less resources on target device to provide cost effective solution for wireless applications.

This paper presents FPGA realizations of Walsh transforms. The realizations are targetted for the system of arbitrary waveform generation, addition/ subtraction, multiplication, and processing of several signals based on Walsh transforms which is defined in term products of Rademacher functions. Input signals are passing through the system in serial, the output either signals or coefficients are also passing out in serial. To minimize the area utilization when the systems are realized in FPGA chips, the word lengths of every processing step have been designed carefully. Based on this, FPGA realizations of those various applications into Xilinx and Altera chips have been done. In Xilinx realizations, Xilinx ISE was used to display the results and to extract some critical parameters such as speed and static power. Meanwhile, the realizations into Altera chips have been conducted using Quartus. Comparisons of speed and power among Xilinx and Altera chip realizations are presented here ...

In This paper provides the performances of adder’s circuit is proposed. The adder circuit is a very familiar method for optimizing speed, surface area. The area, speed is also important parameter to determine the performance of the system. In this paper, the full adder and half adder circuit cells are converting MUX and NAND gates. This type of adders used for design of field programmable gate arrays (FPGA).Simulations can be done by Xilinx 13.1i and layouts for MICROWIND EDA tool with supply voltage 1.8v.

The addition of two binary numbers is the most fundamental and widely used
arithmetic operation. This operation is used in microprocessors, digital signal
processors, data processing application specific integrated circuits and many more.
ETA (Error Tolerant Adder) is an efficient adder which speeds up binary addition.
There is a huge improvement in the power and speed when we use an ETA. For
increasing the speed and decreasing the power dissipation, we use the logic that in an
adder circuit the delay appears mainly because of the carry propagation and also
there is a lot of power dissipation. Design of ETA is done using backend tool under
real time simulation conditions and then compares the performance of the ETA in
terms of accuracy, delay and power consumption with that of conventional adders.
The proposed architecture is then implemented using FPGA.

Future wireless communication system have to be designed to integrate features such as high data rates, high quality of service and multimedia in the existing communication framework. Increased demand in wireless communication system has led to demand for higher network capacity and performance. Higher bandwidth, optimized modulation offer practically limited potential to increase the spectral efficiency. Hence MIMO systems utilizes space multiplex by using array of antenna’s for enhancing the efficiency at particular utilized bandwidth. MIMO use multiple inputs multiple outputs from single channel. These systems defined by spectral diversity and spatial multiplexing. The aim of this paper is to design and implement of channel estimation method and modulation technique for MIMO system. The design specifications are obtained using MATLAB. The RTL coding is carried for the design to be implemented on Xilinx FPGA.

The digital Finite-Impulse-Response (FIR) filters are mainly employed in digital signal processing applications. The main components of digital FIR filters designed on FPGAs are the register bank to save the samples of signals, adder to implement sum operations and multiplier for multiplication of filter coefficients to signal samples. Although, design and implementation of digital FIR filters seem simple but the design bottleneck is multiplier block for speed, power consumption and FPGA chip area occupation. The multipliers are an integral part in FIR structures and these use a large part of the chip area. This limits the number of processing elements (PE) available on the chip to realize a higher order of filter. A model is developed in the Matlab/Simulink environment to investigate the performance of the desired higher order FIR filter. An equivalent FIR filter representation is designed by the Xilinx FIR Compiler by using the exported FIR filter coefficients. The Xilinx implemen...

The digital Finite-Impulse-Response (FIR) filters are mainly employed in digital signal processing applications. The main components of digital FIR filters designed on FPGAs are the register bank to save the samples of signals, adder to implement sum operations and multiplier for multiplication of filter coefficients to signal samples. Although, design and implementation of digital FIR filters seem simple but the design bottleneck is multiplier block for speed, power consumption and FPGA chip area occupation. The multipliers are an integral part in FIR structures and these use a large part of the chip area. This limits the number of processing elements (PE) available on the chip to realize a higher order of filter. A model is developed in the Matlab/Simulink environment to investigate the performance of the desired higher order FIR filter. An equivalent FIR filter representation is designed by the Xilinx FIR Compiler by using the exported FIR filter coefficients. The Xilinx implemen...

Pipelining is a technique that exploits parallelism, among the instructions in a sequential instruction stream to get increased throughput, and it lessens the total time to complete the work.. The major objective of this architecture is to design a low power high performance structure which fulfils all the requirements of the design. The critical factors like power, frequency, area, propagation delay are analysed using Spartan 3E XC3E 1600e device with Xilinx tool. In this paper, the 32-bit MIPS RISC processor is used in 6-stage pipelining to optimize the critical performance factors. The fundamental functional blocks of the processor include Input/Output blocks, configurable logic blocks, Block RAM, and Digital clock Manager and each block permits to connect to multiple sources for the routing. The Auxiliary units enhance the performance of the processor. The comparative study elevates the designed model in terms of Area, Power and Frequency. MATLAB2D/3D graphs represents the relationship among various parameters of this pipelining. In this pipeline model, it consumes very less power (0.129 W),path delay (11.180 ns) and low LUT utilization (421). Similarly, the proposed model achieves better frequency increase (285.583 Mhz.), which obtained better results compared to other models.

This paper presents FPGA realizations of Walsh transforms. The realizations are targetted for the system of arbitrary waveform generation, addition/ subtraction, multiplication, and processing of several signals based on Walsh transforms which is defined in term products of Rademacher functions. Input signals are passing through the system in serial, the output either signals or coefficients are also passing out in serial. To minimize the area utilization when the systems are realized in FPGA chips, the word lengths of every processing step have been designed carefully. Based on this, FPGA realizations of those various applications into Xilinx and Altera chips have been done. In Xilinx realizations, Xilinx ISE was used to display the results and to extract some critical parameters such as speed and static power. Meanwhile, the realizations into Altera chips have been conducted using Quartus. Comparisons of speed and power among Xilinx and Altera chip realizations are presented here even though this is not an apple to apple comparison. Finally, it can be concluded that Walsh transforms can be realized not only for the applications that have been done here, but it is potential can be used for other applications.

the huge datacenters in the world used in the social networks, researching and computing centers, and storage devices have faced fundamental problem reflected in the need for high throughput to switch between the large numbers of virtual machines installed in these datacenters. The increased use of cloud applications will increase the need for greater numbers of virtual machines. In order to meet the requirements of this increase, it must be increased the hardware capabilities in the datacenters, through increasing the number of cores in the servers. Therefore, there is a need to provide network architecture that can connect all of these cores and chips very quickly. Consequently, it is necessary to enhance the virtual switching system to achieve the maximum integration and efficiency between the network segments, and analysis the scheduling and virtual queuing algorithms depending on the decisions from the experiences implemented using high-level source code and hardware descriptio...

The elimination of noise from images becomes a trending field in image processing. Images may get corrupted by random change in pixel intensity, illumination, or due to poor contrast and can’t be used directly. Subsidiary information from such images are extracted by removing the noise, sharpening contrast and detection of the edges by using several filtering techniques. Median filtering is one such nonlinear based method which removes range isolated noise like salt & pepper noise while preserving the edge information. Its miles a computationally intensive operation, so it is hard to put into effect it in actual time. This system introduces a brand-new structure and optimizations for its implementation with FPGAs. The practical consequences show the effectiveness of our improvements allowing actual-time processing and a minimal use of sources. FPGA result is validated by implementing the above algorithm in MATLAB when the images are corrupted by noise models.

The addition of two binary numbers is the most fundamental and widely used arithmetic operation. This operation is used in microprocessors, digital signal processors, data processing application specific integrated circuits and many more. ETA (Error Tolerant Adder) is an efficient adder which speeds up binary addition. There is a huge improvement in the power and speed when we use an ETA. For increasing the speed and decreasing the power dissipation, we use the logic that in an adder circuit the delay appears mainly because of the carry propagation and also there is a lot of power dissipation. Design of ETA is done using backend tool under real time simulation conditions and then compares the performance of the ETA in terms of accuracy, delay and power consumption with that of conventional adders. The proposed architecture is then implemented using FPGA.

This paper presents a novel method for convolution of two finite length sequences using hardware description language(VHDL). Convolution is widely used in digital signal processing. The proposed design replaces conventional multiplier with reversible Vedic multiplier. The proposed design consumes only less area and have higher speed than existing method. Vedic mathematics is world renowned for its quicker mental calculation approach. Urdhva Tiryakbhyam Vedic multiplier is efficient in terms of both power and speed. The comparison of existing method with conventional is done using XILINX software.

Data that is either transmitted over communication channel (e.g. bus) or stored in memory is not completely error free. RAM memory cell contents can change spuriously due to some electromagnetic interference. In magnetic storage devices such as disks, magnetic flux density increases could cause one or more bits to flip (change that value). Exposure to high speed α ray particles is a prominent problem in all the semiconductor memories used for various communication applications. So, in this paper, an error detection and correction method to protect the RAM against the errors is proposed. This method is based on 2-d parities. The parity bits are calculated at the transmitter end for each row, column and diagonal in slash and backslash directions in a memory array. The parities are regenerated at the receiver end. The comparison of transmitted and received parity bits detects the error. As soon as the error is detected, the code corrects the detected error. This method is a promising technique to detect and correct errors in semiconductor memories in presence of large electromagnetic interference with less computational complexity.

Recently high performance and low power consumption custom memory design system is the crucial innovation for wireless embedded devices. In this paper we have implemented MIPS based memory architectural design and analyze its simulation efficiency. Low power and high performance embedded devices such as mobile, wifi devices implemented with MIPS architecture design that reduces the access time and increases the system performance. Existing CAM cell design also reduces the access time as in efficient manner. We have analyzed CAM architecture design with xup-5 FPGA environments and analyze CAM cell efficiency. MIPS RF memory has implemented for various high performances ASIP design architecture and embedded devices.

Random numbers are used for many purposes like generating data encryption keys, simulating and modeling complex phenomena and for selecting samples randomly from larger datasets. They can also used in literature, music and popular for games and gambling. While discussing about single numbers, a random number is one that is drawn from a set of possible values, each of which is equally probable, i.e. uniform distribution. When we are discussing a sequence of random numbers the number drawn must be statistically independent of the others. There are various methods for the generation of Random numbers. There are two types of Random number generators they are Pseudo random number Generator (PRNG) and True Random Number Generator (TRNG). Numbers generated from True Random Number generator will not repeat and are Cryptographically Secured. These are also known as cryptographically secured Pseudo random Numbers (CSPRNG). The sources of Randomness in TRNG are physical phenomena like Lightning, Radio Active Decay, and Thermal Noise etc. In this paper generation of Cryptographically Secured Pseudo Random Numbers using Blum Blum Shub Generator is explained. It was implemented on Virtex-V FPGA using VHDL Programming Language and the Simulation was done on XILINX ISE 12.4i.

The addition of two binary numbers is the most fundamental and widely used arithmetic operation. This operation is used in microprocessors, digital signal processors, data processing application specific integrated circuits and many more. ETA (Error Tolerant Adder) is an efficient adder which speeds up binary addition. There is a huge improvement in the power and speed when we use an ETA. For increasing the speed and decreasing the power dissipation, we use the logic that in an adder circuit the delay appears mainly because of the carry propagation and also there is a lot of power dissipation. Design of ETA is done using backend tool under real time simulation conditions and then compares the performance of the ETA in terms of accuracy, delay and power consumption with that of conventional adders. The proposed architecture is then implemented using FPGA.

JPEG 2000 has high levels of computational complexity due to the presence of entropy encoder block. It takes large amount of times to encode an image using the algorithm with traditional CPUs. This paper focuses on implementing the Bit Plane Coder (BPC) and the MQ coder of the Embedded Block Coding with Optimized Truncation (EBCOT) algorithm using GPU which is used for implementing algorithms with high computational complexity. The serialized structure of the encoder was parallelized for implementation in GPU. The results were found to be at least 4 times faster than any other existing implementation on GPU. The BPC takes only 3.01 ms for processing a 512 x 512 sized image achieving a frame rate of 300 fps and whereas the serialized architecture of MQ coder takes 20.63 ms time.

Increasingly, soft processors are being considered for use within FPGA-based reliable computing systems. In an environment in which radiation is a concern, such as space, the logic and routing (configuration memory) of soft processors are sensitive to radiation effects, including single event upsets (SEUs). Thus, effective tools are needed to evaluate and estimate how sensitive the configuration memories of soft processors are in high-radiation environments. A high-speed FPGA fault injection system and methodology were created using the Xilinx Radiation Test Consortium's (XRTC's) Virtex-5 radiation test hardware to conduct exhaustive tests of the SEU sensitivity of a design within an FPGA's configuration memory. This tool was used to show that the sensitivity of the configuration memory of a soft processor depends on several variables, including its microarchitecture, its customizations and features, and the software instructions that are executed. The fault injection experiments described in this thesis were performed on five different soft processors, i.e., MicroBlaze, LEON3, Arm Cortex-M0 DesignStart, OpenRISC 1200, and PicoBlaze. Emphasis was placed on characterizing the sensitivity of the MicroBlaze soft processor and the dependence of the sensitivity on various modifications. Seven benchmarks were executed through the various experiments and used to determine the SEU sensitivity of the soft processor's configuration memory to the instructions that were executed. In this thesis, a wide variety of soft processor fault injection results are presented to show the differences in sensitivity between multiple soft processors and the software they run.