FIFO

With staff productivity and retention a crucial factor in the longevity of Australia’s mining industry, some mining companies are increasing their focus on the health and well-being of their people, to minimise the risks of deteriorating health in an ageing workforce. Many of Australia’s mining operations rely heavily on long distance commuter (LDC) rosters, which are argued to have a signifi cant impact upon worker health, wellbeing and lifestyle choices. The potential impact of workforce health on mine safety performance, efficiency and operating practice is an interesting additional line of enquiry. Food choice, exercise and recreation initiatives offer living and working conditions that ‘empower healthy choices’ in the shift worker community, but do not guarantee improved worker wellbeing. This paper explores first-hand the experiences of one individual over two and a half years of employment at different mine sites, under different shift conditions and across different operating crews. Novel insights and recommendations concerning the LDC lifestyle are offered through integrating reflections on one individual’s fly-in, fly-out (FIFO) experiences in open pit mining operations from personal, family, professional and academic perspectives.

Indigenous employment, the mining boom and official statistics 'The misery of being exploited by capitalists', wrote economist Joan Robinson, 'is nothing compared to the misery of not being exploited at all'. This assumption underlies much of the current debate about Indigenous involvement in the resource extractive industries, a thesis put perhaps most prominently by Marcia Langton in her 2012 Boyer Lectures 'The Quiet Revolution: Indigenous People and the Resources Boom'. In her lectures, Langton charts a shift in Indigenous relations with the mining industry, from one of antagonism to one of mutual benefits. In particular, Langton argues that mining employment 'offers an alternative to the welfare transfers on which many remote and regional Aboriginal communities depend'. According to this thesis, the Indigenous mining-employment boom is caused by many factors including changing corporate cultures, recently recognised native title rights, shortages in the remote labour force and of course a mining boom that has coincided with a period of strong non-mining macroeconomic activity.

Problem Name: First-Come First-Serve (FCFS) process scheduling algorithm without arrival time. Objectives: To implement FCFS scheduling algorithm using a FIFO queue which is non-preemptive that is if a process started then CPU executes the process until it ends. Introduction: The FCFS is a non-preemptive scheduling algorithm in which a process is automatically queued and processing occurs according to an incoming request or process order implementation of the FCFS policy is managed with a FIFO queue. When a process enters the ready queue, its PCB is linked onto the tail of the queue. When the CPU is free, it is allocated to the process at the head of the queue.

In the earlier era of electronics the UART (Universal asynchronous receiver/transmitter) played a major role in data transmission. This UART IP CORE provides serial communication capabilities, which allow communication with modems or other external devices. This core is designed to be maximally compatible with industry standard designs[4]. The key features of this design are WISHBONE INTERFACE WITH 8-BIT OR 32-BIT selectable data bus modes. Debug interface in 32-bit data bus mode. Register level and functional compatibility. FIFO operation. The design is verified using UVM methodology. The test bench is written with regression test cases in order to acquire maximum functional coverage.

Distributed Denial of service (DDoS) attacks affect millions of users and businesses across the globe every year. With the ever-increasing sophistication and complexity of these attacks services and resources are at the mercy of the attacker, with very little in the way of prevention against these kinds of attacks. Voice over internet protocol (VoIP) and Video Conferencing are most affected by these attacks because they rely on real-time packet delivery whereas applications such as Web browsing can be resent. For the client to be satisfied by application performance, Quality of Service (QoS) needs to be measured. This is usually defined in a service level agreement and is the overall quality of an application. For instance, if the QoS of VoIP is not maintained, then the call quality is severely degraded, and thus the call session is lost.

FIFO is implies first in first out using queue methodology for memories read and write of any information and data using some control logic. The whole work of FIFO is fully dependent on the control circuitry and clock domain. It is often used to control the flow of data from source to destination by the transition of every clock. Basically FIFO differentiate by clock domain either Synchronous or Asynchronous. There are various methods to designing and synthesized FIFO but here fully focused on the memory which is used to store the data in domain of clock either sync. and async. or single and multiple clock cycles. This paper will differentiate the design, synthesize and analyze a Synchronous FIFO using Register file memory by older version of Synchronous FIFO. In this paper, conclude the effect of using register file instead of random access memory for storage of data in FIFO memory. This work shows change the parameters like on-chip components (clock, signal, input and outputs etc), clock domain, type of resources, and how to minimize and optimize hierarchy of the device.The RTL description for the FIFO is written using Verilog HDL (hardware description language). And design is simulated and synthesizes in Xilinx ISE Design suit 12.4.The RTL code simulated in ISim Simulator.

This paper provides a method for approzimating the probability distributions of stationary statistics in FIFO single server queues. The method is based on the Wiener Hopf factorization technique, and is applied to semi-Markov queues where the underlying state space is of unlimited size. A particularly important case is a model for a statistical multiplezer where the net input process forms a stationary ergodic Gaussian discretetime stochastic process.

With the shrinking technology, reduced scale and power-hungry chip IO leads to System on Chip. The design of SOC using traditional standard bus scheme encounters with issues like non-uniform delay and routing problems. Crossbars could scale better when compared to buses but tend to become huge with increasing number of nodes. NOC has become the design paradigm for SOC design for its highly regularized interconnect structure, good scalability and linear design effort. The main components of an NoC topology are the network adapters, routing nodes, and network interconnect links. This paper mainly deals with the implementation of full custom SRAM based arrays over D FF based register arrays in the design of input module of routing node in 2D mesh NOC topology. The custom SRAM blocks replace D FF(D flip flop) memory implementations to optimize area and power of the input block. Full custom design of SRAMs has been carried out by MILKYWAY, while physical implementation of the input module with SRAMs has been carried out by IC Compiler of SYNOPSYS.The improved design occupies approximately 30% of the area of the original design. This is in conformity to the ratio of the area of an SRAM cell to the area of a D flip flop, which is approximately 6:28.The power consumption is almost halved to 1.5 mW. Maximum operating frequency is improved from 50 MHz to 200 MHz. It is intended to study and quantify the behavior of the single packet array design in relation to the multiple packet array design. Intuitively, a common packet buffer would result in better utilization of available buffer space. This in turn would translate into lower delays in transmission. A MATLAB model is used to show quantitatively how performance is improved in a common packet array design.

b) Weighted-average process costing is one of the methods which used for calculating product costing. It multiplies the related product costs and corresponding units of a certain period, then divides the result by all the units, this result is the weighted-average cost of the inventories (Lanen, Anderson&Maher, 2014). First-in, first-out (FIFO) process costing is the other measure that the price of those products that brought in the storage first, is the costing price of the first ones sold. (Lanen, Anderson&Maher, 2014). When we start to assign costs to products using process costing, we can find a lot of similarities and differences between the weighted-average and FIFO process costing inventory method. Similarities: 1. First of all, they both follow five steps: (1) To record the related resources. (2) To count the quantities of the inventories. (3) To distinguish the related inventories' costs each. (4) To identify the costs of the related inventories per equivalent unit after the corresponding calculate methods. (5)To determine the final inventory cost.

Network-on-chip (NoC) architecture provides the communication infrastructure for system-on-chip (SoC) design. The architecture, size, and algorithm dominate the performance of NoC and influence on the design of arbiters in the switch. FIFO buffers are essential components of network switches-buffers have been estimated to be the single largest power consumer for a typical switch in an on-chip network. The presented work has design a 128-bit FIFO to store 128-bit flits in the NoC. The proposed architecture of FIFO is implemented in RTL model using verilog language. The FIFO has achieved a maximum operation frequency 675 MHz on Xilinx Vertex-6 6VLX75TFF484 device.

The focus of this Paper is the actual implementation of Network Router and verifies the functionality of the four port router for network on chip using the latest verification methodologies, Hardware Verification Languages and EDA tools and qualify the IP for Synthesis an implementation. This Router design contains three output ports and one input port, it is packet based Protocol. This Design consists Registers and FIFO. For larger networks, where a direct-mapped approach is not feasible due to FPGA resource limitations, a virtualized timemultiplexed approach was used. Compared to the provided software reference implementation, our direct-mapped approach achieves three orders of magnitude speedup, while our virtualized time multiplexed approach achieves one to two orders of magnitude speedup, depending on the network and router configuration.

With the evolution of traffic applications such as VoIP or Video conferencing, their demand for traffic consumption is increasing. With this higher quality demand the risk of poor levels of QoS is predicted. With the combination of the increased use of these applications and their higher quality resource usage, network congestion has become an increasing problem. Network congestion is when there are insufficient networked resources such as link bandwidth to deal with the flow of the traffic present within the network. This presents a significant danger as it increases packet loss, provides queueing delay and as a result will drop the level of QoS which will make applications performance appear slow and for realtime multimedia applications such as Video Conferencing, the call session would become unstable as static, loss of video and words would be continuous. Therefore, it is vital that proper QoS mechanisms be in place for networks to help elevate and mitigate any network congestion to maintain a high level of QoS. These QoS mechanisms can manage congestion by using priority and buffer systems that specify how each type of traffic is handled.

Self-timed mesochronous interconnection scheme is presented for the inte$ace between synchronous modules. It consists of a self-timed FIFO and a local clock control circuit placed between synchronous modules. The self-timed FIFO receives a data stream and holds it until the Jirst data is synchronized at the receiving module. After the synchronization, the clock input to the receiving module is available through the local clock control circuit. The interconnection scheme operates regardless of the amount of the clock skew between the modules. An experimental design is presented that demonstrates the validity of the method. 122 O-8186-7502-0/96 $5.00 0 1996 IEEE

Wireless sensor network(WSN) consist of compact distributed self-organizing wireless nodes with small amount of CPU memory, low processing power and low battery capacity. The wireless nodes generates different types of data packets such as real time and non-real time data packets because it sense environmental situations. WSN uses most existing packets scheduling system i.e. First come first serve(FCFS).In FCFS concept the data packets which enter the node first will leave the node first. In this process there might be starvation of real time data packets because data packets are processed according to the time but they are not processed according to priority. Scheduling different type of package in WSN is highly important since it ensure deliver of different type of packets based on their priority and fairness with minimum latency.

Lean manufacturing is the manufacturing philosophy and the system that was given by the Toyota, Japan and now the many of the manufacturers are using these techniques in industries. “Lean is simply a systematic technique or approach to identify and eliminating the waste through the continuous improvement by flowing the product at the pull of the customer in pursuit of the perfections. The main aim is to eliminate the wastages in every area of the production including the customer relations and the product design and suppliers”. Lean tools and approach are very much popular in the automobile component manufacturing which is improving the growth initiatives in the automobile industry in last two decades. In automobile these lean tools like JIST,5S, Six Sigma, FIFO, LIFO, Continuous Improvement, JIS, Kanban processes also helps in the rapid development and growth in assembly line and overall production and growth specially in automobile sector. Nowadays almost 70% to 80% improvement in most of industrial growth is due to the approach of lean manufacturing.

The top module or sub-module of a project in the Vivado Design Suite can be packaged as an IP and it is available in the IP repository of the Vivado IP catalog for reuse. This paper exhibit how chosen modules in an RTL project can be packaged as IP for reuse. IP packaging is IP-XACT-compliant, where IP-XACT is a XML format that defines and describes electronic components and their designs. IP packaging also allows for different file sets to be part of the package. These file sets include simulation, test bench, example design, XDC constraints, and documents. Objectives  Select a sub module in an RTL project and begin IP packaging  Select a repository location to create the new IP designation  State basic options for IP packaging  Define IP interfaces from the ports  Specify IP customization parameters  Add or remove files to/from many of the possible file groups throughout during packaging I. INTRODUCTION The Vivado Design Suite provides an IP-centric design flow that helps you to quickly turn the designs and algorithms into reusable IP. The Vivado IP Catalog is a united IP repository that provides the framework for the IP-centric design flow. This catalog consolidates IP's from all sources including Xilinx® IP, thirdparty IP, and end-user designs targeted for reuse as IP into a single environment. The Vivado IP packager tool is a unique design reuse feature, which is based upon the IP-XACT standard. The IP packager tool provides you with the facility to package a design at any phase of the design flow and deploy the core as system-level IP. In this paper, I define a new custom IP from an active Vivado project, using the Create and Package IP wizard. Start with an existing design project in the Vivado IDE, define identification information for the new IP, add documentation to support its use, and add the IP to the IP Catalog. After packaging, you verify the new IP through synthesis in a separate design project. The project contains Verilog source files for a simple UART interface. The existing design includes timing constraints defined in an XDC file (uart_top.xdc). These constraints were defined for the UART design as a standalone design. However, when packaged as an IP, the design inherits some of the needed constraints from the parent design. In this case, you must modify the XDC file to separate constraints the IP requires when used in the context of a parent design, and the constraints the IP requires when used out-of-context (OOC) in a standalone capacity. This requires splitting the current XDC file. We should prepare the design constraints prior to packaging the design for inclusion in the IP catalog; however, we can also perform these steps after packaging the IP.

The process of hardware – software co-design of satellite data acquisition system is described. The hardware components are targeted to execute on a reconfigurable hardware coprocessor which communicates with a host computer that executes the software tasks. Control of the data flow between device interfaces, processing blocks and memories in a data acquisition system is complex in hardware implementation.. With growing computational needs, high design and NRE costs of ASICs, FPGA based co-processor has become a viable alternative. The main objective of our co-design methodology is the usage of hardware designing of algorithms, simulation and synthesis.

Many Australian families experience a parent working away from home on a frequent or prolonged basis in the primary industries, transport or sales sectors or through deployment within the Australian Defence Force (ADF). Researching how these families are affected, and how they cope, survive, and sometimes thrive, during these challenging times offers insights into the ways early childhood educators can promote family resilience. By following these eight steps, educators can partner effectively with these families to ensure they are emotionally and physically supported.

Workers in the Northern Russian oil and gas industry often describe their lives as “extreme.” The adjective refers to working in a physically challenging environment – be it the harsh climate, the hard industrial work, or the long commute to and from work. It also reflects the psychological pressure of living together with colleagues in small closed camps, the lack of privacy, and the hardship of being away from family for long periods of time. Those who have already
spent decades on long-distance commuting (LDC), also called fly-in/fly-out work (FIFO), are now accustomed to this lifestyle; it has become their new “normal.”
In contrast, many new workers who have just started the arduous routine doubt whether this is a sustainable way to earn a livelihood and quit after a few years – or even a few shifts. Not everyone has the adventurous spirit and mental toughness to commute long-term.
This chapter explores how the working conditions in the petroleum industry and the living conditions in the camps in the Russian Arctic and sub-Arctic regions affect the mobility potential of construction and operation workers in the oil and gas sector. It seeks to identify what circumstances enable individuals to embrace a long-term, sustainable career in this difficult environment.

"Within the Australian mining industry, Fly-
in/Fly-out (FIFO) and Drive-in/Drive-out (DIDO) are common types of employment for people working in remote areas. While the number of such FIFO/DIDO employees has increased over recent years, research into the wellbeing of these employees is limited (Sipek, 2012). This paper reports on a recent Australian study of FIFO/DIDO employees, which explores the lifestyle of these employees and the factors associated with their psychosocial wellbeing, with the aim of identifying the potential risk factors for psychological distress amongst the FIFO/DIDO population. The survey of Australian FIFO/DIDO employees was undertaken in 2012, with participants recruited using a snowballing technique and through social networking sites and forums. In total, 150 FIFO/DIDO employees completed the anonymous questionnaire, which included demographic and lifestyle items as well as a range of measures assessing aspects of psychosocial wellbeing. A key finding of this study is that 72% of participants expect to cease FIFO/DIDO employment within the next five years. Additionally, severe to extremely severe levels of depression, anxiety and stress symptomology was reported by 26%, 24% and 36% of participants, respectively. The participants’ employment decisions were found to be related to their psychosocial wellbeing as well as to site and employment conditions. As such, understanding the factors affecting employee social and psychological wellbeing provides further insight into employee turnover and will better equip companies to manage the recruitment and retention of FIFO/DIDO employees. "

This paper studies the performance of Multiprotocol Label Switching (MPLS)networks for VoIP applications when applying both Traffic Engineering (TE) signal protocols and Quality of Service (QoS) algorithms. The used QoS algorithms are First-In First-Out FIFO), Priority Queuing (PQ), and Weighted Fair Queuing (WFQ). The study addresses different audio codecs including PCM (64 Kbps), GSM FR (13 Kbps), G.723.1 (5.3 Kbps), G.726 (16 Kbps), G.728 (16 Kbps), G.729 (8 Kbps) and IS-641(7.4 Kbps).In term of number of maintained calls, the results show that applying QoS algorithms improves the performance of the MPLS network with RSVP TE signal protocol more than that with CR-LDP TE signal protocol. The highest number of calls is achieved when applying both RSVP TE signal protocol with WFQ algorithm. In terms of voice end-to-end delay, voice packet delay variation, and voice jitter, the PQ algorithm gives the lowest values when applied with either CR-LDP or RSVP TE signal protocols.

El propósito principal de la construcción de un sistema operativo de características didácticas, es la de permitir que los alumnos de materias afines puedan comparar el comportamiento de diferentes algoritmos, en primera instancia, de administración de procesos, utilizando para ello una estructura de parametrizaciones en tiempo de ejecución. Esto les permitirá realizar pruebas del comportamiento de los diferentes algoritmos en el manejo de procesos pudiendo realizar análisis de los puntos de conflicto, tan difíciles de experimentar a través de desarrollos manuales La estructura para la resolución de conflictos se basa en la jerarquía excepción, interrupción y llamadas al sistema especificando en que momentos un sistema operativo puede modificar la misma para obtener una mejor performance de acuerdo a nivel de aceptación que se espera del mismo por parte de los diferentes usuarios

Lean manufacturing is now one of the most powerful manufacturing control systems in the current trend. In present competitive and challenging market, industries needs to improve their strength and must concentrate on to their process flows. Lean manufacturing is the solution to improve their quality and increasing profit for manufacturing over the international market. Lean manufacturing provides varieties of tools and strategies which can help in identification of waste, reduction or elimination of waste, manufacturing product with better quality, lowering the product cost, reducing human effort and reducing product manufacturing time. This paper demonstrates various lean manufacturing. Lean manufacturing is a precise approach for economical utilization of raw product and eliminating waste through continuous improvement, and aimed to provide qualitative product to the customers. Lead time is the time spent between the original customer order and final delivery of the product. Project work is being carried out at XYZ organization in Gaziabad,U.P,India. Lean manufacturing is a production practice that considers expenditure of resources for any goal other than creation of value for the end customer to be wasteful and thus a target for elimination. Lead time is calculated by adding value added time and non-value added time. Delivery valve is a non-return valve between the high pressure for the fuel injection system and pump plunger. On observing the present system of delivery valve production the current lead time was calculated and was found to be 14.60 days. The lean tools that are applied in this project are First-In-First-Out (FIFO), a method for organizing the component buffer where the oldest entry or bottom of the stack is processed first which eliminates inventory which in turn reduces the lead time and Value Stream Mapping (VSM) to map the present and the future state. Application of these lean tools has resulted in the reduction of lead time by one day i. e.13.60 days.

In Networks-on-chip, increasing the depth of routers' buffers even by a few stages can have a significant effect on average latency and saturation threshold of the network. However, the price to pay could be high in terms of power and silicon area. In this paper, we propose a low power, high throughput asynchronous FIFO suitable for buffers of GALS NoC routers. We consistently compare the performance with regards to power, area and throughput of our FIFO with some different FIFO structures, by exploring their design trade-offs with various number of stages and for different data lengths. These structures are simulated in 90nm CMOS technology with accurate spice simulations, where results show a low power consumption and latency, with a higher throughput. Finally, a back-annotated HDL model of a 4x4 mesh network, wherein a fully asynchronous router is implemented, shows better average latency, saturation threshold and power tradeoffs, using the proposed FIFO.

In multi-hop networks, packet schedulers at downstream nodes have an opportunity to make up for excessive latencies due to congestion at upstream nodes. Similarly, when packets incur low delays at upstream nodes, downstream nodes can reduce priority and schedule other packets first. The goal of this paper is to define a framework for design and analysis of Coordinated Network Scheduling (CNS) which exploit such inter-node coordination. We first provide a general CNS definition which enables us to classify a number of schedulers from the literature including, FIFO+, CEDF, and work-conserving CJVC as examples of CNS schedulers. We then develop a distributed theory of traffic envelopes which enables us to derive end-to-end statistical admission control conditions for CNS schedulers. We show that CNS schedulers are able to limit traffic distortion to within a narrow range resulting in improved endto-end performance and more efficient resource utilization. ¥ § ©

We present an apparatus used to distribute a timing reference or clock across the extent of a digital system. Selftimed circuitry both generates and distributes a clock signal, while using less power and less skew compared to a clock tree. HSpice simulations in a 180nm CMOS process comparing the Distributed Clock Generator presented in this paper and an H-tree clock distribution system, each clocking a 16mm × 16mm area suggests a 30% power savings. Also worst case skew was reduced from 27ps to 2ps while using a clock period equivalent to 9 FO4 gates.

First-in first-out memories (FIFOs) have progressed from objectively simple logic functions to highspeed
buffers combining large blocks of SRAM. FIFOs are often used to carefully pass data from one clock
dominion to another asynchronous clock dominion. Using a FIFO to pass data from one clock domain to another
clock domain requires multi- asynchronous clock design techniques. This concept will detail one method that is
used to design, synthesize and analyze a safe FIFO between different clock domains using Memory counter that
are synchronized into a different clock domain before testing for "FIFO full" or "FIFO empty" conditions. The
fully analysed, synthesized counter can be included in FIFO.

WSN is a distributed network that consists of great amount of sensor nodes and has the capacity of sensing, processing and transmitting the partially processed and required data only. Sensor nodes have a tiny size, low cost but along with it the constraints of sensor node is they have limited memory, power source which is irreplaceable so power conservation should primarily focused by sensor network protocols. Cloud computing is an on interest administration in which shared assets, data, programming and different gadgets are given by the customers prerequisite at explicit time. The proposed model deals with environmental application where detection of forest fire is analyzed by taking parameters such as temperature, humidity, wind speed and time etc. using fuzzy logic. By earlier detection of fire in forest, it helps to prevent huge loss of living organism, infrastructure and property. After detection, the proposed MSA (Modified Sleep Awake) model work is prolonging lifetime of WSN in forest fire application using selective sleep awake approach. Cloud computing exploits the cloud to share and process the sensory data as collected by WSN anytime and anywhere. Sensory data collected from different sensors is decomposed to the base station and is transferred to the cloud gateway, as Cloud provides capacity of storage through which internet users communicate with cloud and access the data from cloud from anywhere at any time. The resource allocation problem is the major problem for a group of cloud user requests. To implement the Efficient Enhanced Sleep Awake Scheduling using Fuzzy logic and Neural Network, MATLAB tool box is used and different parameters are calculated with different input values. The proposed model provides best results when compared to existing work.

This paper describes about the design methodology for reducing router power consumption with the aid of RTL clock gating technique. It causes inactive clocked elements to have clock gating logic (automatically by using cadence tool) which reduces power consumption on those elements to zero when the values stored by those elements are not changing. This technique allows a variety of features such as easily configurable, automatically implemented clock gating which allows maximal reduction in power requirements with minimal designer involvement and software involvement. In this paper, source code was written in Verilog (Hardware Descriptive language) and it was synthesized in Xilinx 9.1i version, simulated in Modelsim 6.6 version and clock gating was applied by using Cadence.

El propósito principal de la construcción de un sistema operativo de características didácticas, es la de permitir que los alumnos de materias afines puedan comparar el comportamiento de diferentes algoritmos, en primera instancia, de administración de procesos, utilizando para ello una estructura de parametrizaciones en tiempo de ejecución. Esto les permitirá realizar pruebas del comportamiento de los diferentes algoritmos en el manejo de procesos pudiendo realizar análisis de los puntos de conflicto, tan difíciles de experimentar a través de desarrollos manuales La estructura para la resolución de conflictos se basa en la jerarquía excepción, interrupción y llamadas al sistema especificando en que momentos un sistema operativo puede modificar la misma para obtener una mejor performance de acuerdo a nivel de aceptación que se espera del mismo por parte de los diferentes usuarios

In many applications the traffic traversing the network has inter-packet dependencies due to application-level encoding schemes. For some applications, e.g., multimedia streaming, dropping a single packet may render useless the delivery of a whole sequence. In such environments, the algorithm used to decide which packet to drop in case of buffer overflows must be carefully designed, to avoid goodput degradation.

Long Term Evolution (LTE) network deploys Orthogonal Frequency Division Multiple Access (OFDMA) technology for downlink multi-carrier transmission. To meet the Quality of Service (QoS) requirements for  LTE networks, packet scheduling has been employed. Packet scheduling determines when and how the user’s packets are transmitted to the receiver. Therefore effective design of packet scheduling algorithm is an important discussion. The aims of packet scheduling are maximizing system throughput, guaranteeing  fairness among users, and minimizing either or both Packet Loss Ratio (PLR)and packet delay. Inthis paper, the performance of two packet scheduling algorithms namely Log Maximum-Largest Weighted Delay First (LOG-MLWDF) and Max Delay Unit (MDU), developed for OFDM(Orthogonal Frequency Division  Multiplexing)networks, has been investigated in LTE downlink networks, and a comparison of those algorithms with a well-known scheduling algorithm namely Maximum-Largest Weighted Delay First(MLWDF) has been studied.The performance evaluation was in terms of system throughput, PLR and  fairness index. This study was performed for both real time (voice and video streaming)and non-real time (best effort)perspectives. Results show that for streaming flows,LOG-MLWDF shows best PLR  performance among the considered scheduling schemes, and for best effort flows, it outperforms the other two algorithms in terms of packet delay and throughput.

A linear sorter based on a first-in first-out (FIFO) scheme is presented. It is capable of discarding the oldest stored datum and inserting the incoming datum while keeping the rest of the stored data sorted in a single clock cycle. This type of sorter can be used as a co-processor or as a module in specialized architectures that continuously require to process data for non-linear filters based on order statistics. This FIFO sorting process is described by four different parallel functions that exploit the natural hardware parallelism. The architecture is composed of identical processing elements; thus it can be easily adapted to any data lengths, according to the specific application needs. The use of compact identical processing elements results in a high performance yet small architecture. Some examples are presented in order to understand the functionality and initialization of the proposed sorter. The results of synthesizing the proposed architecture targeting a field programmable gate array (FPGA) are presented and compared against other reported hardware-based sorters. The scalability results for several sorted elements with different bits widths are also presented.

http://yukonresearch.yukoncollege.yk.ca/resda/wp-content/uploads/sites/2/2014/05/LACE-folder.pdf

Project: http://www.resda.ca/labour-mobility

Community presentation of results from the research project LACE - Labour mobility and community participation in the extractive industries in the Yukon/Canada
Mayo, Yukon (CAN) Na Cho Nyak Dun First Nation

in the Village of Mayo, October 5th, 2015

This paper provides a method for approzimating the probability distributions of stationary statistics in FIFO single server queues. The method is based on the Wiener Hopf factorization technique, and is applied to semi-Markov queues where the underlying state space is of unlimited size. A particularly important case is a model for a statistical multiplezer where the net input process forms a stationary ergodic Gaussian discretetime stochastic process.

Many Australian families experience a parent working away from home on a frequent or prolonged basis in the primary industries, transport or sales sectors or through deployment within the Australian Defence Force (ADF). Researching how these families are affected, and how they cope, survive, and sometimes thrive, during these challenging times offers insights into the ways early childhood educators can promote family resilience. By following these eight steps, educators can partner effectively with these families to ensure they are emotionally and physically supported.

We consider exible manufacturing systems using the`First Come, First Served' (FCFS or FIFO) scheduling policy at each machine. We describe and discuss in some detail simple deterministic examples which have adequate capacity but which, under FCFS, can exhibit instability: unboundedly growing WIP taking the form of a repeated pattern of behavior with the repetitions on an increasing scale.

The First-In-First-Out or First Come First Serve (FCFS) job scheduling technique is a non-preemptive scheduling technique often used in many hardware, software and production systems. For improvement of parameters such as reduction of waiting time in queue and turnaround time, a version of FCFS is developed with a dynamic time slice allocation technique based on job length. The same dynamic time slice allocation technique is used to improve the standard preemptive round-robin priority-based job scheduling technique. Finally, this paper endeavours to attempt a comparative study between the FCFS job scheduling technique with dynamic time slice allocation, and the pre-emptive priority-based job scheduling technique with dynamic time slice allocation, both of which offer better performances than their standard static time slice allocation-based variants.