
Hamid Cheraghi
Address: Iran, Islamic Republic of
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Papers by Hamid Cheraghi
programmable logic devices such as field programmable gate array (FPGA) can be used
to integrate large amounts of logic in a single IC. This work, proposes a developed
method to design PD controller (PDC) with optimal- gains using FPGA. The method
used to design PD controller is to design it as digital design Proportional and Derivative
controller in parallel through the summer. The proposed design is 32-bits FPGA-based
controller (32PDC), which uses 32-bits for each input/output variable. The single joint of
robot is used to test the controller in simulation environments, using VHDL code for the
purpose of simulation in Xilinx. The same design is coded in MATLAB environment
(MPDC) in order to make a comparison with the proposed FPGA-based design. PDC
needs 16 clock cycles to complete one action with maximum frequency of 108.5 MHz.
32PDC is able to produce an output in 13.24 MHz with the robot system. Therefore, the
proposed controller will be able to control a wide range of the systems with high
sampling rate and 75.545 ns delays.
programmable logic devices such as field programmable gate array (FPGA) can be used
to integrate large amounts of logic in a single IC. This work, proposes a developed
method to design PD controller (PDC) with optimal- gains using FPGA. The method
used to design PD controller is to design it as digital design Proportional and Derivative
controller in parallel through the summer. The proposed design is 32-bits FPGA-based
controller (32PDC), which uses 32-bits for each input/output variable. The single joint of
robot is used to test the controller in simulation environments, using VHDL code for the
purpose of simulation in Xilinx. The same design is coded in MATLAB environment
(MPDC) in order to make a comparison with the proposed FPGA-based design. PDC
needs 16 clock cycles to complete one action with maximum frequency of 108.5 MHz.
32PDC is able to produce an output in 13.24 MHz with the robot system. Therefore, the
proposed controller will be able to control a wide range of the systems with high
sampling rate and 75.545 ns delays.