CMOS Integrated Circuit Design

In this work we present a programmable and reconfigurable
single instruction multiple data (SIMD) visual processor
based on the S-CNN architecture, namely, the Simplicial CNN Digital Visual Processor (SCDVP), oriented to high-performance low level image processing. The cells in the array have a selectable
neighborhood configuration and several registers, which provide
the chip with extended spatial and temporal processing capabilities, in particular optical flow. A prototype 64 64 cell chip with two program memories and a column adder was fabricated in a 90 nm technology, which running at 133 MHz delivers 105.5 GOPS.
The calculation at the cell level is performed with time coded signals and the program memory is located outside the array. This
produces a very efficient realization in terms of area: 53.8 GOPS
per mm , which outperforms all results reported so far. We show
that even after normalization, to account for technology scaling,
the proposed architecture is the most efficient among all reported
digital processors. Computation performance to power ratio also
exceeds all previous results with 817.8 GOPS/W. Experimental results of the working chip are reported.

Design of a low power Successive Approximation Register Analog to Digital Converter (SAR ADC) in 45nm CMOS Technology for biopotential acquisition systems is presented. It is designed by using a high threshold voltage (Vt) cell to reduce power dissipation. A 10-bit SAR ADC is designed and compared with the low resolution SAR ADC and normal threshold voltage (Vt) ADC with respect to power and delay. The results show that high Vt SAR ADC saves power upto 67% as compared to low Vt SAR ADC without any penalty of delay. Other performance metrics studied are the Effective Number of Bits (ENOB) and Signal to Noise Ratio (SNR), Signal to Noise and Distortion Ratio and Spurious Free Dynamic ratio.

We describe an approach to investigating design cognition which involved comparing prescriptive theories of good design practice with observations of actual design behaviour. The tenet of prescriptive theory which formed the focus of the research is the idea that designers should generate and evaluate multiple design alternatives in order to increase the chances of attaining better design solutions than might arise if they fixated upon an initial solution. Our study focused upon six professional electronic engineers attempting a novel integrated-circuit design problem. Verbal-protocol data revealed: (i) a failure to search for alternative solutions; (ii) a marked inclination to stick with early 'satisficing' solution ideas even when these were showing deficiencies; and (iii) only superficial modelling and assessment of competing alternatives when such options were actually considered. We argue that while minimal solution search in design may sometimes be caused by motivational factors and working-memory limitations, its major determinant relates to inhibitory memory processes that arise subsequent to the recognition-based emergence of familiar design solutions. We conclude by exploring the implications of minimal solution search for design support, with particular reference to an agent-based indexing system which we are developing in order to facilitate the pursuit of design alternatives in engineering contexts. 0 1998 Published by Elsevier Science B.V. solving expertise in general as well as of design expertise in particular [ll. At an applied level, an analysis of solution-development processes in design is vital for devising optimal methods for design education and sound techniques for computer-based design support [2]. A general approach to investigating goal-directed problem-solving processes which has been applied to good effect in many areas of cognitive psychology is to compare normative theories of optimal practice with what people actually do. For example, numerous investigations of decision making (e.g., Ref.

The present paper explores and analyses the performance of Carbon Nano Tube Field Effect Transistor (CNTFET) technology in analog domain through its application as a basic current mirror. 32nm channel length-single walled-one tube CNTFET technology has been assessed and compared with 45nm, 32nm and 22nm NMOS technologies through HSPICE simulations of current mirror circuitry. Different methods of comparison like current error, input-output resistances, AC small signal and transient analysis have been employed which highlight the benefits of CNTFET over NMOS technology and its potential to be used for analog VLSI.

A method is presented in this paper for the design of a high frequency CMOS operational amplifier (Op-Amp) which operates at 3V power supply using tsmc 0.18 micron CMOS technology. The OPAMP designed is a two-stage CMOS OPAMP followed by an output buffer. This Operational Transconductance Amplifier (OTA) employs a Miller capacitor and is compensated with a current buffer compensation technique. The unique behaviour of the MOS transistors in saturation region not only allows a designer to work at a low voltage, but also at a high frequency. Designing of two-stage op-amps is a multi-dimensional-optimization problem where optimization of one or more parameters may easily result into degradation of others. The OPAMP is designed to exhibit a unity gain frequency of 2.02GHz and exhibits a gain of 49.02dB with a 60.5 0 phase margin. As compared to the conventional approach, the proposed compensation method results in a higher unity gain frequency under the same load condition. Design has been carried out in Tanner tools. Simulation results are verified using S-edit and W-edit.

Crosstalk noise is a crucial factor affecting chip performance in deep submicron technologies. Among all possible crosstalk noise sources, clock is the most common aggressor as well as victim. Crosstalk on clock nets can increase clock jitter, which may degrade significantly the system performance. It is therefore imperative to design clock buffers to reduce the coupling effects. In this paper, we address the crosstalk effect on clock networks. We propose an algorithm to size clock buffers for given buffered clock trees such that the induced clock jitter is minimized. Our experimental results show a significant reduction of clock jitter by sizing the clock buffers without increasing the total area of buffer.

A comprehensive simulation study has been conducted to show fine-grain reconfigurability in CMOS circuits using work-function engineering (WFE) on Schottky Barrier (SB) FinFETs for sub-10 nm gate length. The study has three subsections. First, two-transistor (2T) & 4T AOI (and-or-invert)/ OAI (or-and-invert) gates with select bits that allow multiple logic functions are introduced. Secondly, the use of WFE to create ultra-compact reconfigurable logic circuits of fundamental operations (0,1,OR, AND,NAND,NOR,XOR) are explored via novel 2T, 3T and 4T gates. These circuits include one or two select bits that are capable of commanding up to four functions with two inputs. To further illustrate the potential of WFE for reconfigurable logic, novel multi-stage circuits such as compact full-adders are also modelled via TCAD simulations. Power×delay product (PDP) figures and DC gain of the proposed gates are quantified and compared against the CMOS designs with similar functionality. Finally, we also design a novel compact one-bit arithmetic logic unit (ALU) which has seven exclusive logic operations (1, NAND, OR, XOR, NOR, Addition, Subtraction) with three select bits using only 26 SB-FinFETs, saving substantial amount of power and chip area. The trade-offs between the number of metal work-functions used in the designs, circuit complexity and simulated performance metrics are also provided. The comparative simulations between reconfigurable SB-FinFET based designs versus conventional p-n junction FinFET circuits show that WFE can lead to absolutely minimalist reconfigurable CMOS logic blocks using ×3 to ×10 less power and between ×2 and ×15 less area than static CMOS counterparts. Although they suffer greater delays (×2 to ×5), the overall PDP performance remains comparable to conventional CMOS.

Schmitt triggers are electronic comparators that are widely used to enhance the immunity of circuits to noise and disturbances and are inherent components of various emerging applications. Conventional Schmitt triggers, composed of operational amplifiers, suffer from some inevitable drawbacks which are not prominent in CMOS Schmitt triggers. In this paper, a review on the advancement of Schmitt trigger circuits are illustrated in different literatures is discussed with their merits and demerits.

Basic concept of an Amplifier An amplifier is an electronics circuit that produces an output maybe current or voltage which is the magnified version of the input (current or voltage). A function, essentially a signal maybe too small to drive any load, overcome the noise levels and provide a well-defined logical level to a digital circuit or good strong power, current, or voltage value to an analog circuit. The input and output characteristics of an amplifier is generally a non-linear function that is approximated as,

This paper presents the design and implementation of two-stage operational amplifier (Op-Amp). The circuit was designed in PTM 45 nm CMOS process. The design consists of very less number of transistors, hence the design is area optimized. Achieved open loop gain of the amplifier is 76 dB. The unity gain bandwidth (UGB) is 10 MHz and the phase margin is 50 degree with a 10 pF capacitive and 1000K ohm resistive load. High gain enables this circuit to operate efficiently in a closed loop feedback system, whereas high bandwidth makes it suitable for high speed application. The average power consumption of the amplifier is 0.167 μW and slew rate is 8 μ/us.

In this paper CMOS operational amplifier using a two stage has been enunciated for low power device application by using it in subthreshold region. The proposed Op amp shows high gain as well as moderate UGB using capacitor compensation technique circuit. It is operated on rail to rail power supply of ±500mV. This amplifier is highly useful for biomedical application due to low power consumption. The designed operational amplifier gain is 48dB, bandwidth is 29 KHz and phase margin is 61O, and slew rate is 50.6V/µS with 21 nW power consumption.  This circuit is designed using Cadence analog & digital system design tools of UMC 90nm CMOS technology.

In this paper a CMOS NAND gate layout has been designed  and  simulated  using  90  nm  technology.  The  layout has  been  designed  using  two  approaches  namely  fully automatic  and  semicustom.  In  fully  automatic  technique NAND gate schematic is developed which is converted into its equivalent  verilog  file  for  automatic  layout  generation.  In semicustom technique layout has been developed manually to optimize  area  and  power.  It  can  be  observed  from  the simulated  results  that  semicustom  layout  results  in  74% saving in area consumption by consuming almost same power as compared to fully automatic design.

The semiconductor electronics industry has achieved an explosive growth over the last few decades since the invention of monolithic integrated circuits (ICs) in the early 1960's. This progress is a direct consequence of rapid advances ...

Se familiariser avec les notions de layout en technologie CMOS.  Pour  cela  on  utilise  un  logiciel  nommé  MICROWIND.  Celui-ci  permet  de designer et de simuler des structures électroniques intégrées telles que des portes logiques, des bascules ou bien encore des ASICS (CAN, Générateur d’impulsions, …).

In the featuring VLSI era, compact electronic devices are popular. The reliability and durability of such compact devices relies on low power utilization. The purpose of this project was to implement a low power adiabatic Static Random Access Memory (SRAM), with the following objectives-To reduce the power waste by means of stepwise charging using tank capacitors which is an adiabatic way of generating power clock. This method is capable of recuperating the electrical energy back to the source. Further to examine the Static Noise Margin (SNM)a parameter which gives detailed information about the cell stabilityin contrast with conventional 6T, 7T and 8T topologies of SRAM under 180 nm technology. Finally, SNM variations with respect to process parameters are also discussed. All the implementations and analysis were made using CADENCE tool and MATLAB tool.

RF receivers are such electronic devices that discrete radio signals from one another and transform specific signals into respective audio, video, or data formats. It uses an antenna to receive transmitted radio signals and a tuner to separate a specific signal from all of the other signals that the antenna receives. Detectors or demodulators at that moment extract information that was programmed formerly to transmission. There are numerous customs to decode or modulate information. Keywords: CMOS, amplitude modulation (AM), frequency modulation (FM), amplitude shift key (ASK), frequency shift key (FSK), phase shift key

In radio frequency identification (RFID) systems, performance degradation of phase locked loops (PLLs) mainly occurs due to high phase noise of voltage-controlled oscillators (VCOs). This paper proposes a low power, low phase noise ring-VCO developed for 2.42 GHz operated active RFID transponders compatible with IEEE 802.11 b/g, Bluetooth, and Zigbee protocols. For ease of integration and implementation of the module in tiny die area, a novel pseudodifferential delay cell based 3-stage ring oscillator has been introduced to fabricate the ring-VCO. In CMOS technology, 0.18 m process is adopted for designing the circuit with 1.5 V power supply. The postlayout simulated results show that the proposed oscillator works in the tuning range of 0.5-2.54 GHz and dissipates 2.47 mW of power. It exhibits a phase noise of −126.62 dBc/Hz at 25 MHz offset from 2.42 GHz carrier frequency.

A comprehensive simulation study has been conducted to show fine-grain reconfigurability in CMOS circuits using work-function engineering (WFE) on Schottky Barrier (SB) FinFETs for sub-10 nm gate length. The study has three subsections. First, two-transistor (2T) & 4T AOI (and-or-invert)/ OAI (or-and-invert) gates with select bits that allow multiple logic functions are introduced. Secondly, the use of WFE to create ultra-compact reconfigurable logic circuits of fundamental operations (0,1,OR, AND,NAND,NOR,XOR) are explored via novel 2T, 3T and 4T gates. These circuits include one or two select bits that are capable of commanding up to four functions with two inputs. To further illustrate the potential of WFE for reconfigurable logic, novel multi-stage circuits such as compact full-adders are also modelled via TCAD simulations. Power×delay product (PDP) figures and DC gain of the proposed gates are quantified and compared against the CMOS designs with similar functionality. Finally, we also design a novel compact one-bit arithmetic logic unit (ALU) which has seven exclusive logic operations (1, NAND, OR, XOR, NOR, Addition, Subtraction) with three select bits using only 26 SB-FinFETs, saving substantial amount of power and chip area. The trade-offs between the number of metal work-functions used in the designs, circuit complexity and simulated performance metrics are also provided. The comparative simulations between reconfigurable SB-FinFET based designs versus conventional p-n junction FinFET circuits show that WFE can lead to absolutely minimalist reconfigurable CMOS logic blocks using ×3 to ×10 less power and between ×2 and ×15 less area than static CMOS counterparts. Although they suffer greater delays (×2 to ×5), the overall PDP performance remains comparable to conventional CMOS.

Flip  flop  forms  the  very  basic  element  for  the sequential  circuits  which  are  synchronous.  This  paper  talks about  D-Flip  flop,  which  has  been  made  area  and  power efficient  with  the  aid  of  software  tools  DSCH  3.1  and Microwind  3.1.  D-flip  flop  is  implemented  through  Nand gates.  Layout  of  DFF  designed  through  auto  generated  and semi custom is compared, analyses and finally the results are computed  showing  57%  improvement  in  area  and approximately  2  %  reduction  in  power.  CMOS  90nm technology  has  been  used  and  efforts  are  made  to  reduce  area and power.

The purpose of this project is to design a single-stage differential input and single-ended output) Amplifier. 0.35-um CMOS process and a supply voltage of 1.8 V is required in this design. The desired specifications is given.Among the single-stage topologies, the folded-cascade topology is chosen to meet the requirement for a high output swing design.

This work presents a comparative analysis of aging impact in CMOS flip-flops. Five different static flip-flop topologies have been evaluated based on an aging estimation method previously proposed for combinational circuits. BTI, HCI and TDDB are being taken into account in such investigation, considering the individual and combined influences. The operation degradation of each transistor present in the flip-flop circuit is provided by the applied methodology. Moreover, electrical simulations were carried out in order to compare all five flip-flops evaluated in terms of propagation delay increasing. This work demonstrates that the impact of wearout mechanisms might be considered as an important design parameter in the choice of the most appropriate flip-flop in specific applications.

In today’s modern electronics industries energy or power  efficiency  is  most  important  feature  to  increase  the speed,  portability,  reliability,  popularity  and  efficiency  of electronic products. Reduction in power consumption or low power  requirement  for  a  system  adds  features  of  low  cost, high  speed,  more  efficiency  and  reliability.  CMOS technology  is  a  popular  name  in  the  field  of  low  power systems.  In  the  field  of  CMOS  technology  various  methods are used to make the systems more power efficient like, use of  Sleepy  transistors,  Stack  method  in  which  transistor length  or  width  is  increased  to  get  reduction  in  leakage power,  use  of  pre-computation  technique  with  the  use  of BDD  (Binary  Decision  Diagram),  use  of  SRAM  (Static Random Access Memory) for high speed operations. In this paper  we  survey  low  power  systems  in  which  various techniques  are  used  to  reduce  the  power  consumption  in different  circuit  areas  of  the  system  to  get  more  power efficient and cost effective electronic systems.

The circuit topology we used for this project is a  cascode LNA with inductive  source degeneration by using 130nm CMOS technology. Specifications:
The designated Operating Frequency  : 0.8-1.0 GHz
GT:  > 15 dB
S11:  Less than -10 dB
S22:  Less than -10 dB
VDD:  1.1 ~ 1.3 V
IIP3 (input)  :  > -10 dBm
Noise Figure (50 ohms)  :  < 1.5 dB

In  this  paper  an  area  and  power  efficient  98T  Up- Down  counter  design  has  been  presented  by  using  Pass transistor logic designing technique. The proposed Up-Down counter design consist of 53 NMOS and 45 PMOS. Four PTL full  adder  modules  has  been  used  to  design  this  Up-Down counter  which  consumes  less  area  and  power  at  120  nm  as compared  to  CMOS,  TG  and  GDI  full  adder designs.  The proposed Up-Down counter  design is based on this area and power  efficient  10  transistors  PTL  full  adder  module.  The proposed Up-Down counter has been designed and simulated using DSCH 3.1 and Microwind 3.1 on 120nm. For proposed design Power variation with respect to the supply voltage has been  performed  on  BSIM-4  and  LEVEL-3  using  120nm technology.  Results  show  that  Area  of  proposed  PTL  Up- Down counter design is 1288.4 µm2 on 120nm technology. At 1.2V  input  supply  voltage  the  proposed  Up-Down counter design consumes 111µW power at BSIM-4.

In this paper, a design of high performance and low
power 4-bit Manchester carry look-ahead adder is presented
with the help of modified multi-threshold domino logic technique.
The introduced MT-MOS transistors decrease the power
dissipation of adder circuit by reducing sub threshold leakage
current. The FTL dynamic logic is another technique used to
increase operating speed of logic circuit, which evaluates the
computational blocks partially before the input signals are
formalized and then the final evaluation is performed as soon as
the input signals arrive. The pre-evaluation logic reduces
propagation delay into half. The combination of FTL dynamic
logic and MT-CMOS domino logic techniques are yields high
fan-out, high switching frequencies since both lower delay and
dynamic low power consumption in the arithmetic circuits. A
Manchester structure of carry generation employed in carry
look-ahead adder minimizes the area of arithmetic circuit by
decreasing number of transistors. The simulation results have
verified that the proposed techniques are reduced the total power
dissipation up to 40%, 55% of propagation delay than the
standard dynamic domino CMOS technology.

With the advancement of this information technology, a new branch in the field of intellectual property flourished, called as the Layout-Design or the of the semiconductor integrated circuits.

This paper ventures into the registrability of Layout-Designs under the Semiconductor Integrated Circuits Layout Designs Act, 2000 (India) and other international Acts.

The design of a linear integrated Op Amp circuit as an alternative solution to differential equation model of RLC Circuit is presented. The fundamental assumption used in the cascaded Operational Amplifier (Op Amp) design is that Op Amp acts linearly. In this paper, we will examine the behavior of the Op Amp when it is used in the cascaded circuit that is an electrical analog to the differential equation model of RLC circuit, which arises in numerous applications particularly in control and communication systems such as ringing circuits, resonant circuits, filters and oscillators. We will design the cascaded op amp circuit that is analog to differential equation model of RLC circuit and obtain graphical results of output function versus time using PSpice Software Probe. To confirm the validity of the design of a linear integrated Op Amp circuit as an alternative solution to differential equation model of RLC circuit implemented in the PSpice Software, simulation results are compared with RLC circuit where we find good agreement between the theoretical predictions of the differential equation model of RLC circuit and the design of a linear integrated Op Amp circuit.

In the featuring VLSI era, compact electronic devices are popular. The reliability and durability of such compact devices relies on low power utilization. The purpose of this project was to implement a low power adiabatic Static Random Access Memory (SRAM), with the following objectives-To reduce the power waste by means of stepwise charging using tank capacitors which is an adiabatic way of generating power clock. This method is capable of recuperating the electrical energy back to the source. Further to examine the Static Noise Margin (SNM) – a parameter which gives detailed information about the cell stability – in contrast with conventional 6T, 7T and 8T topologies of SRAM under 180 nm technology. Finally, SNM variations with respect to process parameters are also discussed. All the implementations and analysis were made using CADENCE tool and MATLAB tool.

MOSFET (stands for Metal-Oxide-Semiconductor Field Effect Transistor) is one of the most widely used microelectronic devices today. Thus, the understanding of its working principles is very important for the integrated circuits engineer. CMOS (Complementary Metal-Oxide-Semiconductor) Inverter is the device consisting of two complementary MOSFETs of N-type and P-type that performs the inversion operation. During this lab, the characteristics of these devices would be simulated using Verilog-A and SPICE BSIM 3 models.

In  this  paper  VLSI  design  have  been introduce  decrease  the  area  and  power  CMOS  90  nm technology  is  used  for  designing  nor  gate.  The  power consumption and area of nor gate compared in this paper. The  proposed  design reduces the  power consumption  and area.  The  nor  gate  reduces  power  consumption  by  46% and    area  by  67%    .two  design  flow  are  implement,  fully automatic  and  semicustom  .the  semicustom  design  better than  fully  automatic  because  in  this  design  flow modification is done to minimize the power and area.

A method is presented in this paper for the design of a high frequency CMOS operational amplifier (Op-Amp) which operates at 3V power supply using tsmc 0.18 micron CMOS technology. The OPAMP designed is a two-stage CMOS OPAMP followed by an output buffer. This Operational Transconductance Amplifier (OTA) employs a Miller capacitor and is compensated with a current buffer compensation technique. The unique behaviour of the MOS transistors in saturation region not only allows a designer to work at a low voltage, but also at a high frequency. Designing of two-stage op-amps is a multi-dimensional-optimization problem where optimization of one or more parameters may easily result into degradation of others. The OPAMP is designed to exhibit a unity gain frequency of 2.02GHz and exhibits a gain of 49.02dB with a 60.5 0 phase margin. As compared to the conventional approach, the proposed compensation method results in a higher unity gain frequency under the same load condition. Design has b...

In the first laboratory work of Integrated Circuit Design course, we are going to fasten all obtained theoretical knowledge in practice. In other words, we are going to get familiarized with MOSFETS, their operation and related circuits. Moreover, for the first time we will work with software equipment called Tanner EDA, which is widely used in designing and simulation of Integrated Circuits.

To  any  digital  circuit reduction  of  surface  area is one of the important parameter. Very large scale integration VLSI  provides  the  way  to  reduce  the  silicon  area.  In  this paper  area  efficient  design  of  4  bit  full  adder  is  developed. Adder  is  one  important  element  in  computer  arithmetic.  It uses for the addition of binary numbers. To design 4-bit full adder  two  different  methods  are  used  in  this  paper.  First  is fully auto CMOS design and second is semicustom design. In first fully automatic CMOS design schematic and layout of 4- bit  full  adder  are  developed.  In  second  semicustom  design method  layout  of  4-bit  full  adder  is  developed  by  using number  of  fringers.  The  layouts  of  both  techniques  are simulated using 90nm technology. It can be observed from the simulated  results  that  semicustom  layout  results  in  72% reduction  of  silicon  area  as  compared  to  full  automatic CMOS design

Signal & Image Processing : An International Journal is an Open Access peer-reviewed journal intended for researchers from academia and industry, who are active in the multidisciplinary field of signal & image processing. The scope of the journal covers all theoretical and practical aspects of the Digital Signal Processing & Image processing, from basic research to development of application.

Authors are solicited to contribute to the journal by submitting articles that illustrate research results, projects, surveying works and industrial experiences that describe significant advances in the areas of Signal & Image processing.

International Journal of VLSI design & Communication Systems (VLSICS) is a bi monthly open access peer-reviewed journal that publishes articles which contribute new results in all areas of VLSI Design & Communications. The goal of this journal is to bring together researchers and practitioners from academia and industry to focus on advanced VLSI Design & communication concepts and establishing new collaborations in these areas.

Authors are solicited to contribute to this journal by submitting articles that illustrate research results, projects, surveying works and industrial experiences that describe significant advances in the VLSI design & Communications.

The topic of this thesis is efficiency of analog-to-digital converters (ADC) in nano-scale CMOS technology. With downscaling of CMOS technology it is harder to design ADCs. The power supply is reduced due to reliability concerns and the output resistance of transistors is reduced because of shorter channel lengths. Such challenges makes it harder to design ADCs with conventional circuit techniques and ADC architectures.

This paper presents optimized layout of SR flip--flop using NAND gates on 90nm technology. The proposed SR flip-flop has been designed using different approaches. In the first approach layout has been generated using fully automatic technique with the help of SR flip-flop schematic. In second approach layout has been generated manually by using one finger and in the
last approach semicustom layout is further optimized by using two fingers. The area and power consumption of all the designs has been compared and analyzed. It can be observed from the simulated results that SR flip-flop by using two fingers and SR flip-flop by using one finger with semicustom technique consumes  (68.93% , 41.72%) and (51.17%, 37.36%) less (area, power) as compare to the layout that has been generated using fully automatic technique with the help of SR flip-flop  schematic.

This work presents a CMOS technique for designing and implementing a biologically inspired neuron which will accept multiple synaptic inputs. The circuit accepts synapses as inputs and generates a pulse width modulated output waveform of constant frequency depending on the level of activation. Next, the behavior of this implementation has been presented, and the realization of various basic logic gates through this combination has been realized.